1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef N1SDP_SCP_MMAP_H
9 #define N1SDP_SCP_MMAP_H
10 
11 #include <stdint.h>
12 
13 /*
14  * Top-level base addresses
15  */
16 #define SCP_EXPANSION1_BASE          UINT32_C(0x01000000)
17 #define SCP_EXPANSION2_BASE          UINT32_C(0x21000000)
18 #define SCP_SCC_BASE                 UINT32_C(0x3FFFF000)
19 #define SCP_EXPANSION3_BASE          UINT32_C(0x40000000)
20 #define SCP_PERIPHERAL_BASE          UINT32_C(0x44000000)
21 #define SCP_MEMORY_CONTROLLER        UINT32_C(0x4E000000)
22 #define SCP_POWER_PERIPHERAL_BASE    UINT32_C(0x50000000)
23 #define SCP_NOC_GPV_BASE             UINT32_C(0x51000000)
24 #define SCP_SYS0_BASE                UINT32_C(0x60000000)
25 #define SCP_SYS1_BASE                UINT32_C(0xA0000000)
26 #define SCP_PPB_BASE_INTERNAL        UINT32_C(0xE0000000)
27 #define SCP_PPB_BASE_EXTERNAL        UINT32_C(0xE0040000)
28 
29 /*
30  * Peripherals - Timer/Counter
31  */
32 #define SCP_REFCLK_CNTCTL_BASE       (SCP_PERIPHERAL_BASE + 0x0000)
33 #define SCP_REFCLK_CNTBASE0_BASE     (SCP_PERIPHERAL_BASE + 0x1000)
34 #define SCP_WDOG_BASE                (SCP_PERIPHERAL_BASE + 0x6000)
35 
36 /*
37  * Timer Synchronization Module base
38  */
39 #define SCP_TIMER_SYNC_BASE          UINT32_C(0x47000000)
40 
41 /*
42  * CoreSight control base
43  */
44 #define SCP_CS_CNTCONTROL_BASE       (SCP_PERIPHERAL_BASE + 0xA000)
45 
46 /*
47  * Peripherals - Serial communication
48  */
49 #define SCP_UART_BASE                (SCP_PERIPHERAL_BASE + 0x2000)
50 #define DIMM_SPD_I2C_BASE            (0xBC040000)
51 #define SCP_I2C0_BASE                (0x3FFFA000)
52 #define SCP_I2C1_BASE                (0x3FFFB000)
53 #define SCP_I2C2_BASE                (0x3FFFC000)
54 
55 /*
56  * Peripherals - Mailbox communication
57  */
58 #define SCP_MHU_AP_BASE              (SCP_PERIPHERAL_BASE + 0x1000000)
59 #define SCP_MHU_MCP_BASE             (SCP_PERIPHERAL_BASE + 0x1600000)
60 
61 /*
62  * Power control peripherals
63  */
64 #define SCP_PIK_SCP_BASE             (SCP_POWER_PERIPHERAL_BASE + 0x00000)
65 #define SCP_PIK_DEBUG_BASE           (SCP_POWER_PERIPHERAL_BASE + 0x20000)
66 #define SCP_SCP_SENSOR_DEBUG_BASE    (SCP_POWER_PERIPHERAL_BASE + 0x30000)
67 #define SCP_PIK_SYSTEM_BASE          (SCP_POWER_PERIPHERAL_BASE + 0x40000)
68 #define SCP_SENSOR_SYSTEM_BASE       (SCP_POWER_PERIPHERAL_BASE + 0x50000)
69 #define SCP_SENSOR_CLUS0_BASE        (SCP_POWER_PERIPHERAL_BASE + 0x60000)
70 #define SCP_SENSOR_CLUS1_BASE        (SCP_POWER_PERIPHERAL_BASE + 0x80000)
71 #define SCP_PIK_DEBUG_CHAIN_BASE     (SCP_POWER_PERIPHERAL_BASE + 0x500000)
72 #define SCP_PIK_CLUSTER_BASE(n)      ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + \
73                                       ((n) * 0x20000))
74 
75 /*
76  * PPU base address
77  */
78 #define SCP_PPU_SCP_BASE             (SCP_PIK_SCP_BASE + 0x1000)
79 #define SCP_PPU_SYS0_BASE            (SCP_PIK_SYSTEM_BASE + 0x1000)
80 #define SCP_PPU_SYS1_BASE            (SCP_PIK_SYSTEM_BASE + 0x5000)
81 #define SCP_PPU_DEBUG_BASE           (SCP_PIK_DEBUG_BASE + 0x1000)
82 #define SCP_PPU_CLUSTER_BASE(n)      (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
83 #define SCP_PPU_CORE_BASE(n, m)      (SCP_PPU_CLUSTER_BASE((n)) + \
84                                       ((m) + 1) * 0x1000)
85 
86 /*
87  * PCIe & CCIX Peripherals
88  *
89  * SCP memory for PCIe and CCIX APB and AXI Access
90  * (0x6000_0000 - 0x9FFF_FFFF) maps AP memory address
91  * space (0x4000_0000 - 0x7FFF_FFFF)
92  */
93 
94 /*
95  * APB Registers
96  */
97 #define PCIE_RC_CFG_REG_SCP_BASE     UINT32_C(0x80000000)
98 #define PCIE_IP_CFG_REG_SCP_BASE     UINT32_C(0x80800000)
99 #define PCIE_MSG_CFG_REG_SCP_BASE    UINT32_C(0x80850000)
100 
101 #define CCIX_RC_CFG_REG_SCP_BASE     UINT32_C(0x82000000)
102 #define CCIX_IP_CFG_REG_SCP_BASE     UINT32_C(0x82800000)
103 #define CCIX_MSG_CFG_REG_SCP_BASE    UINT32_C(0x82850000)
104 
105 /*
106  * PCIe and CCIX Subordinate AXI space visible to SCP
107  */
108 #define PCIE_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x90000000)
109 #define CCIX_AXI_SUBORDINATE_SCP_BASE UINT32_C(0x88000000)
110 
111 /*
112  * PCIe and CCIX Subordinate AXI in 64-bit space visible to AP
113  */
114 #define PCIE_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x900000000)
115 #define CCIX_AXI64_SUBORDINATE_AP_BASE UINT64_C(0x2900000000)
116 
117 /*
118  * 1MB window into AP memory space
119  * This region enables SCP to access AP's memory region
120  * in terms of 1MB windows.
121  */
122 #define SCP_AP_1MB_WINDOW_OFFSET     0x2B000000
123 #define SCP_AP_1MB_WINDOW_BASE       (SCP_SYS1_BASE + SCP_AP_1MB_WINDOW_OFFSET)
124 #define SCP_AP_1MB_WINDOW_SIZE       0x100000
125 #define SCP_AP_1MB_WINDOW_ADDR_MASK  0xFFFFF
126 #define SCP_AP_1MB_WINDOW_SHIFT      20
127 
128 /*
129  * GIC600 Registers
130  */
131 #define GIC600_GICC_BASE          (SCP_SYS1_BASE + 0x2C000000)
132 #define GIC600_GICH_BASE          (SCP_SYS1_BASE + 0x2C010000)
133 #define GIC600_GICV_BASE          (SCP_SYS1_BASE + 0x2C020000)
134 
135 #define GIC600_GICD_BASE          (SCP_SYS1_BASE + 0x30000000)
136 #define GIC600_GICA_BASE          (SCP_SYS1_BASE + 0x30010000)
137 #define GIC600_GICP_BASE          (SCP_SYS1_BASE + 0x30030000)
138 #define GIC600_GITS_BASE          (SCP_SYS1_BASE + 0x30040000)
139 
140 /*
141  * System access port 0
142  */
143 #define SCP_CMN600_BASE           (SCP_SYS0_BASE + 0x10000000)
144 #define CMN600_ROOT_NODE_OFFSET   0xD00000
145 #define CMN600_ROOTNODE_BASE      (SCP_CMN600_BASE + CMN600_ROOT_NODE_OFFSET)
146 
147 #define SCP_AP_SHARED_SECURE_RAM     (SCP_SYS0_BASE + 0x05400000)
148 #define SCP_AP_SHARED_NONSECURE_RAM  (SCP_SYS0_BASE + 0x05200000)
149 #define SCP_MCP_SHARED_SECURE_RAM    (SCP_PERIPHERAL_BASE + 0x01620000)
150 #define SCP_MCP_SHARED_NONSECURE_RAM (SCP_PERIPHERAL_BASE + 0x01610000)
151 
152 /*
153  * System access port 1
154  */
155 #define SCP_TRUSTED_RAM_BASE          (SCP_SYS1_BASE + 0x04000000)
156 #define SCP_NONTRUSTED_RAM_BASE       (SCP_SYS1_BASE + 0x06000000)
157 #define SCP_SSC_BASE                  (SCP_SYS1_BASE + 0x2A420000)
158 #define SCP_REFCLK_CNTCONTROL_BASE    (SCP_SYS1_BASE + 0x2A430000)
159 
160 /*
161  * Base addresses of MHU devices
162  */
163 #define MHU_SCP_TO_AP_NS(cluster) ((SCP_MHU_AP_BASE + \
164                                    (0x00010000 * cluster) + 0x00000020))
165 #define MHU_AP_TO_SCP_NS(cluster) ((SCP_MHU_AP_BASE + \
166                                    (0x00010000 * cluster) + 0x00000120))
167 #define MHU_SCP_TO_AP_S(cluster)  ((SCP_MHU_AP_BASE + \
168                                    (0x00010000 * cluster) + 0x00000200))
169 #define MHU_AP_TO_SCP_S(cluster)  ((SCP_MHU_AP_BASE + \
170                                    (0x00010000 * cluster) + 0x00000300))
171 
172 #define MHU_SCP_TO_MCP_NS         (SCP_MHU_MCP_BASE + 0x00000020)
173 #define MHU_MCP_TO_SCP_NS         (SCP_MHU_MCP_BASE + 0x00000120)
174 #define MHU_SCP_TO_MCP_S          (SCP_MHU_MCP_BASE + 0x00000200)
175 #define MHU_MCP_TO_SCP_S          (SCP_MHU_MCP_BASE + 0x00000300)
176 
177 /*
178  * N1SDP PLL address space
179  */
180 #define SCP_PLL_CPU0_CTRL            (SCP_SCC_BASE + 0x00000100)
181 #define SCP_PLL_CPU0_STAT            (SCP_SCC_BASE + 0x00000104)
182 #define SCP_PLL_CPU1_CTRL            (SCP_SCC_BASE + 0x00000108)
183 #define SCP_PLL_CPU1_STAT            (SCP_SCC_BASE + 0x0000010C)
184 #define SCP_PLL_CLUS_CTRL            (SCP_SCC_BASE + 0x00000110)
185 #define SCP_PLL_CLUS_STAT            (SCP_SCC_BASE + 0x00000114)
186 #define SCP_PLL_SYSPLL_CTRL          (SCP_SCC_BASE + 0x00000118)
187 #define SCP_PLL_SYSPLL_STAT          (SCP_SCC_BASE + 0x0000011C)
188 #define SCP_PLL_DMC_CTRL             (SCP_SCC_BASE + 0x00000120)
189 #define SCP_PLL_DMC_STAT             (SCP_SCC_BASE + 0x00000124)
190 #define SCP_PLL_INTERCONNECT_CTRL    (SCP_SCC_BASE + 0x00000128)
191 #define SCP_PLL_INTERCONNECT_STAT    (SCP_SCC_BASE + 0x0000012C)
192 
193 /*
194  * DDR PHY base address
195  */
196 #define SCP_DDR_PHY0                 (0x50604000)
197 #define SCP_DDR_PHY1                 (0x50614000)
198 
199 /*
200  * DMC-620 controller base address
201  */
202 #define SCP_DMC0                     (SCP_MEMORY_CONTROLLER + 0x00000000)
203 #define SCP_DMC1                     (SCP_MEMORY_CONTROLLER + 0x00100000)
204 
205 /*
206  * SoC temperature register address
207  */
208 #define SCP_PLAT_BASE                (SCP_SYS0_BASE + 0x3FFE0000)
209 #define SCP_SENSOR_SOC_TEMP          (SCP_PLAT_BASE + 0x00000080)
210 
211 #endif /* N1SDP_SCP_MMAP_H */
212