1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Macronix(MX25L25635F) definitions. 9 * https://www.macronix.com/Lists/Datasheet/Attachments/7414/MX25L25635F,%203V,%20256Mb,%20v1.5.pdf 10 */ 11 12 #ifndef DEVICE_NOR_MX25_H 13 #define DEVICE_NOR_MX25_H 14 15 #include "qspi_api.h" 16 17 #define PROGRAM_PAGE_SIZE (0x1U << 8) /* 256 byte */ 18 #define ERASE_BLOCK_SIZE (0x1U << 16) /* 64KiB */ 19 20 /* 21 * Supports only 1bit I/O for instruction phase. 22 * Therefore, it should not be implemented a command 23 * which has 2bit or 4bit I/O for instruction phase. 24 */ 25 26 /* common command is referred by config_nor.c */ 27 #define COMMAND_RESET_ENABLE QSPI_COMMAND_TYPE_CODE(0x66) 28 #define COMMAND_RESET_MEMORY QSPI_COMMAND_TYPE_CODE(0x99) 29 #define COMMAND_READ_ID QSPI_COMMAND_TYPE_CODE_DATA(0x9F) 30 #define COMMAND_READ_SFDP QSPI_COMMAND_TYPE_READ(0x5A, 3, 8, 1, 1, 1) 31 #define COMMAND_WRITE_ENABLE QSPI_COMMAND_TYPE_CODE(0x06) 32 #define COMMAND_WRITE_DISABLE QSPI_COMMAND_TYPE_CODE(0x04) 33 #define COMMAND_READ_STATUS_REG QSPI_COMMAND_TYPE_CODE_DATA(0x05) 34 #define COMMAND_WRITE_STATUS_REG QSPI_COMMAND_TYPE_CODE_DATA(0x01) 35 #define COMMAND_READ QSPI_COMMAND_TYPE_READ(0x03, 3, 0, 1, 1, 1) 36 #define COMMAND_FAST_READ QSPI_COMMAND_TYPE_READ(0x0B, 3, 8, 1, 1, 1) 37 #define COMMAND_FAST_READ_1_1_2 QSPI_COMMAND_TYPE_READ(0x3B, 3, 8, 1, 1, 2) 38 #define COMMAND_FAST_READ_1_2_2 QSPI_COMMAND_TYPE_READ(0xBB, 3, 4, 1, 2, 2) 39 #define COMMAND_FAST_READ_1_1_4 QSPI_COMMAND_TYPE_READ(0x6B, 3, 8, 1, 1, 4) 40 #define COMMAND_FAST_READ_1_4_4 QSPI_COMMAND_TYPE_READ(0xEB, 3, 6, 1, 4, 4) 41 #define COMMAND_READ_4B QSPI_COMMAND_TYPE_READ(0x13, 4, 0, 1, 1, 1) 42 #define COMMAND_FAST_READ_4B QSPI_COMMAND_TYPE_READ(0x0C, 4, 8, 1, 1, 1) 43 #define COMMAND_FAST_READ_1_1_2_4B QSPI_COMMAND_TYPE_READ(0x3C, 4, 8, 1, 1, 2) 44 #define COMMAND_FAST_READ_1_2_2_4B QSPI_COMMAND_TYPE_READ(0xBC, 4, 4, 1, 2, 2) 45 #define COMMAND_FAST_READ_1_1_4_4B QSPI_COMMAND_TYPE_READ(0x6C, 4, 8, 1, 1, 4) 46 #define COMMAND_FAST_READ_1_4_4_4B QSPI_COMMAND_TYPE_READ(0xEC, 4, 6, 1, 4, 4) 47 #define COMMAND_PROGRAM QSPI_COMMAND_TYPE_WRITE(0x02, 3, 1, 1, 1) 48 #define COMMAND_PROGRAM_1_1_2 QSPI_COMMAND_EMPTY 49 #define COMMAND_PROGRAM_1_2_2 QSPI_COMMAND_EMPTY 50 #define COMMAND_PROGRAM_1_1_4 QSPI_COMMAND_EMPTY 51 #define COMMAND_PROGRAM_1_4_4 QSPI_COMMAND_TYPE_WRITE(0x38, 3, 1, 4, 4) 52 #define COMMAND_PROGRAM_4B QSPI_COMMAND_TYPE_WRITE(0x12, 4, 1, 1, 1) 53 #define COMMAND_PROGRAM_1_1_4_4B QSPI_COMMAND_EMPTY 54 #define COMMAND_PROGRAM_1_4_4_4B QSPI_COMMAND_TYPE_WRITE(0x3E, 4, 1, 4, 4) 55 #define COMMAND_ERASE_4KB QSPI_COMMAND_TYPE_WRITE_ADDR(0x20, 3, 1, 1, 1) 56 #define COMMAND_ERASE_32KB QSPI_COMMAND_TYPE_WRITE_ADDR(0x52, 3, 1, 1, 1) 57 #define COMMAND_ERASE_BLOCK QSPI_COMMAND_TYPE_WRITE_ADDR(0xD8, 3, 1, 1, 1) 58 #define COMMAND_ERASE_CHIP QSPI_COMMAND_TYPE_CODE(0x60) 59 #define COMMAND_ERASE_4KB_4B QSPI_COMMAND_TYPE_WRITE_ADDR(0x21, 4, 1, 1, 1) 60 #define COMMAND_ERASE_32KB_4B QSPI_COMMAND_TYPE_WRITE_ADDR(0x5C, 4, 1, 1, 1) 61 #define COMMAND_ERASE_BLOCK_4B QSPI_COMMAND_TYPE_WRITE_ADDR(0xDC, 4, 1, 1, 1) 62 63 /* Macronix MX25 specific command */ 64 #define MX25_COMMAND_ENTER_4BYTE QSPI_COMMAND_TYPE_CODE(0xB7) 65 #define MX25_COMMAND_EXIT_4BYTE QSPI_COMMAND_TYPE_CODE(0xE9) 66 #define MX25_COMMAND_READ_SECURITY_REG QSPI_COMMAND_TYPE_CODE_DATA(0x2B) 67 68 /* Status Register */ 69 #define MX25_QE_BIT (0x1 << 6) 70 #define MX25_QUAD_DISABLE(val) ((val) &= ~MX25_QE_BIT) 71 #define MX25_QUAD_ENABLE(val) ((val) |= MX25_QE_BIT) 72 #define MX25_IS_QUAD_ENABLE(val) (((val)&MX25_QE_BIT) != 0) 73 74 #define MX25_WEL_ENABLE (0x1 << 1) 75 #define MX25_IS_WEL_ENABLE(status) (((status)&MX25_WEL_ENABLE) != 0) 76 77 /* Security Register */ 78 #define MX25_E_FAIL (0x1 << 6) 79 #define MX25_IS_ERASE_FAIL(sec) (((sec)&MX25_E_FAIL) != 0) 80 81 #define MX25_P_FAIL (0x1 << 5) 82 #define MX25_IS_PROGRAM_FAIL(sec) (((sec)&MX25_P_FAIL) != 0) 83 84 int mx25_nor_set_io_protocol( 85 fwk_id_t id, 86 const struct qspi_api *qspi_api, 87 void *arg); 88 int mx25_nor_set_4byte_addr_mode( 89 fwk_id_t id, 90 const struct qspi_api *qspi_api, 91 void *arg); 92 int mx25_nor_get_program_result( 93 fwk_id_t id, 94 const struct qspi_api *qspi_api, 95 void *arg); 96 int mx25_nor_get_erase_result( 97 fwk_id_t id, 98 const struct qspi_api *qspi_api, 99 void *arg); 100 101 /* alias for configuration data */ 102 #define nor_set_io_protocol mx25_nor_set_io_protocol 103 #define nor_set_4byte_addr_mode mx25_nor_set_4byte_addr_mode 104 #define nor_get_program_result mx25_nor_get_program_result 105 #define nor_get_erase_result mx25_nor_get_erase_result 106 107 #endif /* DEVICE_NOR_MX25_H */ 108