1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Winbond (W25Q256JV) definitions. 9 * https://cdn.sparkfun.com/assets/c/2/9/2/6/W25Q256JV.pdf 10 */ 11 12 #ifndef DEVICE_NOR_W25_H 13 #define DEVICE_NOR_W25_H 14 15 #include "qspi_api.h" 16 17 #define PROGRAM_PAGE_SIZE (0x1U << 8) /* 256 byte */ 18 #define ERASE_BLOCK_SIZE (0x1U << 16) /* 64KiB */ 19 20 /* 21 * Supports only 1bit I/O for instruction phase. 22 * Therefore, it should not be implemented a command 23 * which has 2bit or 4bit I/O for instruction phase. 24 */ 25 26 /* common command is referred by config_nor.c */ 27 #define COMMAND_RESET_ENABLE QSPI_COMMAND_TYPE_CODE(0x66) 28 #define COMMAND_RESET_MEMORY QSPI_COMMAND_TYPE_CODE(0x99) 29 #define COMMAND_READ_ID QSPI_COMMAND_TYPE_CODE_DATA(0x9F) 30 #define COMMAND_READ_SFDP QSPI_COMMAND_TYPE_READ(0x5A, 3, 8, 1, 1, 1) 31 #define COMMAND_WRITE_ENABLE QSPI_COMMAND_TYPE_CODE(0x06) 32 #define COMMAND_WRITE_DISABLE QSPI_COMMAND_TYPE_CODE(0x04) 33 #define COMMAND_READ_STATUS_REG QSPI_COMMAND_TYPE_CODE_DATA(0x05) 34 #define COMMAND_WRITE_STATUS_REG QSPI_COMMAND_TYPE_CODE_DATA(0x01) 35 #define COMMAND_READ QSPI_COMMAND_TYPE_READ(0x03, 3, 0, 1, 1, 1) 36 #define COMMAND_FAST_READ QSPI_COMMAND_TYPE_READ(0x0B, 3, 8, 1, 1, 1) 37 #define COMMAND_FAST_READ_1_1_2 QSPI_COMMAND_TYPE_READ(0x3B, 3, 8, 1, 1, 2) 38 #define COMMAND_FAST_READ_1_2_2 \ 39 QSPI_COMMAND_TYPE_READ_WITH_ALT_FF( \ 40 0xBB, 3, 1, 0, 1, 2, 2) /* M7-M0 should be 0xFF */ 41 #define COMMAND_FAST_READ_1_1_4 QSPI_COMMAND_TYPE_READ(0x6B, 3, 8, 1, 1, 4) 42 #define COMMAND_FAST_READ_1_4_4 \ 43 QSPI_COMMAND_TYPE_READ_WITH_ALT_FF( \ 44 0xEB, 3, 1, 4, 1, 4, 4) /* M7-M0 should be 0xFF */ 45 #define COMMAND_READ_4B QSPI_COMMAND_TYPE_READ(0x13, 4, 0, 1, 1, 1) 46 #define COMMAND_FAST_READ_4B QSPI_COMMAND_TYPE_READ(0x0C, 4, 8, 1, 1, 1) 47 #define COMMAND_FAST_READ_1_1_2_4B QSPI_COMMAND_TYPE_READ(0x3C, 4, 8, 1, 1, 2) 48 #define COMMAND_FAST_READ_1_2_2_4B \ 49 QSPI_COMMAND_TYPE_READ_WITH_ALT_FF( \ 50 0xBC, 4, 1, 0, 1, 2, 2) /* M7-M0 should be 0xFF */ 51 #define COMMAND_FAST_READ_1_1_4_4B QSPI_COMMAND_TYPE_READ(0x6C, 4, 8, 1, 1, 4) 52 #define COMMAND_FAST_READ_1_4_4_4B \ 53 QSPI_COMMAND_TYPE_READ_WITH_ALT_FF( \ 54 0xEC, 4, 1, 4, 1, 4, 4) /* M7-M0 should be 0xFF */ 55 #define COMMAND_PROGRAM QSPI_COMMAND_TYPE_WRITE(0x02, 3, 1, 1, 1) 56 #define COMMAND_PROGRAM_1_1_2 QSPI_COMMAND_EMPTY 57 #define COMMAND_PROGRAM_1_2_2 QSPI_COMMAND_EMPTY 58 #define COMMAND_PROGRAM_1_1_4 QSPI_COMMAND_TYPE_WRITE(0x32, 3, 1, 1, 4) 59 #define COMMAND_PROGRAM_1_4_4 QSPI_COMMAND_EMPTY 60 #define COMMAND_PROGRAM_4B QSPI_COMMAND_TYPE_WRITE(0x12, 4, 1, 1, 1) 61 #define COMMAND_PROGRAM_1_1_4_4B QSPI_COMMAND_TYPE_WRITE(0x34, 4, 1, 1, 4) 62 #define COMMAND_PROGRAM_1_4_4_4B QSPI_COMMAND_EMPTY 63 #define COMMAND_ERASE_4KB QSPI_COMMAND_TYPE_WRITE_ADDR(0x20, 3, 1, 1, 1) 64 #define COMMAND_ERASE_32KB QSPI_COMMAND_TYPE_WRITE_ADDR(0x52, 3, 1, 1, 1) 65 #define COMMAND_ERASE_BLOCK QSPI_COMMAND_TYPE_WRITE_ADDR(0xD8, 3, 1, 1, 1) 66 #define COMMAND_ERASE_CHIP QSPI_COMMAND_TYPE_CODE(0x60) 67 #define COMMAND_ERASE_4KB_4B QSPI_COMMAND_TYPE_WRITE_ADDR(0x21, 4, 1, 1, 1) 68 #define COMMAND_ERASE_32KB_4B QSPI_COMMAND_EMPTY 69 #define COMMAND_ERASE_BLOCK_4B QSPI_COMMAND_TYPE_WRITE_ADDR(0xDC, 4, 1, 1, 1) 70 71 /* Winbond specific command */ 72 #define W25_COMMAND_ENTER_4BYTE QSPI_COMMAND_TYPE_CODE(0xB7) 73 #define W25_COMMAND_EXIT_4BYTE QSPI_COMMAND_TYPE_CODE(0xE9) 74 #define W25_COMMAND_READ_STATUS_REG_2 QSPI_COMMAND_TYPE_CODE_DATA(0x35) 75 #define W25_COMMAND_READ_STATUS_REG_3 QSPI_COMMAND_TYPE_CODE_DATA(0x15) 76 #define W25_COMMAND_WRITE_STATUS_REG_2 QSPI_COMMAND_TYPE_CODE_DATA(0x31) 77 #define W25_COMMAND_WRITE_STATUS_REG_3 QSPI_COMMAND_TYPE_CODE_DATA(0x11) 78 79 /* Status Register */ 80 #define W25_WEL_ENABLE (0x1 << 1) 81 #define W25_IS_WEL_ENABLE(status) (((status)&W25_WEL_ENABLE) != 0) 82 83 /* Status Register 2 */ 84 #define W25_QE_BIT (0x1 << 2) 85 #define W25_QUAD_DISABLE(val) ((val) &= ~W25_QE_BIT) 86 #define W25_QUAD_ENABLE(val) ((val) |= W25_QE_BIT) 87 #define W25_IS_QUAD_ENABLE(val) (((val)&W25_QE_BIT) != 0) 88 89 int w25_nor_set_io_protocol( 90 fwk_id_t id, 91 const struct qspi_api *qspi_api, 92 void *arg); 93 int w25_nor_set_4byte_addr_mode( 94 fwk_id_t id, 95 const struct qspi_api *qspi_api, 96 void *arg); 97 98 // alias for configuration data 99 #define nor_set_io_protocol w25_nor_set_io_protocol 100 #define nor_set_4byte_addr_mode w25_nor_set_4byte_addr_mode 101 #define nor_get_program_result NULL 102 #define nor_get_erase_result NULL 103 104 #endif /* DEVICE_NOR_W25_H */ 105