1 /* 2 3 Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef NRF51_TO_NRF52_H 34 #define NRF51_TO_NRF52_H 35 36 /*lint ++flb "Enter library region */ 37 38 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. 39 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 40 * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 41 * from the nrf51_deprecated.h file. */ 42 43 44 /* IRQ */ 45 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 46 #ifndef UART0_IRQHandler 47 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 48 #endif 49 #ifndef SPI0_TWI0_IRQHandler 50 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 51 #endif 52 #ifndef SPI1_TWI1_IRQHandler 53 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 54 #endif 55 #ifndef ADC_IRQHandler 56 #define ADC_IRQHandler SAADC_IRQHandler 57 #endif 58 #ifndef LPCOMP_IRQHandler 59 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 60 #endif 61 #ifndef SWI0_IRQHandler 62 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 63 #endif 64 #ifndef SWI1_IRQHandler 65 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 66 #endif 67 #ifndef SWI2_IRQHandler 68 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 69 #endif 70 #ifndef SWI3_IRQHandler 71 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 72 #endif 73 #ifndef SWI4_IRQHandler 74 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 75 #endif 76 #ifndef SWI5_IRQHandler 77 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 78 #endif 79 80 #ifndef UART0_IRQn 81 #define UART0_IRQn UARTE0_UART0_IRQn 82 #endif 83 #ifndef SPI0_TWI0_IRQn 84 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 85 #endif 86 #ifndef SPI1_TWI1_IRQn 87 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 88 #endif 89 #ifndef ADC_IRQn 90 #define ADC_IRQn SAADC_IRQn 91 #endif 92 #ifndef LPCOMP_IRQn 93 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 94 #endif 95 #ifndef SWI0_IRQn 96 #define SWI0_IRQn SWI0_EGU0_IRQn 97 #endif 98 #ifndef SWI1_IRQn 99 #define SWI1_IRQn SWI1_EGU1_IRQn 100 #endif 101 #ifndef SWI2_IRQn 102 #define SWI2_IRQn SWI2_EGU2_IRQn 103 #endif 104 #ifndef SWI3_IRQn 105 #define SWI3_IRQn SWI3_EGU3_IRQn 106 #endif 107 #ifndef SWI4_IRQn 108 #define SWI4_IRQn SWI4_EGU4_IRQn 109 #endif 110 #ifndef SWI5_IRQn 111 #define SWI5_IRQn SWI5_EGU5_IRQn 112 #endif 113 114 115 /* UICR */ 116 /* Register RBPCONF was renamed to APPROTECT. */ 117 #ifndef RBPCONF 118 #define RBPCONF APPROTECT 119 #endif 120 121 #ifndef UICR_RBPCONF_PALL_Pos 122 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 123 #endif 124 #ifndef UICR_RBPCONF_PALL_Msk 125 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 126 #endif 127 #ifndef UICR_RBPCONF_PALL_Enabled 128 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 129 #endif 130 #ifndef UICR_RBPCONF_PALL_Disabled 131 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 132 #endif 133 134 /* GPIO */ 135 /* GPIO port was renamed to P0. */ 136 #ifndef NRF_GPIO 137 #define NRF_GPIO NRF_P0 138 #endif 139 #ifndef NRF_GPIO_BASE 140 #define NRF_GPIO_BASE NRF_P0_BASE 141 #endif 142 143 /* QDEC */ 144 /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 145 #ifndef PSELLED 146 #define PSELLED PSEL.LED 147 #endif 148 #ifndef PSELA 149 #define PSELA PSEL.A 150 #endif 151 #ifndef PSELB 152 #define PSELB PSEL.B 153 #endif 154 155 156 /* SPIS */ 157 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 158 #ifndef PSELSCK 159 #define PSELSCK PSEL.SCK 160 #endif 161 #ifndef PSELMISO 162 #define PSELMISO PSEL.MISO 163 #endif 164 #ifndef PSELMOSI 165 #define PSELMOSI PSEL.MOSI 166 #endif 167 #ifndef PSELCSN 168 #define PSELCSN PSEL.CSN 169 #endif 170 171 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 172 #ifndef RXDPTR 173 #define RXDPTR RXD.PTR 174 #endif 175 #ifndef MAXRX 176 #define MAXRX RXD.MAXCNT 177 #endif 178 #ifndef AMOUNTRX 179 #define AMOUNTRX RXD.AMOUNT 180 #endif 181 182 #ifndef SPIS_MAXRX_MAXRX_Pos 183 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 184 #endif 185 #ifndef SPIS_MAXRX_MAXRX_Msk 186 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 187 #endif 188 189 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos 190 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 191 #endif 192 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk 193 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 194 #endif 195 196 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 197 #ifndef TXDPTR 198 #define TXDPTR TXD.PTR 199 #endif 200 #ifndef MAXTX 201 #define MAXTX TXD.MAXCNT 202 #endif 203 #ifndef AMOUNTTX 204 #define AMOUNTTX TXD.AMOUNT 205 #endif 206 207 #ifndef SPIS_MAXTX_MAXTX_Pos 208 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 209 #endif 210 #ifndef SPIS_MAXTX_MAXTX_Msk 211 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 212 #endif 213 214 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos 215 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 216 #endif 217 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk 218 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 219 #endif 220 221 /* MPU */ 222 /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ 223 #ifndef NRF_MPU 224 #define NRF_MPU NRF_BPROT 225 #endif 226 227 /* Register DISABLEINDEBUG macros were affected. */ 228 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos 229 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos 230 #endif 231 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk 232 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk 233 #endif 234 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 235 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 236 #endif 237 #ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 238 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 239 #endif 240 241 /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ 242 #ifndef PROTENSET0 243 #define PROTENSET0 CONFIG0 244 #endif 245 #ifndef PROTENSET1 246 #define PROTENSET1 CONFIG1 247 #endif 248 249 #ifndef MPU_PROTENSET1_PROTREG63_Pos 250 #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos 251 #endif 252 #ifndef MPU_PROTENSET1_PROTREG63_Msk 253 #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk 254 #endif 255 #ifndef MPU_PROTENSET1_PROTREG63_Disabled 256 #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled 257 #endif 258 #ifndef MPU_PROTENSET1_PROTREG63_Enabled 259 #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled 260 #endif 261 #ifndef MPU_PROTENSET1_PROTREG63_Set 262 #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled 263 #endif 264 265 #ifndef MPU_PROTENSET1_PROTREG62_Pos 266 #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos 267 #endif 268 #ifndef MPU_PROTENSET1_PROTREG62_Msk 269 #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk 270 #endif 271 #ifndef MPU_PROTENSET1_PROTREG62_Disabled 272 #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled 273 #endif 274 #ifndef MPU_PROTENSET1_PROTREG62_Enabled 275 #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled 276 #endif 277 #ifndef MPU_PROTENSET1_PROTREG62_Set 278 #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled 279 #endif 280 281 #ifndef MPU_PROTENSET1_PROTREG61_Pos 282 #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos 283 #endif 284 #ifndef MPU_PROTENSET1_PROTREG61_Msk 285 #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk 286 #endif 287 #ifndef MPU_PROTENSET1_PROTREG61_Disabled 288 #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled 289 #endif 290 #ifndef MPU_PROTENSET1_PROTREG61_Enabled 291 #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled 292 #endif 293 #ifndef MPU_PROTENSET1_PROTREG61_Set 294 #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled 295 #endif 296 297 #ifndef MPU_PROTENSET1_PROTREG60_Pos 298 #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos 299 #endif 300 #ifndef MPU_PROTENSET1_PROTREG60_Msk 301 #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk 302 #endif 303 #ifndef MPU_PROTENSET1_PROTREG60_Disabled 304 #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled 305 #endif 306 #ifndef MPU_PROTENSET1_PROTREG60_Enabled 307 #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled 308 #endif 309 #ifndef MPU_PROTENSET1_PROTREG60_Set 310 #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled 311 #endif 312 313 #ifndef MPU_PROTENSET1_PROTREG59_Pos 314 #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos 315 #endif 316 #ifndef MPU_PROTENSET1_PROTREG59_Msk 317 #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk 318 #endif 319 #ifndef MPU_PROTENSET1_PROTREG59_Disabled 320 #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled 321 #endif 322 #ifndef MPU_PROTENSET1_PROTREG59_Enabled 323 #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled 324 #endif 325 #ifndef MPU_PROTENSET1_PROTREG59_Set 326 #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled 327 #endif 328 329 #ifndef MPU_PROTENSET1_PROTREG58_Pos 330 #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos 331 #endif 332 #ifndef MPU_PROTENSET1_PROTREG58_Msk 333 #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk 334 #endif 335 #ifndef MPU_PROTENSET1_PROTREG58_Disabled 336 #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled 337 #endif 338 #ifndef MPU_PROTENSET1_PROTREG58_Enabled 339 #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled 340 #endif 341 #ifndef MPU_PROTENSET1_PROTREG58_Set 342 #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled 343 #endif 344 345 #ifndef MPU_PROTENSET1_PROTREG57_Pos 346 #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos 347 #endif 348 #ifndef MPU_PROTENSET1_PROTREG57_Msk 349 #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk 350 #endif 351 #ifndef MPU_PROTENSET1_PROTREG57_Disabled 352 #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled 353 #endif 354 #ifndef MPU_PROTENSET1_PROTREG57_Enabled 355 #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled 356 #endif 357 #ifndef MPU_PROTENSET1_PROTREG57_Set 358 #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled 359 #endif 360 361 #ifndef MPU_PROTENSET1_PROTREG56_Pos 362 #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos 363 #endif 364 #ifndef MPU_PROTENSET1_PROTREG56_Msk 365 #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk 366 #endif 367 #ifndef MPU_PROTENSET1_PROTREG56_Disabled 368 #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled 369 #endif 370 #ifndef MPU_PROTENSET1_PROTREG56_Enabled 371 #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled 372 #endif 373 #ifndef MPU_PROTENSET1_PROTREG56_Set 374 #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled 375 #endif 376 377 #ifndef MPU_PROTENSET1_PROTREG55_Pos 378 #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos 379 #endif 380 #ifndef MPU_PROTENSET1_PROTREG55_Msk 381 #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk 382 #endif 383 #ifndef MPU_PROTENSET1_PROTREG55_Disabled 384 #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled 385 #endif 386 #ifndef MPU_PROTENSET1_PROTREG55_Enabled 387 #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled 388 #endif 389 #ifndef MPU_PROTENSET1_PROTREG55_Set 390 #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled 391 #endif 392 393 #ifndef MPU_PROTENSET1_PROTREG54_Pos 394 #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos 395 #endif 396 #ifndef MPU_PROTENSET1_PROTREG54_Msk 397 #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk 398 #endif 399 #ifndef MPU_PROTENSET1_PROTREG54_Disabled 400 #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled 401 #endif 402 #ifndef MPU_PROTENSET1_PROTREG54_Enabled 403 #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled 404 #endif 405 #ifndef MPU_PROTENSET1_PROTREG54_Set 406 #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled 407 #endif 408 409 #ifndef MPU_PROTENSET1_PROTREG53_Pos 410 #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos 411 #endif 412 #ifndef MPU_PROTENSET1_PROTREG53_Msk 413 #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk 414 #endif 415 #ifndef MPU_PROTENSET1_PROTREG53_Disabled 416 #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled 417 #endif 418 #ifndef MPU_PROTENSET1_PROTREG53_Enabled 419 #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled 420 #endif 421 #ifndef MPU_PROTENSET1_PROTREG53_Set 422 #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled 423 #endif 424 425 #ifndef MPU_PROTENSET1_PROTREG52_Pos 426 #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos 427 #endif 428 #ifndef MPU_PROTENSET1_PROTREG52_Msk 429 #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk 430 #endif 431 #ifndef MPU_PROTENSET1_PROTREG52_Disabled 432 #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled 433 #endif 434 #ifndef MPU_PROTENSET1_PROTREG52_Enabled 435 #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled 436 #endif 437 #ifndef MPU_PROTENSET1_PROTREG52_Set 438 #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled 439 #endif 440 441 #ifndef MPU_PROTENSET1_PROTREG51_Pos 442 #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos 443 #endif 444 #ifndef MPU_PROTENSET1_PROTREG51_Msk 445 #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk 446 #endif 447 #ifndef MPU_PROTENSET1_PROTREG51_Disabled 448 #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled 449 #endif 450 #ifndef MPU_PROTENSET1_PROTREG51_Enabled 451 #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled 452 #endif 453 #ifndef MPU_PROTENSET1_PROTREG51_Set 454 #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled 455 #endif 456 457 #ifndef MPU_PROTENSET1_PROTREG50_Pos 458 #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos 459 #endif 460 #ifndef MPU_PROTENSET1_PROTREG50_Msk 461 #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk 462 #endif 463 #ifndef MPU_PROTENSET1_PROTREG50_Disabled 464 #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled 465 #endif 466 #ifndef MPU_PROTENSET1_PROTREG50_Enabled 467 #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled 468 #endif 469 #ifndef MPU_PROTENSET1_PROTREG50_Set 470 #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled 471 #endif 472 473 #ifndef MPU_PROTENSET1_PROTREG49_Pos 474 #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos 475 #endif 476 #ifndef MPU_PROTENSET1_PROTREG49_Msk 477 #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk 478 #endif 479 #ifndef MPU_PROTENSET1_PROTREG49_Disabled 480 #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled 481 #endif 482 #ifndef MPU_PROTENSET1_PROTREG49_Enabled 483 #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled 484 #endif 485 #ifndef MPU_PROTENSET1_PROTREG49_Set 486 #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled 487 #endif 488 489 #ifndef MPU_PROTENSET1_PROTREG48_Pos 490 #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos 491 #endif 492 #ifndef MPU_PROTENSET1_PROTREG48_Msk 493 #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk 494 #endif 495 #ifndef MPU_PROTENSET1_PROTREG48_Disabled 496 #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled 497 #endif 498 #ifndef MPU_PROTENSET1_PROTREG48_Enabled 499 #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled 500 #endif 501 #ifndef MPU_PROTENSET1_PROTREG48_Set 502 #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled 503 #endif 504 505 #ifndef MPU_PROTENSET1_PROTREG47_Pos 506 #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos 507 #endif 508 #ifndef MPU_PROTENSET1_PROTREG47_Msk 509 #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk 510 #endif 511 #ifndef MPU_PROTENSET1_PROTREG47_Disabled 512 #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled 513 #endif 514 #ifndef MPU_PROTENSET1_PROTREG47_Enabled 515 #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled 516 #endif 517 #ifndef MPU_PROTENSET1_PROTREG47_Set 518 #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled 519 #endif 520 521 #ifndef MPU_PROTENSET1_PROTREG46_Pos 522 #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos 523 #endif 524 #ifndef MPU_PROTENSET1_PROTREG46_Msk 525 #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk 526 #endif 527 #ifndef MPU_PROTENSET1_PROTREG46_Disabled 528 #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled 529 #endif 530 #ifndef MPU_PROTENSET1_PROTREG46_Enabled 531 #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled 532 #endif 533 #ifndef MPU_PROTENSET1_PROTREG46_Set 534 #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled 535 #endif 536 537 #ifndef MPU_PROTENSET1_PROTREG45_Pos 538 #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos 539 #endif 540 #ifndef MPU_PROTENSET1_PROTREG45_Msk 541 #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk 542 #endif 543 #ifndef MPU_PROTENSET1_PROTREG45_Disabled 544 #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled 545 #endif 546 #ifndef MPU_PROTENSET1_PROTREG45_Enabled 547 #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled 548 #endif 549 #ifndef MPU_PROTENSET1_PROTREG45_Set 550 #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled 551 #endif 552 553 #ifndef MPU_PROTENSET1_PROTREG44_Pos 554 #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos 555 #endif 556 #ifndef MPU_PROTENSET1_PROTREG44_Msk 557 #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk 558 #endif 559 #ifndef MPU_PROTENSET1_PROTREG44_Disabled 560 #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled 561 #endif 562 #ifndef MPU_PROTENSET1_PROTREG44_Enabled 563 #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled 564 #endif 565 #ifndef MPU_PROTENSET1_PROTREG44_Set 566 #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled 567 #endif 568 569 #ifndef MPU_PROTENSET1_PROTREG43_Pos 570 #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos 571 #endif 572 #ifndef MPU_PROTENSET1_PROTREG43_Msk 573 #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk 574 #endif 575 #ifndef MPU_PROTENSET1_PROTREG43_Disabled 576 #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled 577 #endif 578 #ifndef MPU_PROTENSET1_PROTREG43_Enabled 579 #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled 580 #endif 581 #ifndef MPU_PROTENSET1_PROTREG43_Set 582 #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled 583 #endif 584 585 #ifndef MPU_PROTENSET1_PROTREG42_Pos 586 #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos 587 #endif 588 #ifndef MPU_PROTENSET1_PROTREG42_Msk 589 #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk 590 #endif 591 #ifndef MPU_PROTENSET1_PROTREG42_Disabled 592 #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled 593 #endif 594 #ifndef MPU_PROTENSET1_PROTREG42_Enabled 595 #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled 596 #endif 597 #ifndef MPU_PROTENSET1_PROTREG42_Set 598 #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled 599 #endif 600 601 #ifndef MPU_PROTENSET1_PROTREG41_Pos 602 #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos 603 #endif 604 #ifndef MPU_PROTENSET1_PROTREG41_Msk 605 #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk 606 #endif 607 #ifndef MPU_PROTENSET1_PROTREG41_Disabled 608 #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled 609 #endif 610 #ifndef MPU_PROTENSET1_PROTREG41_Enabled 611 #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled 612 #endif 613 #ifndef MPU_PROTENSET1_PROTREG41_Set 614 #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled 615 #endif 616 617 #ifndef MPU_PROTENSET1_PROTREG40_Pos 618 #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos 619 #endif 620 #ifndef MPU_PROTENSET1_PROTREG40_Msk 621 #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk 622 #endif 623 #ifndef MPU_PROTENSET1_PROTREG40_Disabled 624 #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled 625 #endif 626 #ifndef MPU_PROTENSET1_PROTREG40_Enabled 627 #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled 628 #endif 629 #ifndef MPU_PROTENSET1_PROTREG40_Set 630 #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled 631 #endif 632 633 #ifndef MPU_PROTENSET1_PROTREG39_Pos 634 #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos 635 #endif 636 #ifndef MPU_PROTENSET1_PROTREG39_Msk 637 #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk 638 #endif 639 #ifndef MPU_PROTENSET1_PROTREG39_Disabled 640 #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled 641 #endif 642 #ifndef MPU_PROTENSET1_PROTREG39_Enabled 643 #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled 644 #endif 645 #ifndef MPU_PROTENSET1_PROTREG39_Set 646 #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled 647 #endif 648 649 #ifndef MPU_PROTENSET1_PROTREG38_Pos 650 #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos 651 #endif 652 #ifndef MPU_PROTENSET1_PROTREG38_Msk 653 #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk 654 #endif 655 #ifndef MPU_PROTENSET1_PROTREG38_Disabled 656 #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled 657 #endif 658 #ifndef MPU_PROTENSET1_PROTREG38_Enabled 659 #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled 660 #endif 661 #ifndef MPU_PROTENSET1_PROTREG38_Set 662 #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled 663 #endif 664 665 #ifndef MPU_PROTENSET1_PROTREG37_Pos 666 #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos 667 #endif 668 #ifndef MPU_PROTENSET1_PROTREG37_Msk 669 #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk 670 #endif 671 #ifndef MPU_PROTENSET1_PROTREG37_Disabled 672 #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled 673 #endif 674 #ifndef MPU_PROTENSET1_PROTREG37_Enabled 675 #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled 676 #endif 677 #ifndef MPU_PROTENSET1_PROTREG37_Set 678 #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled 679 #endif 680 681 #ifndef MPU_PROTENSET1_PROTREG36_Pos 682 #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos 683 #endif 684 #ifndef MPU_PROTENSET1_PROTREG36_Msk 685 #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk 686 #endif 687 #ifndef MPU_PROTENSET1_PROTREG36_Disabled 688 #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled 689 #endif 690 #ifndef MPU_PROTENSET1_PROTREG36_Enabled 691 #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled 692 #endif 693 #ifndef MPU_PROTENSET1_PROTREG36_Set 694 #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled 695 #endif 696 697 #ifndef MPU_PROTENSET1_PROTREG35_Pos 698 #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos 699 #endif 700 #ifndef MPU_PROTENSET1_PROTREG35_Msk 701 #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk 702 #endif 703 #ifndef MPU_PROTENSET1_PROTREG35_Disabled 704 #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled 705 #endif 706 #ifndef MPU_PROTENSET1_PROTREG35_Enabled 707 #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled 708 #endif 709 #ifndef MPU_PROTENSET1_PROTREG35_Set 710 #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled 711 #endif 712 713 #ifndef MPU_PROTENSET1_PROTREG34_Pos 714 #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos 715 #endif 716 #ifndef MPU_PROTENSET1_PROTREG34_Msk 717 #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk 718 #endif 719 #ifndef MPU_PROTENSET1_PROTREG34_Disabled 720 #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled 721 #endif 722 #ifndef MPU_PROTENSET1_PROTREG34_Enabled 723 #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled 724 #endif 725 #ifndef MPU_PROTENSET1_PROTREG34_Set 726 #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled 727 #endif 728 729 #ifndef MPU_PROTENSET1_PROTREG33_Pos 730 #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos 731 #endif 732 #ifndef MPU_PROTENSET1_PROTREG33_Msk 733 #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk 734 #endif 735 #ifndef MPU_PROTENSET1_PROTREG33_Disabled 736 #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled 737 #endif 738 #ifndef MPU_PROTENSET1_PROTREG33_Enabled 739 #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled 740 #endif 741 #ifndef MPU_PROTENSET1_PROTREG33_Set 742 #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled 743 #endif 744 745 #ifndef MPU_PROTENSET1_PROTREG32_Pos 746 #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos 747 #endif 748 #ifndef MPU_PROTENSET1_PROTREG32_Msk 749 #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk 750 #endif 751 #ifndef MPU_PROTENSET1_PROTREG32_Disabled 752 #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled 753 #endif 754 #ifndef MPU_PROTENSET1_PROTREG32_Enabled 755 #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled 756 #endif 757 #ifndef MPU_PROTENSET1_PROTREG32_Set 758 #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled 759 #endif 760 761 #ifndef MPU_PROTENSET0_PROTREG31_Pos 762 #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos 763 #endif 764 #ifndef MPU_PROTENSET0_PROTREG31_Msk 765 #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk 766 #endif 767 #ifndef MPU_PROTENSET0_PROTREG31_Disabled 768 #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled 769 #endif 770 #ifndef MPU_PROTENSET0_PROTREG31_Enabled 771 #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled 772 #endif 773 #ifndef MPU_PROTENSET0_PROTREG31_Set 774 #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled 775 #endif 776 777 #ifndef MPU_PROTENSET0_PROTREG30_Pos 778 #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos 779 #endif 780 #ifndef MPU_PROTENSET0_PROTREG30_Msk 781 #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk 782 #endif 783 #ifndef MPU_PROTENSET0_PROTREG30_Disabled 784 #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled 785 #endif 786 #ifndef MPU_PROTENSET0_PROTREG30_Enabled 787 #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled 788 #endif 789 #ifndef MPU_PROTENSET0_PROTREG30_Set 790 #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled 791 #endif 792 793 #ifndef MPU_PROTENSET0_PROTREG29_Pos 794 #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos 795 #endif 796 #ifndef MPU_PROTENSET0_PROTREG29_Msk 797 #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk 798 #endif 799 #ifndef MPU_PROTENSET0_PROTREG29_Disabled 800 #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled 801 #endif 802 #ifndef MPU_PROTENSET0_PROTREG29_Enabled 803 #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled 804 #endif 805 #ifndef MPU_PROTENSET0_PROTREG29_Set 806 #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled 807 #endif 808 809 #ifndef MPU_PROTENSET0_PROTREG28_Pos 810 #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos 811 #endif 812 #ifndef MPU_PROTENSET0_PROTREG28_Msk 813 #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk 814 #endif 815 #ifndef MPU_PROTENSET0_PROTREG28_Disabled 816 #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled 817 #endif 818 #ifndef MPU_PROTENSET0_PROTREG28_Enabled 819 #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled 820 #endif 821 #ifndef MPU_PROTENSET0_PROTREG28_Set 822 #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled 823 #endif 824 825 #ifndef MPU_PROTENSET0_PROTREG27_Pos 826 #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos 827 #endif 828 #ifndef MPU_PROTENSET0_PROTREG27_Msk 829 #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk 830 #endif 831 #ifndef MPU_PROTENSET0_PROTREG27_Disabled 832 #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled 833 #endif 834 #ifndef MPU_PROTENSET0_PROTREG27_Enabled 835 #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled 836 #endif 837 #ifndef MPU_PROTENSET0_PROTREG27_Set 838 #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled 839 #endif 840 841 #ifndef MPU_PROTENSET0_PROTREG26_Pos 842 #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos 843 #endif 844 #ifndef MPU_PROTENSET0_PROTREG26_Msk 845 #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk 846 #endif 847 #ifndef MPU_PROTENSET0_PROTREG26_Disabled 848 #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled 849 #endif 850 #ifndef MPU_PROTENSET0_PROTREG26_Enabled 851 #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled 852 #endif 853 #ifndef MPU_PROTENSET0_PROTREG26_Set 854 #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled 855 #endif 856 857 #ifndef MPU_PROTENSET0_PROTREG25_Pos 858 #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos 859 #endif 860 #ifndef MPU_PROTENSET0_PROTREG25_Msk 861 #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk 862 #endif 863 #ifndef MPU_PROTENSET0_PROTREG25_Disabled 864 #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled 865 #endif 866 #ifndef MPU_PROTENSET0_PROTREG25_Enabled 867 #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled 868 #endif 869 #ifndef MPU_PROTENSET0_PROTREG25_Set 870 #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled 871 #endif 872 873 #ifndef MPU_PROTENSET0_PROTREG24_Pos 874 #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos 875 #endif 876 #ifndef MPU_PROTENSET0_PROTREG24_Msk 877 #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk 878 #endif 879 #ifndef MPU_PROTENSET0_PROTREG24_Disabled 880 #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled 881 #endif 882 #ifndef MPU_PROTENSET0_PROTREG24_Enabled 883 #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled 884 #endif 885 #ifndef MPU_PROTENSET0_PROTREG24_Set 886 #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled 887 #endif 888 889 #ifndef MPU_PROTENSET0_PROTREG23_Pos 890 #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos 891 #endif 892 #ifndef MPU_PROTENSET0_PROTREG23_Msk 893 #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk 894 #endif 895 #ifndef MPU_PROTENSET0_PROTREG23_Disabled 896 #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled 897 #endif 898 #ifndef MPU_PROTENSET0_PROTREG23_Enabled 899 #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled 900 #endif 901 #ifndef MPU_PROTENSET0_PROTREG23_Set 902 #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled 903 #endif 904 905 #ifndef MPU_PROTENSET0_PROTREG22_Pos 906 #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos 907 #endif 908 #ifndef MPU_PROTENSET0_PROTREG22_Msk 909 #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk 910 #endif 911 #ifndef MPU_PROTENSET0_PROTREG22_Disabled 912 #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled 913 #endif 914 #ifndef MPU_PROTENSET0_PROTREG22_Enabled 915 #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled 916 #endif 917 #ifndef MPU_PROTENSET0_PROTREG22_Set 918 #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled 919 #endif 920 921 #ifndef MPU_PROTENSET0_PROTREG21_Pos 922 #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos 923 #endif 924 #ifndef MPU_PROTENSET0_PROTREG21_Msk 925 #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk 926 #endif 927 #ifndef MPU_PROTENSET0_PROTREG21_Disabled 928 #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled 929 #endif 930 #ifndef MPU_PROTENSET0_PROTREG21_Enabled 931 #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled 932 #endif 933 #ifndef MPU_PROTENSET0_PROTREG21_Set 934 #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled 935 #endif 936 937 #ifndef MPU_PROTENSET0_PROTREG20_Pos 938 #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos 939 #endif 940 #ifndef MPU_PROTENSET0_PROTREG20_Msk 941 #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk 942 #endif 943 #ifndef MPU_PROTENSET0_PROTREG20_Disabled 944 #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled 945 #endif 946 #ifndef MPU_PROTENSET0_PROTREG20_Enabled 947 #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled 948 #endif 949 #ifndef MPU_PROTENSET0_PROTREG20_Set 950 #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled 951 #endif 952 953 #ifndef MPU_PROTENSET0_PROTREG19_Pos 954 #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos 955 #endif 956 #ifndef MPU_PROTENSET0_PROTREG19_Msk 957 #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk 958 #endif 959 #ifndef MPU_PROTENSET0_PROTREG19_Disabled 960 #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled 961 #endif 962 #ifndef MPU_PROTENSET0_PROTREG19_Enabled 963 #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled 964 #endif 965 #ifndef MPU_PROTENSET0_PROTREG19_Set 966 #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled 967 #endif 968 969 #ifndef MPU_PROTENSET0_PROTREG18_Pos 970 #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos 971 #endif 972 #ifndef MPU_PROTENSET0_PROTREG18_Msk 973 #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk 974 #endif 975 #ifndef MPU_PROTENSET0_PROTREG18_Disabled 976 #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled 977 #endif 978 #ifndef MPU_PROTENSET0_PROTREG18_Enabled 979 #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled 980 #endif 981 #ifndef MPU_PROTENSET0_PROTREG18_Set 982 #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled 983 #endif 984 985 #ifndef MPU_PROTENSET0_PROTREG17_Pos 986 #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos 987 #endif 988 #ifndef MPU_PROTENSET0_PROTREG17_Msk 989 #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk 990 #endif 991 #ifndef MPU_PROTENSET0_PROTREG17_Disabled 992 #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled 993 #endif 994 #ifndef MPU_PROTENSET0_PROTREG17_Enabled 995 #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled 996 #endif 997 #ifndef MPU_PROTENSET0_PROTREG17_Set 998 #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled 999 #endif 1000 1001 #ifndef MPU_PROTENSET0_PROTREG16_Pos 1002 #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos 1003 #endif 1004 #ifndef MPU_PROTENSET0_PROTREG16_Msk 1005 #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk 1006 #endif 1007 #ifndef MPU_PROTENSET0_PROTREG16_Disabled 1008 #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled 1009 #endif 1010 #ifndef MPU_PROTENSET0_PROTREG16_Enabled 1011 #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled 1012 #endif 1013 #ifndef MPU_PROTENSET0_PROTREG16_Set 1014 #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled 1015 #endif 1016 1017 #ifndef MPU_PROTENSET0_PROTREG16_Set 1018 #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos 1019 #endif 1020 #ifndef MPU_PROTENSET0_PROTREG15_Msk 1021 #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk 1022 #endif 1023 #ifndef MPU_PROTENSET0_PROTREG15_Disabled 1024 #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled 1025 #endif 1026 #ifndef MPU_PROTENSET0_PROTREG15_Enabled 1027 #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled 1028 #endif 1029 #ifndef MPU_PROTENSET0_PROTREG15_Set 1030 #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled 1031 #endif 1032 1033 #ifndef MPU_PROTENSET0_PROTREG14_Pos 1034 #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos 1035 #endif 1036 #ifndef MPU_PROTENSET0_PROTREG14_Msk 1037 #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk 1038 #endif 1039 #ifndef MPU_PROTENSET0_PROTREG14_Disabled 1040 #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled 1041 #endif 1042 #ifndef MPU_PROTENSET0_PROTREG14_Enabled 1043 #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled 1044 #endif 1045 #ifndef MPU_PROTENSET0_PROTREG14_Set 1046 #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled 1047 #endif 1048 1049 #ifndef MPU_PROTENSET0_PROTREG13_Pos 1050 #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos 1051 #endif 1052 #ifndef MPU_PROTENSET0_PROTREG13_Msk 1053 #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk 1054 #endif 1055 #ifndef MPU_PROTENSET0_PROTREG13_Disabled 1056 #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled 1057 #endif 1058 #ifndef MPU_PROTENSET0_PROTREG13_Enabled 1059 #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled 1060 #endif 1061 #ifndef MPU_PROTENSET0_PROTREG13_Set 1062 #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled 1063 #endif 1064 1065 #ifndef MPU_PROTENSET0_PROTREG12_Pos 1066 #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos 1067 #endif 1068 #ifndef MPU_PROTENSET0_PROTREG12_Msk 1069 #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk 1070 #endif 1071 #ifndef MPU_PROTENSET0_PROTREG12_Disabled 1072 #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled 1073 #endif 1074 #ifndef MPU_PROTENSET0_PROTREG12_Enabled 1075 #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled 1076 #endif 1077 #ifndef MPU_PROTENSET0_PROTREG12_Set 1078 #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled 1079 #endif 1080 1081 #ifndef MPU_PROTENSET0_PROTREG11_Pos 1082 #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos 1083 #endif 1084 #ifndef MPU_PROTENSET0_PROTREG11_Msk 1085 #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk 1086 #endif 1087 #ifndef MPU_PROTENSET0_PROTREG11_Disabled 1088 #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled 1089 #endif 1090 #ifndef MPU_PROTENSET0_PROTREG11_Enabled 1091 #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled 1092 #endif 1093 #ifndef MPU_PROTENSET0_PROTREG11_Set 1094 #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled 1095 #endif 1096 1097 #ifndef MPU_PROTENSET0_PROTREG10_Pos 1098 #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos 1099 #endif 1100 #ifndef MPU_PROTENSET0_PROTREG10_Msk 1101 #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk 1102 #endif 1103 #ifndef MPU_PROTENSET0_PROTREG10_Disabled 1104 #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled 1105 #endif 1106 #ifndef MPU_PROTENSET0_PROTREG10_Enabled 1107 #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled 1108 #endif 1109 #ifndef MPU_PROTENSET0_PROTREG10_Set 1110 #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled 1111 #endif 1112 1113 #ifndef MPU_PROTENSET0_PROTREG9_Pos 1114 #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos 1115 #endif 1116 #ifndef MPU_PROTENSET0_PROTREG9_Msk 1117 #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk 1118 #endif 1119 #ifndef MPU_PROTENSET0_PROTREG9_Disabled 1120 #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled 1121 #endif 1122 #ifndef MPU_PROTENSET0_PROTREG9_Enabled 1123 #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled 1124 #endif 1125 #ifndef MPU_PROTENSET0_PROTREG9_Set 1126 #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled 1127 #endif 1128 1129 #ifndef MPU_PROTENSET0_PROTREG8_Pos 1130 #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos 1131 #endif 1132 #ifndef MPU_PROTENSET0_PROTREG8_Msk 1133 #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk 1134 #endif 1135 #ifndef MPU_PROTENSET0_PROTREG8_Disabled 1136 #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled 1137 #endif 1138 #ifndef MPU_PROTENSET0_PROTREG8_Enabled 1139 #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled 1140 #endif 1141 #ifndef MPU_PROTENSET0_PROTREG8_Set 1142 #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled 1143 #endif 1144 1145 #ifndef MPU_PROTENSET0_PROTREG7_Pos 1146 #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos 1147 #endif 1148 #ifndef MPU_PROTENSET0_PROTREG7_Msk 1149 #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk 1150 #endif 1151 #ifndef MPU_PROTENSET0_PROTREG7_Disabled 1152 #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled 1153 #endif 1154 #ifndef MPU_PROTENSET0_PROTREG7_Enabled 1155 #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled 1156 #endif 1157 #ifndef MPU_PROTENSET0_PROTREG7_Set 1158 #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled 1159 #endif 1160 1161 #ifndef MPU_PROTENSET0_PROTREG6_Pos 1162 #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos 1163 #endif 1164 #ifndef MPU_PROTENSET0_PROTREG6_Msk 1165 #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk 1166 #endif 1167 #ifndef MPU_PROTENSET0_PROTREG6_Disabled 1168 #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled 1169 #endif 1170 #ifndef MPU_PROTENSET0_PROTREG6_Enabled 1171 #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled 1172 #endif 1173 #ifndef MPU_PROTENSET0_PROTREG6_Set 1174 #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled 1175 #endif 1176 1177 #ifndef MPU_PROTENSET0_PROTREG5_Pos 1178 #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos 1179 #endif 1180 #ifndef MPU_PROTENSET0_PROTREG5_Msk 1181 #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk 1182 #endif 1183 #ifndef MPU_PROTENSET0_PROTREG5_Disabled 1184 #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled 1185 #endif 1186 #ifndef MPU_PROTENSET0_PROTREG5_Enabled 1187 #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled 1188 #endif 1189 #ifndef MPU_PROTENSET0_PROTREG5_Set 1190 #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled 1191 #endif 1192 1193 #ifndef MPU_PROTENSET0_PROTREG4_Pos 1194 #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos 1195 #endif 1196 #ifndef MPU_PROTENSET0_PROTREG4_Msk 1197 #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk 1198 #endif 1199 #ifndef MPU_PROTENSET0_PROTREG4_Disabled 1200 #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled 1201 #endif 1202 #ifndef MPU_PROTENSET0_PROTREG4_Enabled 1203 #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled 1204 #endif 1205 #ifndef MPU_PROTENSET0_PROTREG4_Set 1206 #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled 1207 #endif 1208 1209 #ifndef MPU_PROTENSET0_PROTREG3_Pos 1210 #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos 1211 #endif 1212 #ifndef MPU_PROTENSET0_PROTREG3_Msk 1213 #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk 1214 #endif 1215 #ifndef MPU_PROTENSET0_PROTREG3_Disabled 1216 #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled 1217 #endif 1218 #ifndef MPU_PROTENSET0_PROTREG3_Enabled 1219 #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled 1220 #endif 1221 #ifndef MPU_PROTENSET0_PROTREG3_Set 1222 #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled 1223 #endif 1224 1225 #ifndef MPU_PROTENSET0_PROTREG2_Pos 1226 #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos 1227 #endif 1228 #ifndef MPU_PROTENSET0_PROTREG2_Msk 1229 #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk 1230 #endif 1231 #ifndef MPU_PROTENSET0_PROTREG2_Disabled 1232 #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled 1233 #endif 1234 #ifndef MPU_PROTENSET0_PROTREG2_Enabled 1235 #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled 1236 #endif 1237 #ifndef MPU_PROTENSET0_PROTREG2_Set 1238 #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled 1239 #endif 1240 1241 #ifndef MPU_PROTENSET0_PROTREG1_Pos 1242 #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos 1243 #endif 1244 #ifndef MPU_PROTENSET0_PROTREG1_Msk 1245 #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk 1246 #endif 1247 #ifndef MPU_PROTENSET0_PROTREG1_Disabled 1248 #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled 1249 #endif 1250 #ifndef MPU_PROTENSET0_PROTREG1_Enabled 1251 #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled 1252 #endif 1253 #ifndef MPU_PROTENSET0_PROTREG1_Set 1254 #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled 1255 #endif 1256 1257 #ifndef MPU_PROTENSET0_PROTREG0_Pos 1258 #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos 1259 #endif 1260 #ifndef MPU_PROTENSET0_PROTREG0_Msk 1261 #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk 1262 #endif 1263 #ifndef MPU_PROTENSET0_PROTREG0_Disabled 1264 #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled 1265 #endif 1266 #ifndef MPU_PROTENSET0_PROTREG0_Enabled 1267 #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled 1268 #endif 1269 #ifndef MPU_PROTENSET0_PROTREG0_Set 1270 #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled 1271 #endif 1272 1273 1274 /* From nrf51_deprecated.h */ 1275 1276 /* NVMC */ 1277 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 1278 #ifndef ERASEPROTECTEDPAGE 1279 #define ERASEPROTECTEDPAGE ERASEPCR0 1280 #endif 1281 1282 1283 /* IRQ */ 1284 /* COMP module was eliminated. Adapted to nrf52 headers. */ 1285 #ifndef LPCOMP_COMP_IRQHandler 1286 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 1287 #endif 1288 #ifndef LPCOMP_COMP_IRQn 1289 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 1290 #endif 1291 1292 1293 /* REFSEL register redefined enumerated values and added some more. */ 1294 #ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling 1295 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd 1296 #endif 1297 #ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling 1298 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd 1299 #endif 1300 #ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling 1301 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd 1302 #endif 1303 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling 1304 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd 1305 #endif 1306 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling 1307 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd 1308 #endif 1309 #ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling 1310 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd 1311 #endif 1312 #ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling 1313 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd 1314 #endif 1315 1316 /* RADIO */ 1317 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 1318 #ifndef RADIO_CRCCNF_SKIP_ADDR_Pos 1319 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 1320 #endif 1321 #ifndef RADIO_CRCCNF_SKIP_ADDR_Msk 1322 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 1323 #endif 1324 #ifndef RADIO_CRCCNF_SKIP_ADDR_Include 1325 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 1326 #endif 1327 #ifndef RADIO_CRCCNF_SKIP_ADDR_Skip 1328 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 1329 #endif 1330 1331 1332 /* FICR */ 1333 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 1334 #ifndef DEVICEID0 1335 #define DEVICEID0 DEVICEID[0] 1336 #endif 1337 #ifndef DEVICEID1 1338 #define DEVICEID1 DEVICEID[1] 1339 #endif 1340 1341 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 1342 #ifndef ER0 1343 #define ER0 ER[0] 1344 #endif 1345 #ifndef ER1 1346 #define ER1 ER[1] 1347 #endif 1348 #ifndef ER2 1349 #define ER2 ER[2] 1350 #endif 1351 #ifndef ER3 1352 #define ER3 ER[3] 1353 #endif 1354 1355 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 1356 #ifndef IR0 1357 #define IR0 IR[0] 1358 #endif 1359 #ifndef IR1 1360 #define IR1 IR[1] 1361 #endif 1362 #ifndef IR2 1363 #define IR2 IR[2] 1364 #endif 1365 #ifndef IR3 1366 #define IR3 IR[3] 1367 #endif 1368 1369 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 1370 #ifndef DEVICEADDR0 1371 #define DEVICEADDR0 DEVICEADDR[0] 1372 #endif 1373 #ifndef DEVICEADDR1 1374 #define DEVICEADDR1 DEVICEADDR[1] 1375 #endif 1376 1377 1378 /* PPI */ 1379 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 1380 #ifndef TASKS_CHG0EN 1381 #define TASKS_CHG0EN TASKS_CHG[0].EN 1382 #endif 1383 #ifndef TASKS_CHG0DIS 1384 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 1385 #endif 1386 #ifndef TASKS_CHG1EN 1387 #define TASKS_CHG1EN TASKS_CHG[1].EN 1388 #endif 1389 #ifndef TASKS_CHG1DIS 1390 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 1391 #endif 1392 #ifndef TASKS_CHG2EN 1393 #define TASKS_CHG2EN TASKS_CHG[2].EN 1394 #endif 1395 #ifndef TASKS_CHG2DIS 1396 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 1397 #endif 1398 #ifndef TASKS_CHG3EN 1399 #define TASKS_CHG3EN TASKS_CHG[3].EN 1400 #endif 1401 #ifndef TASKS_CHG3DIS 1402 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 1403 #endif 1404 1405 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 1406 #ifndef CH0_EEP 1407 #define CH0_EEP CH[0].EEP 1408 #endif 1409 #ifndef CH0_TEP 1410 #define CH0_TEP CH[0].TEP 1411 #endif 1412 #ifndef CH1_EEP 1413 #define CH1_EEP CH[1].EEP 1414 #endif 1415 #ifndef CH1_TEP 1416 #define CH1_TEP CH[1].TEP 1417 #endif 1418 #ifndef CH2_EEP 1419 #define CH2_EEP CH[2].EEP 1420 #endif 1421 #ifndef CH2_TEP 1422 #define CH2_TEP CH[2].TEP 1423 #endif 1424 #ifndef CH3_EEP 1425 #define CH3_EEP CH[3].EEP 1426 #endif 1427 #ifndef CH3_TEP 1428 #define CH3_TEP CH[3].TEP 1429 #endif 1430 #ifndef CH4_EEP 1431 #define CH4_EEP CH[4].EEP 1432 #endif 1433 #ifndef CH4_TEP 1434 #define CH4_TEP CH[4].TEP 1435 #endif 1436 #ifndef CH5_EEP 1437 #define CH5_EEP CH[5].EEP 1438 #endif 1439 #ifndef CH5_TEP 1440 #define CH5_TEP CH[5].TEP 1441 #endif 1442 #ifndef CH6_EEP 1443 #define CH6_EEP CH[6].EEP 1444 #endif 1445 #ifndef CH6_TEP 1446 #define CH6_TEP CH[6].TEP 1447 #endif 1448 #ifndef CH7_EEP 1449 #define CH7_EEP CH[7].EEP 1450 #endif 1451 #ifndef CH7_TEP 1452 #define CH7_TEP CH[7].TEP 1453 #endif 1454 #ifndef CH8_EEP 1455 #define CH8_EEP CH[8].EEP 1456 #endif 1457 #ifndef CH8_TEP 1458 #define CH8_TEP CH[8].TEP 1459 #endif 1460 #ifndef CH9_EEP 1461 #define CH9_EEP CH[9].EEP 1462 #endif 1463 #ifndef CH9_TEP 1464 #define CH9_TEP CH[9].TEP 1465 #endif 1466 #ifndef CH10_EEP 1467 #define CH10_EEP CH[10].EEP 1468 #endif 1469 #ifndef CH10_TEP 1470 #define CH10_TEP CH[10].TEP 1471 #endif 1472 #ifndef CH11_EEP 1473 #define CH11_EEP CH[11].EEP 1474 #endif 1475 #ifndef CH11_TEP 1476 #define CH11_TEP CH[11].TEP 1477 #endif 1478 #ifndef CH12_EEP 1479 #define CH12_EEP CH[12].EEP 1480 #endif 1481 #ifndef CH12_TEP 1482 #define CH12_TEP CH[12].TEP 1483 #endif 1484 #ifndef CH13_EEP 1485 #define CH13_EEP CH[13].EEP 1486 #endif 1487 #ifndef CH13_TEP 1488 #define CH13_TEP CH[13].TEP 1489 #endif 1490 #ifndef CH14_EEP 1491 #define CH14_EEP CH[14].EEP 1492 #endif 1493 #ifndef CH14_TEP 1494 #define CH14_TEP CH[14].TEP 1495 #endif 1496 #ifndef CH15_EEP 1497 #define CH15_EEP CH[15].EEP 1498 #endif 1499 #ifndef CH15_TEP 1500 #define CH15_TEP CH[15].TEP 1501 #endif 1502 1503 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 1504 #ifndef CHG0 1505 #define CHG0 CHG[0] 1506 #endif 1507 #ifndef CHG1 1508 #define CHG1 CHG[1] 1509 #endif 1510 #ifndef CHG2 1511 #define CHG2 CHG[2] 1512 #endif 1513 #ifndef CHG3 1514 #define CHG3 CHG[3] 1515 #endif 1516 1517 /* All bitfield macros for the CHGx registers therefore changed name. */ 1518 #ifndef PPI_CHG0_CH15_Pos 1519 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 1520 #endif 1521 #ifndef PPI_CHG0_CH15_Msk 1522 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 1523 #endif 1524 #ifndef PPI_CHG0_CH15_Excluded 1525 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 1526 #endif 1527 #ifndef PPI_CHG0_CH15_Included 1528 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 1529 #endif 1530 1531 #ifndef PPI_CHG0_CH14_Pos 1532 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 1533 #endif 1534 #ifndef PPI_CHG0_CH14_Msk 1535 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 1536 #endif 1537 #ifndef PPI_CHG0_CH14_Excluded 1538 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 1539 #endif 1540 #ifndef PPI_CHG0_CH14_Included 1541 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 1542 #endif 1543 1544 #ifndef PPI_CHG0_CH13_Pos 1545 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 1546 #endif 1547 #ifndef PPI_CHG0_CH13_Msk 1548 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 1549 #endif 1550 #ifndef PPI_CHG0_CH13_Excluded 1551 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 1552 #endif 1553 #ifndef PPI_CHG0_CH13_Included 1554 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 1555 #endif 1556 1557 #ifndef PPI_CHG0_CH12_Pos 1558 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 1559 #endif 1560 #ifndef PPI_CHG0_CH12_Msk 1561 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 1562 #endif 1563 #ifndef PPI_CHG0_CH12_Excluded 1564 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 1565 #endif 1566 #ifndef PPI_CHG0_CH12_Included 1567 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 1568 #endif 1569 1570 #ifndef PPI_CHG0_CH11_Pos 1571 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 1572 #endif 1573 #ifndef PPI_CHG0_CH11_Msk 1574 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 1575 #endif 1576 #ifndef PPI_CHG0_CH11_Excluded 1577 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 1578 #endif 1579 #ifndef PPI_CHG0_CH11_Included 1580 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 1581 #endif 1582 1583 #ifndef PPI_CHG0_CH10_Pos 1584 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 1585 #endif 1586 #ifndef PPI_CHG0_CH10_Msk 1587 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 1588 #endif 1589 #ifndef PPI_CHG0_CH10_Excluded 1590 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 1591 #endif 1592 #ifndef PPI_CHG0_CH10_Included 1593 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 1594 #endif 1595 1596 #ifndef PPI_CHG0_CH9_Pos 1597 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 1598 #endif 1599 #ifndef PPI_CHG0_CH9_Msk 1600 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 1601 #endif 1602 #ifndef PPI_CHG0_CH9_Excluded 1603 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 1604 #endif 1605 #ifndef PPI_CHG0_CH9_Included 1606 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 1607 #endif 1608 1609 #ifndef PPI_CHG0_CH8_Pos 1610 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 1611 #endif 1612 #ifndef PPI_CHG0_CH8_Msk 1613 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 1614 #endif 1615 #ifndef PPI_CHG0_CH8_Excluded 1616 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 1617 #endif 1618 #ifndef PPI_CHG0_CH8_Included 1619 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 1620 #endif 1621 1622 #ifndef PPI_CHG0_CH7_Pos 1623 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 1624 #endif 1625 #ifndef PPI_CHG0_CH7_Msk 1626 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 1627 #endif 1628 #ifndef PPI_CHG0_CH7_Excluded 1629 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 1630 #endif 1631 #ifndef PPI_CHG0_CH7_Included 1632 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 1633 #endif 1634 1635 #ifndef PPI_CHG0_CH6_Pos 1636 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 1637 #endif 1638 #ifndef PPI_CHG0_CH6_Msk 1639 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 1640 #endif 1641 #ifndef PPI_CHG0_CH6_Excluded 1642 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 1643 #endif 1644 #ifndef PPI_CHG0_CH6_Included 1645 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 1646 #endif 1647 1648 #ifndef PPI_CHG0_CH5_Pos 1649 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 1650 #endif 1651 #ifndef PPI_CHG0_CH5_Msk 1652 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 1653 #endif 1654 #ifndef PPI_CHG0_CH5_Excluded 1655 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 1656 #endif 1657 #ifndef PPI_CHG0_CH5_Included 1658 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 1659 #endif 1660 1661 #ifndef PPI_CHG0_CH4_Pos 1662 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 1663 #endif 1664 #ifndef PPI_CHG0_CH4_Msk 1665 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 1666 #endif 1667 #ifndef PPI_CHG0_CH4_Excluded 1668 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 1669 #endif 1670 #ifndef PPI_CHG0_CH4_Included 1671 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 1672 #endif 1673 1674 #ifndef PPI_CHG0_CH3_Pos 1675 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 1676 #endif 1677 #ifndef PPI_CHG0_CH3_Msk 1678 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 1679 #endif 1680 #ifndef PPI_CHG0_CH3_Excluded 1681 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 1682 #endif 1683 #ifndef PPI_CHG0_CH3_Included 1684 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 1685 #endif 1686 1687 #ifndef PPI_CHG0_CH2_Pos 1688 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 1689 #endif 1690 #ifndef PPI_CHG0_CH2_Msk 1691 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 1692 #endif 1693 #ifndef PPI_CHG0_CH2_Excluded 1694 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 1695 #endif 1696 #ifndef PPI_CHG0_CH2_Included 1697 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 1698 #endif 1699 1700 #ifndef PPI_CHG0_CH1_Pos 1701 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 1702 #endif 1703 #ifndef PPI_CHG0_CH1_Msk 1704 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 1705 #endif 1706 #ifndef PPI_CHG0_CH1_Excluded 1707 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 1708 #endif 1709 #ifndef PPI_CHG0_CH1_Included 1710 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 1711 #endif 1712 1713 #ifndef PPI_CHG0_CH0_Pos 1714 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 1715 #endif 1716 #ifndef PPI_CHG0_CH0_Msk 1717 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 1718 #endif 1719 #ifndef PPI_CHG0_CH0_Excluded 1720 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 1721 #endif 1722 #ifndef PPI_CHG0_CH0_Included 1723 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 1724 #endif 1725 1726 #ifndef PPI_CHG1_CH15_Pos 1727 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 1728 #endif 1729 #ifndef PPI_CHG1_CH15_Msk 1730 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 1731 #endif 1732 #ifndef PPI_CHG1_CH15_Excluded 1733 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 1734 #endif 1735 #ifndef PPI_CHG1_CH15_Included 1736 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 1737 #endif 1738 1739 #ifndef PPI_CHG1_CH14_Pos 1740 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 1741 #endif 1742 #ifndef PPI_CHG1_CH14_Msk 1743 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 1744 #endif 1745 #ifndef PPI_CHG1_CH14_Excluded 1746 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 1747 #endif 1748 #ifndef PPI_CHG1_CH14_Included 1749 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 1750 #endif 1751 1752 #ifndef PPI_CHG1_CH13_Pos 1753 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 1754 #endif 1755 #ifndef PPI_CHG1_CH13_Msk 1756 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 1757 #endif 1758 #ifndef PPI_CHG1_CH13_Excluded 1759 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 1760 #endif 1761 #ifndef PPI_CHG1_CH13_Included 1762 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 1763 #endif 1764 1765 #ifndef PPI_CHG1_CH12_Pos 1766 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 1767 #endif 1768 #ifndef PPI_CHG1_CH12_Msk 1769 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 1770 #endif 1771 #ifndef PPI_CHG1_CH12_Excluded 1772 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 1773 #endif 1774 #ifndef PPI_CHG1_CH12_Included 1775 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 1776 #endif 1777 1778 #ifndef PPI_CHG1_CH11_Pos 1779 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 1780 #endif 1781 #ifndef PPI_CHG1_CH11_Msk 1782 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 1783 #endif 1784 #ifndef PPI_CHG1_CH11_Excluded 1785 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 1786 #endif 1787 #ifndef PPI_CHG1_CH11_Included 1788 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 1789 #endif 1790 1791 #ifndef PPI_CHG1_CH10_Pos 1792 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 1793 #endif 1794 #ifndef PPI_CHG1_CH10_Msk 1795 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 1796 #endif 1797 #ifndef PPI_CHG1_CH10_Excluded 1798 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 1799 #endif 1800 #ifndef PPI_CHG1_CH10_Included 1801 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 1802 #endif 1803 1804 #ifndef PPI_CHG1_CH9_Pos 1805 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 1806 #endif 1807 #ifndef PPI_CHG1_CH9_Msk 1808 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 1809 #endif 1810 #ifndef PPI_CHG1_CH9_Excluded 1811 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 1812 #endif 1813 #ifndef PPI_CHG1_CH9_Included 1814 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 1815 #endif 1816 1817 #ifndef PPI_CHG1_CH8_Pos 1818 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 1819 #endif 1820 #ifndef PPI_CHG1_CH8_Msk 1821 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 1822 #endif 1823 #ifndef PPI_CHG1_CH8_Excluded 1824 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 1825 #endif 1826 #ifndef PPI_CHG1_CH8_Included 1827 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 1828 #endif 1829 1830 #ifndef PPI_CHG1_CH7_Pos 1831 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 1832 #endif 1833 #ifndef PPI_CHG1_CH7_Msk 1834 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 1835 #endif 1836 #ifndef PPI_CHG1_CH7_Excluded 1837 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 1838 #endif 1839 #ifndef PPI_CHG1_CH7_Included 1840 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 1841 #endif 1842 1843 #ifndef PPI_CHG1_CH6_Pos 1844 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 1845 #endif 1846 #ifndef PPI_CHG1_CH6_Msk 1847 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 1848 #endif 1849 #ifndef PPI_CHG1_CH6_Excluded 1850 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 1851 #endif 1852 #ifndef PPI_CHG1_CH6_Included 1853 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 1854 #endif 1855 1856 #ifndef PPI_CHG1_CH5_Pos 1857 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 1858 #endif 1859 #ifndef PPI_CHG1_CH5_Msk 1860 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 1861 #endif 1862 #ifndef PPI_CHG1_CH5_Excluded 1863 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 1864 #endif 1865 #ifndef PPI_CHG1_CH5_Included 1866 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 1867 #endif 1868 1869 #ifndef PPI_CHG1_CH4_Pos 1870 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 1871 #endif 1872 #ifndef PPI_CHG1_CH4_Msk 1873 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 1874 #endif 1875 #ifndef PPI_CHG1_CH4_Excluded 1876 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 1877 #endif 1878 #ifndef PPI_CHG1_CH4_Included 1879 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 1880 #endif 1881 1882 #ifndef PPI_CHG1_CH3_Pos 1883 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 1884 #endif 1885 #ifndef PPI_CHG1_CH3_Msk 1886 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 1887 #endif 1888 #ifndef PPI_CHG1_CH3_Excluded 1889 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 1890 #endif 1891 #ifndef PPI_CHG1_CH3_Included 1892 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 1893 #endif 1894 1895 #ifndef PPI_CHG1_CH2_Pos 1896 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 1897 #endif 1898 #ifndef PPI_CHG1_CH2_Msk 1899 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 1900 #endif 1901 #ifndef PPI_CHG1_CH2_Excluded 1902 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 1903 #endif 1904 #ifndef PPI_CHG1_CH2_Included 1905 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 1906 #endif 1907 1908 #ifndef PPI_CHG1_CH1_Pos 1909 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 1910 #endif 1911 #ifndef PPI_CHG1_CH1_Msk 1912 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 1913 #endif 1914 #ifndef PPI_CHG1_CH1_Excluded 1915 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 1916 #endif 1917 #ifndef PPI_CHG1_CH1_Included 1918 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 1919 #endif 1920 1921 #ifndef PPI_CHG1_CH0_Pos 1922 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 1923 #endif 1924 #ifndef PPI_CHG1_CH0_Msk 1925 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 1926 #endif 1927 #ifndef PPI_CHG1_CH0_Excluded 1928 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 1929 #endif 1930 #ifndef PPI_CHG1_CH0_Included 1931 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 1932 #endif 1933 1934 #ifndef PPI_CHG2_CH15_Pos 1935 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 1936 #endif 1937 #ifndef PPI_CHG2_CH15_Msk 1938 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 1939 #endif 1940 #ifndef PPI_CHG2_CH15_Excluded 1941 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 1942 #endif 1943 #ifndef PPI_CHG2_CH15_Included 1944 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 1945 #endif 1946 1947 #ifndef PPI_CHG2_CH14_Pos 1948 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 1949 #endif 1950 #ifndef PPI_CHG2_CH14_Msk 1951 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 1952 #endif 1953 #ifndef PPI_CHG2_CH14_Excluded 1954 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 1955 #endif 1956 #ifndef PPI_CHG2_CH14_Included 1957 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 1958 #endif 1959 1960 #ifndef PPI_CHG2_CH13_Pos 1961 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 1962 #endif 1963 #ifndef PPI_CHG2_CH13_Msk 1964 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 1965 #endif 1966 #ifndef PPI_CHG2_CH13_Excluded 1967 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 1968 #endif 1969 #ifndef PPI_CHG2_CH13_Included 1970 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 1971 #endif 1972 1973 #ifndef PPI_CHG2_CH12_Pos 1974 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 1975 #endif 1976 #ifndef PPI_CHG2_CH12_Msk 1977 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 1978 #endif 1979 #ifndef PPI_CHG2_CH12_Excluded 1980 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 1981 #endif 1982 #ifndef PPI_CHG2_CH12_Included 1983 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 1984 #endif 1985 1986 #ifndef PPI_CHG2_CH11_Pos 1987 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 1988 #endif 1989 #ifndef PPI_CHG2_CH11_Msk 1990 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 1991 #endif 1992 #ifndef PPI_CHG2_CH11_Excluded 1993 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 1994 #endif 1995 #ifndef PPI_CHG2_CH11_Included 1996 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 1997 #endif 1998 1999 #ifndef PPI_CHG2_CH10_Pos 2000 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 2001 #endif 2002 #ifndef PPI_CHG2_CH10_Msk 2003 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 2004 #endif 2005 #ifndef PPI_CHG2_CH10_Excluded 2006 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 2007 #endif 2008 #ifndef PPI_CHG2_CH10_Included 2009 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 2010 #endif 2011 2012 #ifndef PPI_CHG2_CH9_Pos 2013 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 2014 #endif 2015 #ifndef PPI_CHG2_CH9_Msk 2016 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 2017 #endif 2018 #ifndef PPI_CHG2_CH9_Excluded 2019 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 2020 #endif 2021 #ifndef PPI_CHG2_CH9_Included 2022 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 2023 #endif 2024 2025 #ifndef PPI_CHG2_CH8_Pos 2026 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 2027 #endif 2028 #ifndef PPI_CHG2_CH8_Msk 2029 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 2030 #endif 2031 #ifndef PPI_CHG2_CH8_Excluded 2032 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 2033 #endif 2034 #ifndef PPI_CHG2_CH8_Included 2035 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 2036 #endif 2037 2038 #ifndef PPI_CHG2_CH7_Pos 2039 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 2040 #endif 2041 #ifndef PPI_CHG2_CH7_Msk 2042 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 2043 #endif 2044 #ifndef PPI_CHG2_CH7_Excluded 2045 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 2046 #endif 2047 #ifndef PPI_CHG2_CH7_Included 2048 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 2049 #endif 2050 2051 #ifndef PPI_CHG2_CH6_Pos 2052 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 2053 #endif 2054 #ifndef PPI_CHG2_CH6_Msk 2055 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 2056 #endif 2057 #ifndef PPI_CHG2_CH6_Excluded 2058 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 2059 #endif 2060 #ifndef PPI_CHG2_CH6_Included 2061 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 2062 #endif 2063 2064 #ifndef PPI_CHG2_CH5_Pos 2065 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 2066 #endif 2067 #ifndef PPI_CHG2_CH5_Msk 2068 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 2069 #endif 2070 #ifndef PPI_CHG2_CH5_Excluded 2071 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 2072 #endif 2073 #ifndef PPI_CHG2_CH5_Included 2074 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 2075 #endif 2076 2077 #ifndef PPI_CHG2_CH4_Pos 2078 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 2079 #endif 2080 #ifndef PPI_CHG2_CH4_Msk 2081 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 2082 #endif 2083 #ifndef PPI_CHG2_CH4_Excluded 2084 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 2085 #endif 2086 #ifndef PPI_CHG2_CH4_Included 2087 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 2088 #endif 2089 2090 #ifndef PPI_CHG2_CH3_Pos 2091 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 2092 #endif 2093 #ifndef PPI_CHG2_CH3_Msk 2094 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 2095 #endif 2096 #ifndef PPI_CHG2_CH3_Excluded 2097 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 2098 #endif 2099 #ifndef PPI_CHG2_CH3_Included 2100 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 2101 #endif 2102 2103 #ifndef PPI_CHG2_CH2_Pos 2104 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 2105 #endif 2106 #ifndef PPI_CHG2_CH2_Msk 2107 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 2108 #endif 2109 #ifndef PPI_CHG2_CH2_Excluded 2110 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 2111 #endif 2112 #ifndef PPI_CHG2_CH2_Included 2113 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 2114 #endif 2115 2116 #ifndef PPI_CHG2_CH1_Pos 2117 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 2118 #endif 2119 #ifndef PPI_CHG2_CH1_Msk 2120 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 2121 #endif 2122 #ifndef PPI_CHG2_CH1_Excluded 2123 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 2124 #endif 2125 #ifndef PPI_CHG2_CH1_Included 2126 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 2127 #endif 2128 2129 #ifndef PPI_CHG2_CH0_Pos 2130 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 2131 #endif 2132 #ifndef PPI_CHG2_CH0_Msk 2133 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 2134 #endif 2135 #ifndef PPI_CHG2_CH0_Excluded 2136 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 2137 #endif 2138 #ifndef PPI_CHG2_CH0_Included 2139 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 2140 #endif 2141 2142 #ifndef PPI_CHG3_CH15_Pos 2143 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 2144 #endif 2145 #ifndef PPI_CHG3_CH15_Msk 2146 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 2147 #endif 2148 #ifndef PPI_CHG3_CH15_Excluded 2149 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 2150 #endif 2151 #ifndef PPI_CHG3_CH15_Included 2152 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 2153 #endif 2154 2155 #ifndef PPI_CHG3_CH14_Pos 2156 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 2157 #endif 2158 #ifndef PPI_CHG3_CH14_Msk 2159 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 2160 #endif 2161 #ifndef PPI_CHG3_CH14_Excluded 2162 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 2163 #endif 2164 #ifndef PPI_CHG3_CH14_Included 2165 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 2166 #endif 2167 2168 #ifndef PPI_CHG3_CH13_Pos 2169 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 2170 #endif 2171 #ifndef PPI_CHG3_CH13_Msk 2172 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 2173 #endif 2174 #ifndef PPI_CHG3_CH13_Excluded 2175 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 2176 #endif 2177 #ifndef PPI_CHG3_CH13_Included 2178 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 2179 #endif 2180 2181 #ifndef PPI_CHG3_CH12_Pos 2182 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 2183 #endif 2184 #ifndef PPI_CHG3_CH12_Msk 2185 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 2186 #endif 2187 #ifndef PPI_CHG3_CH12_Excluded 2188 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 2189 #endif 2190 #ifndef PPI_CHG3_CH12_Included 2191 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 2192 #endif 2193 2194 #ifndef PPI_CHG3_CH11_Pos 2195 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 2196 #endif 2197 #ifndef PPI_CHG3_CH11_Msk 2198 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 2199 #endif 2200 #ifndef PPI_CHG3_CH11_Excluded 2201 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 2202 #endif 2203 #ifndef PPI_CHG3_CH11_Included 2204 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 2205 #endif 2206 2207 #ifndef PPI_CHG3_CH10_Pos 2208 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 2209 #endif 2210 #ifndef PPI_CHG3_CH10_Msk 2211 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 2212 #endif 2213 #ifndef PPI_CHG3_CH10_Excluded 2214 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 2215 #endif 2216 #ifndef PPI_CHG3_CH10_Included 2217 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 2218 #endif 2219 2220 #ifndef PPI_CHG3_CH9_Pos 2221 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 2222 #endif 2223 #ifndef PPI_CHG3_CH9_Msk 2224 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 2225 #endif 2226 #ifndef PPI_CHG3_CH9_Excluded 2227 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 2228 #endif 2229 #ifndef PPI_CHG3_CH9_Included 2230 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 2231 #endif 2232 2233 #ifndef PPI_CHG3_CH8_Pos 2234 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 2235 #endif 2236 #ifndef PPI_CHG3_CH8_Msk 2237 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 2238 #endif 2239 #ifndef PPI_CHG3_CH8_Excluded 2240 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 2241 #endif 2242 #ifndef PPI_CHG3_CH8_Included 2243 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 2244 #endif 2245 2246 #ifndef PPI_CHG3_CH7_Pos 2247 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 2248 #endif 2249 #ifndef PPI_CHG3_CH7_Msk 2250 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 2251 #endif 2252 #ifndef PPI_CHG3_CH7_Excluded 2253 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 2254 #endif 2255 #ifndef PPI_CHG3_CH7_Included 2256 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 2257 #endif 2258 2259 #ifndef PPI_CHG3_CH6_Pos 2260 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 2261 #endif 2262 #ifndef PPI_CHG3_CH6_Msk 2263 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 2264 #endif 2265 #ifndef PPI_CHG3_CH6_Excluded 2266 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 2267 #endif 2268 #ifndef PPI_CHG3_CH6_Included 2269 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 2270 #endif 2271 2272 #ifndef PPI_CHG3_CH5_Pos 2273 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 2274 #endif 2275 #ifndef PPI_CHG3_CH5_Msk 2276 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 2277 #endif 2278 #ifndef PPI_CHG3_CH5_Excluded 2279 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 2280 #endif 2281 #ifndef PPI_CHG3_CH5_Included 2282 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 2283 #endif 2284 2285 #ifndef PPI_CHG3_CH4_Pos 2286 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 2287 #endif 2288 #ifndef PPI_CHG3_CH4_Msk 2289 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 2290 #endif 2291 #ifndef PPI_CHG3_CH4_Excluded 2292 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 2293 #endif 2294 #ifndef PPI_CHG3_CH4_Included 2295 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 2296 #endif 2297 2298 #ifndef PPI_CHG3_CH3_Pos 2299 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 2300 #endif 2301 #ifndef PPI_CHG3_CH3_Msk 2302 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 2303 #endif 2304 #ifndef PPI_CHG3_CH3_Excluded 2305 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 2306 #endif 2307 #ifndef PPI_CHG3_CH3_Included 2308 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 2309 #endif 2310 2311 #ifndef PPI_CHG3_CH2_Pos 2312 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 2313 #endif 2314 #ifndef PPI_CHG3_CH2_Msk 2315 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 2316 #endif 2317 #ifndef PPI_CHG3_CH2_Excluded 2318 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 2319 #endif 2320 #ifndef PPI_CHG3_CH2_Included 2321 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 2322 #endif 2323 2324 #ifndef PPI_CHG3_CH1_Pos 2325 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 2326 #endif 2327 #ifndef PPI_CHG3_CH1_Msk 2328 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 2329 #endif 2330 #ifndef PPI_CHG3_CH1_Excluded 2331 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 2332 #endif 2333 #ifndef PPI_CHG3_CH1_Included 2334 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 2335 #endif 2336 2337 #ifndef PPI_CHG3_CH0_Pos 2338 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 2339 #endif 2340 #ifndef PPI_CHG3_CH0_Msk 2341 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 2342 #endif 2343 #ifndef PPI_CHG3_CH0_Excluded 2344 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 2345 #endif 2346 #ifndef PPI_CHG3_CH0_Included 2347 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 2348 #endif 2349 2350 2351 2352 /*lint --flb "Leave library region" */ 2353 2354 #endif /* NRF51_TO_NRF52_H */ 2355 2356