1 /* 2 3 Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 4 5 Redistribution and use in source and binary forms, with or without 6 modification, are permitted provided that the following conditions are met: 7 8 1. Redistributions of source code must retain the above copyright notice, this 9 list of conditions and the following disclaimer. 10 11 2. Redistributions in binary form must reproduce the above copyright 12 notice, this list of conditions and the following disclaimer in the 13 documentation and/or other materials provided with the distribution. 14 15 3. Neither the name of Nordic Semiconductor ASA nor the names of its 16 contributors may be used to endorse or promote products derived from this 17 software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. 30 31 */ 32 33 #ifndef NRF51_TO_NRF52840_H 34 #define NRF51_TO_NRF52840_H 35 36 /*lint ++flb "Enter library region */ 37 38 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52840 devices. 39 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 40 * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros 41 * from the nrf51_deprecated.h file. */ 42 43 44 /* IRQ */ 45 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 46 #ifndef UART0_IRQHandler 47 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 48 #endif 49 #ifndef SPI0_TWI0_IRQHandler 50 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 51 #endif 52 #ifndef SPI1_TWI1_IRQHandler 53 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 54 #endif 55 #ifndef ADC_IRQHandler 56 #define ADC_IRQHandler SAADC_IRQHandler 57 #endif 58 #ifndef LPCOMP_IRQHandler 59 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 60 #endif 61 #ifndef SWI0_IRQHandler 62 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 63 #endif 64 #ifndef SWI1_IRQHandler 65 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 66 #endif 67 #ifndef SWI2_IRQHandler 68 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 69 #endif 70 #ifndef SWI3_IRQHandler 71 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 72 #endif 73 #ifndef SWI4_IRQHandler 74 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 75 #endif 76 #ifndef SWI5_IRQHandler 77 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 78 #endif 79 80 #ifndef UART0_IRQn 81 #define UART0_IRQn UARTE0_UART0_IRQn 82 #endif 83 #ifndef SPI0_TWI0_IRQn 84 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 85 #endif 86 #ifndef SPI1_TWI1_IRQn 87 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 88 #endif 89 #ifndef ADC_IRQn 90 #define ADC_IRQn SAADC_IRQn 91 #endif 92 #ifndef LPCOMP_IRQn 93 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 94 #endif 95 #ifndef SWI0_IRQn 96 #define SWI0_IRQn SWI0_EGU0_IRQn 97 #endif 98 #ifndef SWI1_IRQn 99 #define SWI1_IRQn SWI1_EGU1_IRQn 100 #endif 101 #ifndef SWI2_IRQn 102 #define SWI2_IRQn SWI2_EGU2_IRQn 103 #endif 104 #ifndef SWI3_IRQn 105 #define SWI3_IRQn SWI3_EGU3_IRQn 106 #endif 107 #ifndef SWI4_IRQn 108 #define SWI4_IRQn SWI4_EGU4_IRQn 109 #endif 110 #ifndef SWI5_IRQn 111 #define SWI5_IRQn SWI5_EGU5_IRQn 112 #endif 113 114 115 /* UICR */ 116 /* Register RBPCONF was renamed to APPROTECT. */ 117 #ifndef RBPCONF 118 #define RBPCONF APPROTECT 119 #endif 120 121 #ifndef UICR_RBPCONF_PALL_Pos 122 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 123 #endif 124 #ifndef UICR_RBPCONF_PALL_Msk 125 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 126 #endif 127 #ifndef UICR_RBPCONF_PALL_Enabled 128 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 129 #endif 130 #ifndef UICR_RBPCONF_PALL_Disabled 131 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 132 #endif 133 134 135 /* GPIO */ 136 /* GPIO port was renamed to P0. */ 137 #ifndef NRF_GPIO 138 #define NRF_GPIO NRF_P0 139 #endif 140 #ifndef NRF_GPIO_BASE 141 #define NRF_GPIO_BASE NRF_P0_BASE 142 #endif 143 144 145 /* QDEC */ 146 /* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ 147 #ifndef PSELLED 148 #define PSELLED PSEL.LED 149 #endif 150 #ifndef PSELA 151 #define PSELA PSEL.A 152 #endif 153 #ifndef PSELB 154 #define PSELB PSEL.B 155 #endif 156 157 158 /* SPIS */ 159 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 160 #ifndef PSELSCK 161 #define PSELSCK PSEL.SCK 162 #endif 163 #ifndef PSELMISO 164 #define PSELMISO PSEL.MISO 165 #endif 166 #ifndef PSELMOSI 167 #define PSELMOSI PSEL.MOSI 168 #endif 169 #ifndef PSELCSN 170 #define PSELCSN PSEL.CSN 171 #endif 172 173 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 174 #ifndef RXDPTR 175 #define RXDPTR RXD.PTR 176 #endif 177 #ifndef MAXRX 178 #define MAXRX RXD.MAXCNT 179 #endif 180 #ifndef AMOUNTRX 181 #define AMOUNTRX RXD.AMOUNT 182 #endif 183 184 #ifndef SPIS_MAXRX_MAXRX_Pos 185 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 186 #endif 187 #ifndef SPIS_MAXRX_MAXRX_Msk 188 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 189 #endif 190 191 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos 192 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 193 #endif 194 #ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk 195 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 196 #endif 197 198 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 199 #ifndef TXDPTR 200 #define TXDPTR TXD.PTR 201 #endif 202 #ifndef MAXTX 203 #define MAXTX TXD.MAXCNT 204 #endif 205 #ifndef AMOUNTTX 206 #define AMOUNTTX TXD.AMOUNT 207 #endif 208 209 #ifndef SPIS_MAXTX_MAXTX_Pos 210 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 211 #endif 212 #ifndef SPIS_MAXTX_MAXTX_Msk 213 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 214 #endif 215 216 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos 217 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 218 #endif 219 #ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk 220 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 221 #endif 222 223 224 /* UART */ 225 /* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ 226 #ifndef PSELRTS 227 #define PSELRTS PSEL.RTS 228 #endif 229 #ifndef PSELTXD 230 #define PSELTXD PSEL.TXD 231 #endif 232 #ifndef PSELCTS 233 #define PSELCTS PSEL.CTS 234 #endif 235 #ifndef PSELRXD 236 #define PSELRXD PSEL.RXD 237 #endif 238 239 /* TWI */ 240 /* The registers PSELSCL, PSELSDA were restructured into a struct. */ 241 #ifndef PSELSCL 242 #define PSELSCL PSEL.SCL 243 #endif 244 #ifndef PSELSDA 245 #define PSELSDA PSEL.SDA 246 #endif 247 248 249 /* From nrf51_deprecated.h */ 250 251 /* NVMC */ 252 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 253 #ifndef ERASEPROTECTEDPAGE 254 #define ERASEPROTECTEDPAGE ERASEPCR0 255 #endif 256 257 258 /* IRQ */ 259 /* COMP module was eliminated. Adapted to nrf52840 headers. */ 260 #ifndef LPCOMP_COMP_IRQHandler 261 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 262 #endif 263 #ifndef LPCOMP_COMP_IRQn 264 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 265 #endif 266 267 268 /* REFSEL register redefined enumerated values and added some more. */ 269 #ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling 270 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd 271 #endif 272 #ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling 273 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd 274 #endif 275 #ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling 276 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd 277 #endif 278 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling 279 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd 280 #endif 281 #ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling 282 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd 283 #endif 284 #ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling 285 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd 286 #endif 287 #ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling 288 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd 289 #endif 290 291 292 /* RADIO */ 293 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 294 #ifndef RADIO_CRCCNF_SKIP_ADDR_Pos 295 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 296 #endif 297 #ifndef RADIO_CRCCNF_SKIP_ADDR_Msk 298 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 299 #endif 300 #ifndef RADIO_CRCCNF_SKIP_ADDR_Include 301 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 302 #endif 303 #ifndef RADIO_CRCCNF_SKIP_ADDR_Skip 304 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 305 #endif 306 307 308 /* FICR */ 309 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 310 #ifndef DEVICEID0 311 #define DEVICEID0 DEVICEID[0] 312 #endif 313 #ifndef DEVICEID1 314 #define DEVICEID1 DEVICEID[1] 315 #endif 316 317 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 318 #ifndef ER0 319 #define ER0 ER[0] 320 #endif 321 #ifndef ER1 322 #define ER1 ER[1] 323 #endif 324 #ifndef ER2 325 #define ER2 ER[2] 326 #endif 327 #ifndef ER3 328 #define ER3 ER[3] 329 #endif 330 331 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 332 #ifndef IR0 333 #define IR0 IR[0] 334 #endif 335 #ifndef IR1 336 #define IR1 IR[1] 337 #endif 338 #ifndef IR2 339 #define IR2 IR[2] 340 #endif 341 #ifndef IR3 342 #define IR3 IR[3] 343 #endif 344 345 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 346 #ifndef DEVICEADDR0 347 #define DEVICEADDR0 DEVICEADDR[0] 348 #endif 349 #ifndef DEVICEADDR1 350 #define DEVICEADDR1 DEVICEADDR[1] 351 #endif 352 353 354 /* PPI */ 355 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 356 #ifndef TASKS_CHG0EN 357 #define TASKS_CHG0EN TASKS_CHG[0].EN 358 #endif 359 #ifndef TASKS_CHG0DIS 360 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 361 #endif 362 #ifndef TASKS_CHG1EN 363 #define TASKS_CHG1EN TASKS_CHG[1].EN 364 #endif 365 #ifndef TASKS_CHG1DIS 366 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 367 #endif 368 #ifndef TASKS_CHG2EN 369 #define TASKS_CHG2EN TASKS_CHG[2].EN 370 #endif 371 #ifndef TASKS_CHG2DIS 372 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 373 #endif 374 #ifndef TASKS_CHG3EN 375 #define TASKS_CHG3EN TASKS_CHG[3].EN 376 #endif 377 #ifndef TASKS_CHG3DIS 378 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 379 #endif 380 381 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 382 #ifndef CH0_EEP 383 #define CH0_EEP CH[0].EEP 384 #endif 385 #ifndef CH0_TEP 386 #define CH0_TEP CH[0].TEP 387 #endif 388 #ifndef CH1_EEP 389 #define CH1_EEP CH[1].EEP 390 #endif 391 #ifndef CH1_TEP 392 #define CH1_TEP CH[1].TEP 393 #endif 394 #ifndef CH2_EEP 395 #define CH2_EEP CH[2].EEP 396 #endif 397 #ifndef CH2_TEP 398 #define CH2_TEP CH[2].TEP 399 #endif 400 #ifndef CH3_EEP 401 #define CH3_EEP CH[3].EEP 402 #endif 403 #ifndef CH3_TEP 404 #define CH3_TEP CH[3].TEP 405 #endif 406 #ifndef CH4_EEP 407 #define CH4_EEP CH[4].EEP 408 #endif 409 #ifndef CH4_TEP 410 #define CH4_TEP CH[4].TEP 411 #endif 412 #ifndef CH5_EEP 413 #define CH5_EEP CH[5].EEP 414 #endif 415 #ifndef CH5_TEP 416 #define CH5_TEP CH[5].TEP 417 #endif 418 #ifndef CH6_EEP 419 #define CH6_EEP CH[6].EEP 420 #endif 421 #ifndef CH6_TEP 422 #define CH6_TEP CH[6].TEP 423 #endif 424 #ifndef CH7_EEP 425 #define CH7_EEP CH[7].EEP 426 #endif 427 #ifndef CH7_TEP 428 #define CH7_TEP CH[7].TEP 429 #endif 430 #ifndef CH8_EEP 431 #define CH8_EEP CH[8].EEP 432 #endif 433 #ifndef CH8_TEP 434 #define CH8_TEP CH[8].TEP 435 #endif 436 #ifndef CH9_EEP 437 #define CH9_EEP CH[9].EEP 438 #endif 439 #ifndef CH9_TEP 440 #define CH9_TEP CH[9].TEP 441 #endif 442 #ifndef CH10_EEP 443 #define CH10_EEP CH[10].EEP 444 #endif 445 #ifndef CH10_TEP 446 #define CH10_TEP CH[10].TEP 447 #endif 448 #ifndef CH11_EEP 449 #define CH11_EEP CH[11].EEP 450 #endif 451 #ifndef CH11_TEP 452 #define CH11_TEP CH[11].TEP 453 #endif 454 #ifndef CH12_EEP 455 #define CH12_EEP CH[12].EEP 456 #endif 457 #ifndef CH12_TEP 458 #define CH12_TEP CH[12].TEP 459 #endif 460 #ifndef CH13_EEP 461 #define CH13_EEP CH[13].EEP 462 #endif 463 #ifndef CH13_TEP 464 #define CH13_TEP CH[13].TEP 465 #endif 466 #ifndef CH14_EEP 467 #define CH14_EEP CH[14].EEP 468 #endif 469 #ifndef CH14_TEP 470 #define CH14_TEP CH[14].TEP 471 #endif 472 #ifndef CH15_EEP 473 #define CH15_EEP CH[15].EEP 474 #endif 475 #ifndef CH15_TEP 476 #define CH15_TEP CH[15].TEP 477 #endif 478 479 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 480 #ifndef CHG0 481 #define CHG0 CHG[0] 482 #endif 483 #ifndef CHG1 484 #define CHG1 CHG[1] 485 #endif 486 #ifndef CHG2 487 #define CHG2 CHG[2] 488 #endif 489 #ifndef CHG3 490 #define CHG3 CHG[3] 491 #endif 492 493 /* All bitfield macros for the CHGx registers therefore changed name. */ 494 #ifndef PPI_CHG0_CH15_Pos 495 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 496 #endif 497 #ifndef PPI_CHG0_CH15_Msk 498 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 499 #endif 500 #ifndef PPI_CHG0_CH15_Excluded 501 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 502 #endif 503 #ifndef PPI_CHG0_CH15_Included 504 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 505 #endif 506 507 #ifndef PPI_CHG0_CH14_Pos 508 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 509 #endif 510 #ifndef PPI_CHG0_CH14_Msk 511 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 512 #endif 513 #ifndef PPI_CHG0_CH14_Excluded 514 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 515 #endif 516 #ifndef PPI_CHG0_CH14_Included 517 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 518 #endif 519 520 #ifndef PPI_CHG0_CH13_Pos 521 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 522 #endif 523 #ifndef PPI_CHG0_CH13_Msk 524 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 525 #endif 526 #ifndef PPI_CHG0_CH13_Excluded 527 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 528 #endif 529 #ifndef PPI_CHG0_CH13_Included 530 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 531 #endif 532 533 #ifndef PPI_CHG0_CH12_Pos 534 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 535 #endif 536 #ifndef PPI_CHG0_CH12_Msk 537 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 538 #endif 539 #ifndef PPI_CHG0_CH12_Excluded 540 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 541 #endif 542 #ifndef PPI_CHG0_CH12_Included 543 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 544 #endif 545 546 #ifndef PPI_CHG0_CH11_Pos 547 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 548 #endif 549 #ifndef PPI_CHG0_CH11_Msk 550 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 551 #endif 552 #ifndef PPI_CHG0_CH11_Excluded 553 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 554 #endif 555 #ifndef PPI_CHG0_CH11_Included 556 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 557 #endif 558 559 #ifndef PPI_CHG0_CH10_Pos 560 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 561 #endif 562 #ifndef PPI_CHG0_CH10_Msk 563 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 564 #endif 565 #ifndef PPI_CHG0_CH10_Excluded 566 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 567 #endif 568 #ifndef PPI_CHG0_CH10_Included 569 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 570 #endif 571 572 #ifndef PPI_CHG0_CH9_Pos 573 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 574 #endif 575 #ifndef PPI_CHG0_CH9_Msk 576 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 577 #endif 578 #ifndef PPI_CHG0_CH9_Excluded 579 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 580 #endif 581 #ifndef PPI_CHG0_CH9_Included 582 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 583 #endif 584 585 #ifndef PPI_CHG0_CH8_Pos 586 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 587 #endif 588 #ifndef PPI_CHG0_CH8_Msk 589 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 590 #endif 591 #ifndef PPI_CHG0_CH8_Excluded 592 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 593 #endif 594 #ifndef PPI_CHG0_CH8_Included 595 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 596 #endif 597 598 #ifndef PPI_CHG0_CH7_Pos 599 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 600 #endif 601 #ifndef PPI_CHG0_CH7_Msk 602 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 603 #endif 604 #ifndef PPI_CHG0_CH7_Excluded 605 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 606 #endif 607 #ifndef PPI_CHG0_CH7_Included 608 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 609 #endif 610 611 #ifndef PPI_CHG0_CH6_Pos 612 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 613 #endif 614 #ifndef PPI_CHG0_CH6_Msk 615 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 616 #endif 617 #ifndef PPI_CHG0_CH6_Excluded 618 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 619 #endif 620 #ifndef PPI_CHG0_CH6_Included 621 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 622 #endif 623 624 #ifndef PPI_CHG0_CH5_Pos 625 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 626 #endif 627 #ifndef PPI_CHG0_CH5_Msk 628 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 629 #endif 630 #ifndef PPI_CHG0_CH5_Excluded 631 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 632 #endif 633 #ifndef PPI_CHG0_CH5_Included 634 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 635 #endif 636 637 #ifndef PPI_CHG0_CH4_Pos 638 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 639 #endif 640 #ifndef PPI_CHG0_CH4_Msk 641 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 642 #endif 643 #ifndef PPI_CHG0_CH4_Excluded 644 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 645 #endif 646 #ifndef PPI_CHG0_CH4_Included 647 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 648 #endif 649 650 #ifndef PPI_CHG0_CH3_Pos 651 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 652 #endif 653 #ifndef PPI_CHG0_CH3_Msk 654 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 655 #endif 656 #ifndef PPI_CHG0_CH3_Excluded 657 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 658 #endif 659 #ifndef PPI_CHG0_CH3_Included 660 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 661 #endif 662 663 #ifndef PPI_CHG0_CH2_Pos 664 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 665 #endif 666 #ifndef PPI_CHG0_CH2_Msk 667 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 668 #endif 669 #ifndef PPI_CHG0_CH2_Excluded 670 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 671 #endif 672 #ifndef PPI_CHG0_CH2_Included 673 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 674 #endif 675 676 #ifndef PPI_CHG0_CH1_Pos 677 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 678 #endif 679 #ifndef PPI_CHG0_CH1_Msk 680 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 681 #endif 682 #ifndef PPI_CHG0_CH1_Excluded 683 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 684 #endif 685 #ifndef PPI_CHG0_CH1_Included 686 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 687 #endif 688 689 #ifndef PPI_CHG0_CH0_Pos 690 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 691 #endif 692 #ifndef PPI_CHG0_CH0_Msk 693 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 694 #endif 695 #ifndef PPI_CHG0_CH0_Excluded 696 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 697 #endif 698 #ifndef PPI_CHG0_CH0_Included 699 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 700 #endif 701 702 #ifndef PPI_CHG1_CH15_Pos 703 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 704 #endif 705 #ifndef PPI_CHG1_CH15_Msk 706 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 707 #endif 708 #ifndef PPI_CHG1_CH15_Excluded 709 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 710 #endif 711 #ifndef PPI_CHG1_CH15_Included 712 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 713 #endif 714 715 #ifndef PPI_CHG1_CH14_Pos 716 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 717 #endif 718 #ifndef PPI_CHG1_CH14_Msk 719 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 720 #endif 721 #ifndef PPI_CHG1_CH14_Excluded 722 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 723 #endif 724 #ifndef PPI_CHG1_CH14_Included 725 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 726 #endif 727 728 #ifndef PPI_CHG1_CH13_Pos 729 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 730 #endif 731 #ifndef PPI_CHG1_CH13_Msk 732 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 733 #endif 734 #ifndef PPI_CHG1_CH13_Excluded 735 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 736 #endif 737 #ifndef PPI_CHG1_CH13_Included 738 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 739 #endif 740 741 #ifndef PPI_CHG1_CH12_Pos 742 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 743 #endif 744 #ifndef PPI_CHG1_CH12_Msk 745 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 746 #endif 747 #ifndef PPI_CHG1_CH12_Excluded 748 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 749 #endif 750 #ifndef PPI_CHG1_CH12_Included 751 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 752 #endif 753 754 #ifndef PPI_CHG1_CH11_Pos 755 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 756 #endif 757 #ifndef PPI_CHG1_CH11_Msk 758 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 759 #endif 760 #ifndef PPI_CHG1_CH11_Excluded 761 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 762 #endif 763 #ifndef PPI_CHG1_CH11_Included 764 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 765 #endif 766 767 #ifndef PPI_CHG1_CH10_Pos 768 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 769 #endif 770 #ifndef PPI_CHG1_CH10_Msk 771 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 772 #endif 773 #ifndef PPI_CHG1_CH10_Excluded 774 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 775 #endif 776 #ifndef PPI_CHG1_CH10_Included 777 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 778 #endif 779 780 #ifndef PPI_CHG1_CH9_Pos 781 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 782 #endif 783 #ifndef PPI_CHG1_CH9_Msk 784 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 785 #endif 786 #ifndef PPI_CHG1_CH9_Excluded 787 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 788 #endif 789 #ifndef PPI_CHG1_CH9_Included 790 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 791 #endif 792 793 #ifndef PPI_CHG1_CH8_Pos 794 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 795 #endif 796 #ifndef PPI_CHG1_CH8_Msk 797 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 798 #endif 799 #ifndef PPI_CHG1_CH8_Excluded 800 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 801 #endif 802 #ifndef PPI_CHG1_CH8_Included 803 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 804 #endif 805 806 #ifndef PPI_CHG1_CH7_Pos 807 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 808 #endif 809 #ifndef PPI_CHG1_CH7_Msk 810 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 811 #endif 812 #ifndef PPI_CHG1_CH7_Excluded 813 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 814 #endif 815 #ifndef PPI_CHG1_CH7_Included 816 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 817 #endif 818 819 #ifndef PPI_CHG1_CH6_Pos 820 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 821 #endif 822 #ifndef PPI_CHG1_CH6_Msk 823 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 824 #endif 825 #ifndef PPI_CHG1_CH6_Excluded 826 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 827 #endif 828 #ifndef PPI_CHG1_CH6_Included 829 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 830 #endif 831 832 #ifndef PPI_CHG1_CH5_Pos 833 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 834 #endif 835 #ifndef PPI_CHG1_CH5_Msk 836 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 837 #endif 838 #ifndef PPI_CHG1_CH5_Excluded 839 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 840 #endif 841 #ifndef PPI_CHG1_CH5_Included 842 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 843 #endif 844 845 #ifndef PPI_CHG1_CH4_Pos 846 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 847 #endif 848 #ifndef PPI_CHG1_CH4_Msk 849 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 850 #endif 851 #ifndef PPI_CHG1_CH4_Excluded 852 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 853 #endif 854 #ifndef PPI_CHG1_CH4_Included 855 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 856 #endif 857 858 #ifndef PPI_CHG1_CH3_Pos 859 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 860 #endif 861 #ifndef PPI_CHG1_CH3_Msk 862 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 863 #endif 864 #ifndef PPI_CHG1_CH3_Excluded 865 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 866 #endif 867 #ifndef PPI_CHG1_CH3_Included 868 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 869 #endif 870 871 #ifndef PPI_CHG1_CH2_Pos 872 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 873 #endif 874 #ifndef PPI_CHG1_CH2_Msk 875 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 876 #endif 877 #ifndef PPI_CHG1_CH2_Excluded 878 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 879 #endif 880 #ifndef PPI_CHG1_CH2_Included 881 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 882 #endif 883 884 #ifndef PPI_CHG1_CH1_Pos 885 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 886 #endif 887 #ifndef PPI_CHG1_CH1_Msk 888 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 889 #endif 890 #ifndef PPI_CHG1_CH1_Excluded 891 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 892 #endif 893 #ifndef PPI_CHG1_CH1_Included 894 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 895 #endif 896 897 #ifndef PPI_CHG1_CH0_Pos 898 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 899 #endif 900 #ifndef PPI_CHG1_CH0_Msk 901 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 902 #endif 903 #ifndef PPI_CHG1_CH0_Excluded 904 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 905 #endif 906 #ifndef PPI_CHG1_CH0_Included 907 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 908 #endif 909 910 #ifndef PPI_CHG2_CH15_Pos 911 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 912 #endif 913 #ifndef PPI_CHG2_CH15_Msk 914 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 915 #endif 916 #ifndef PPI_CHG2_CH15_Excluded 917 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 918 #endif 919 #ifndef PPI_CHG2_CH15_Included 920 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 921 #endif 922 923 #ifndef PPI_CHG2_CH14_Pos 924 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 925 #endif 926 #ifndef PPI_CHG2_CH14_Msk 927 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 928 #endif 929 #ifndef PPI_CHG2_CH14_Excluded 930 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 931 #endif 932 #ifndef PPI_CHG2_CH14_Included 933 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 934 #endif 935 936 #ifndef PPI_CHG2_CH13_Pos 937 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 938 #endif 939 #ifndef PPI_CHG2_CH13_Msk 940 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 941 #endif 942 #ifndef PPI_CHG2_CH13_Excluded 943 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 944 #endif 945 #ifndef PPI_CHG2_CH13_Included 946 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 947 #endif 948 949 #ifndef PPI_CHG2_CH12_Pos 950 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 951 #endif 952 #ifndef PPI_CHG2_CH12_Msk 953 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 954 #endif 955 #ifndef PPI_CHG2_CH12_Excluded 956 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 957 #endif 958 #ifndef PPI_CHG2_CH12_Included 959 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 960 #endif 961 962 #ifndef PPI_CHG2_CH11_Pos 963 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 964 #endif 965 #ifndef PPI_CHG2_CH11_Msk 966 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 967 #endif 968 #ifndef PPI_CHG2_CH11_Excluded 969 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 970 #endif 971 #ifndef PPI_CHG2_CH11_Included 972 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 973 #endif 974 975 #ifndef PPI_CHG2_CH10_Pos 976 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 977 #endif 978 #ifndef PPI_CHG2_CH10_Msk 979 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 980 #endif 981 #ifndef PPI_CHG2_CH10_Excluded 982 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 983 #endif 984 #ifndef PPI_CHG2_CH10_Included 985 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 986 #endif 987 988 #ifndef PPI_CHG2_CH9_Pos 989 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 990 #endif 991 #ifndef PPI_CHG2_CH9_Msk 992 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 993 #endif 994 #ifndef PPI_CHG2_CH9_Excluded 995 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 996 #endif 997 #ifndef PPI_CHG2_CH9_Included 998 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 999 #endif 1000 1001 #ifndef PPI_CHG2_CH8_Pos 1002 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 1003 #endif 1004 #ifndef PPI_CHG2_CH8_Msk 1005 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 1006 #endif 1007 #ifndef PPI_CHG2_CH8_Excluded 1008 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 1009 #endif 1010 #ifndef PPI_CHG2_CH8_Included 1011 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 1012 #endif 1013 1014 #ifndef PPI_CHG2_CH7_Pos 1015 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 1016 #endif 1017 #ifndef PPI_CHG2_CH7_Msk 1018 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 1019 #endif 1020 #ifndef PPI_CHG2_CH7_Excluded 1021 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 1022 #endif 1023 #ifndef PPI_CHG2_CH7_Included 1024 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 1025 #endif 1026 1027 #ifndef PPI_CHG2_CH6_Pos 1028 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 1029 #endif 1030 #ifndef PPI_CHG2_CH6_Msk 1031 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 1032 #endif 1033 #ifndef PPI_CHG2_CH6_Excluded 1034 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 1035 #endif 1036 #ifndef PPI_CHG2_CH6_Included 1037 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 1038 #endif 1039 1040 #ifndef PPI_CHG2_CH5_Pos 1041 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 1042 #endif 1043 #ifndef PPI_CHG2_CH5_Msk 1044 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 1045 #endif 1046 #ifndef PPI_CHG2_CH5_Excluded 1047 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 1048 #endif 1049 #ifndef PPI_CHG2_CH5_Included 1050 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 1051 #endif 1052 1053 #ifndef PPI_CHG2_CH4_Pos 1054 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 1055 #endif 1056 #ifndef PPI_CHG2_CH4_Msk 1057 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 1058 #endif 1059 #ifndef PPI_CHG2_CH4_Excluded 1060 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 1061 #endif 1062 #ifndef PPI_CHG2_CH4_Included 1063 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 1064 #endif 1065 1066 #ifndef PPI_CHG2_CH3_Pos 1067 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 1068 #endif 1069 #ifndef PPI_CHG2_CH3_Msk 1070 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 1071 #endif 1072 #ifndef PPI_CHG2_CH3_Excluded 1073 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 1074 #endif 1075 #ifndef PPI_CHG2_CH3_Included 1076 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 1077 #endif 1078 1079 #ifndef PPI_CHG2_CH2_Pos 1080 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 1081 #endif 1082 #ifndef PPI_CHG2_CH2_Msk 1083 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 1084 #endif 1085 #ifndef PPI_CHG2_CH2_Excluded 1086 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 1087 #endif 1088 #ifndef PPI_CHG2_CH2_Included 1089 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 1090 #endif 1091 1092 #ifndef PPI_CHG2_CH1_Pos 1093 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 1094 #endif 1095 #ifndef PPI_CHG2_CH1_Msk 1096 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 1097 #endif 1098 #ifndef PPI_CHG2_CH1_Excluded 1099 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 1100 #endif 1101 #ifndef PPI_CHG2_CH1_Included 1102 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 1103 #endif 1104 1105 #ifndef PPI_CHG2_CH0_Pos 1106 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 1107 #endif 1108 #ifndef PPI_CHG2_CH0_Msk 1109 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 1110 #endif 1111 #ifndef PPI_CHG2_CH0_Excluded 1112 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 1113 #endif 1114 #ifndef PPI_CHG2_CH0_Included 1115 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 1116 #endif 1117 1118 #ifndef PPI_CHG3_CH15_Pos 1119 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 1120 #endif 1121 #ifndef PPI_CHG3_CH15_Msk 1122 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 1123 #endif 1124 #ifndef PPI_CHG3_CH15_Excluded 1125 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 1126 #endif 1127 #ifndef PPI_CHG3_CH15_Included 1128 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 1129 #endif 1130 1131 #ifndef PPI_CHG3_CH14_Pos 1132 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 1133 #endif 1134 #ifndef PPI_CHG3_CH14_Msk 1135 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 1136 #endif 1137 #ifndef PPI_CHG3_CH14_Excluded 1138 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 1139 #endif 1140 #ifndef PPI_CHG3_CH14_Included 1141 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 1142 #endif 1143 1144 #ifndef PPI_CHG3_CH13_Pos 1145 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 1146 #endif 1147 #ifndef PPI_CHG3_CH13_Msk 1148 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 1149 #endif 1150 #ifndef PPI_CHG3_CH13_Excluded 1151 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 1152 #endif 1153 #ifndef PPI_CHG3_CH13_Included 1154 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 1155 #endif 1156 1157 #ifndef PPI_CHG3_CH12_Pos 1158 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 1159 #endif 1160 #ifndef PPI_CHG3_CH12_Msk 1161 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 1162 #endif 1163 #ifndef PPI_CHG3_CH12_Excluded 1164 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 1165 #endif 1166 #ifndef PPI_CHG3_CH12_Included 1167 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 1168 #endif 1169 1170 #ifndef PPI_CHG3_CH11_Pos 1171 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 1172 #endif 1173 #ifndef PPI_CHG3_CH11_Msk 1174 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 1175 #endif 1176 #ifndef PPI_CHG3_CH11_Excluded 1177 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 1178 #endif 1179 #ifndef PPI_CHG3_CH11_Included 1180 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 1181 #endif 1182 1183 #ifndef PPI_CHG3_CH10_Pos 1184 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 1185 #endif 1186 #ifndef PPI_CHG3_CH10_Msk 1187 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 1188 #endif 1189 #ifndef PPI_CHG3_CH10_Excluded 1190 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 1191 #endif 1192 #ifndef PPI_CHG3_CH10_Included 1193 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 1194 #endif 1195 1196 #ifndef PPI_CHG3_CH9_Pos 1197 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 1198 #endif 1199 #ifndef PPI_CHG3_CH9_Msk 1200 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 1201 #endif 1202 #ifndef PPI_CHG3_CH9_Excluded 1203 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 1204 #endif 1205 #ifndef PPI_CHG3_CH9_Included 1206 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 1207 #endif 1208 1209 #ifndef PPI_CHG3_CH8_Pos 1210 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 1211 #endif 1212 #ifndef PPI_CHG3_CH8_Msk 1213 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 1214 #endif 1215 #ifndef PPI_CHG3_CH8_Excluded 1216 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 1217 #endif 1218 #ifndef PPI_CHG3_CH8_Included 1219 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 1220 #endif 1221 1222 #ifndef PPI_CHG3_CH7_Pos 1223 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 1224 #endif 1225 #ifndef PPI_CHG3_CH7_Msk 1226 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 1227 #endif 1228 #ifndef PPI_CHG3_CH7_Excluded 1229 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 1230 #endif 1231 #ifndef PPI_CHG3_CH7_Included 1232 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 1233 #endif 1234 1235 #ifndef PPI_CHG3_CH6_Pos 1236 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 1237 #endif 1238 #ifndef PPI_CHG3_CH6_Msk 1239 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 1240 #endif 1241 #ifndef PPI_CHG3_CH6_Excluded 1242 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 1243 #endif 1244 #ifndef PPI_CHG3_CH6_Included 1245 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 1246 #endif 1247 1248 #ifndef PPI_CHG3_CH5_Pos 1249 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 1250 #endif 1251 #ifndef PPI_CHG3_CH5_Msk 1252 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 1253 #endif 1254 #ifndef PPI_CHG3_CH5_Excluded 1255 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 1256 #endif 1257 #ifndef PPI_CHG3_CH5_Included 1258 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 1259 #endif 1260 1261 #ifndef PPI_CHG3_CH4_Pos 1262 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 1263 #endif 1264 #ifndef PPI_CHG3_CH4_Msk 1265 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 1266 #endif 1267 #ifndef PPI_CHG3_CH4_Excluded 1268 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 1269 #endif 1270 #ifndef PPI_CHG3_CH4_Included 1271 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 1272 #endif 1273 1274 #ifndef PPI_CHG3_CH3_Pos 1275 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 1276 #endif 1277 #ifndef PPI_CHG3_CH3_Msk 1278 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 1279 #endif 1280 #ifndef PPI_CHG3_CH3_Excluded 1281 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 1282 #endif 1283 #ifndef PPI_CHG3_CH3_Included 1284 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 1285 #endif 1286 1287 #ifndef PPI_CHG3_CH2_Pos 1288 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 1289 #endif 1290 #ifndef PPI_CHG3_CH2_Msk 1291 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 1292 #endif 1293 #ifndef PPI_CHG3_CH2_Excluded 1294 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 1295 #endif 1296 #ifndef PPI_CHG3_CH2_Included 1297 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 1298 #endif 1299 1300 #ifndef PPI_CHG3_CH1_Pos 1301 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 1302 #endif 1303 #ifndef PPI_CHG3_CH1_Msk 1304 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 1305 #endif 1306 #ifndef PPI_CHG3_CH1_Excluded 1307 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 1308 #endif 1309 #ifndef PPI_CHG3_CH1_Included 1310 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 1311 #endif 1312 1313 #ifndef PPI_CHG3_CH0_Pos 1314 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 1315 #endif 1316 #ifndef PPI_CHG3_CH0_Msk 1317 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 1318 #endif 1319 #ifndef PPI_CHG3_CH0_Excluded 1320 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 1321 #endif 1322 #ifndef PPI_CHG3_CH0_Included 1323 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 1324 #endif 1325 1326 1327 1328 1329 1330 /*lint --flb "Leave library region" */ 1331 1332 #endif /* NRF51_TO_NRF52840_H */ 1333 1334