1 /* 2 * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52805.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 14. August 2020 34 * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 35 * from File 'nrf52805.svd', 36 * last modified on Friday, 14.08.2020 13:02:06 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52805 47 * @{ 48 */ 49 50 51 #ifndef NRF52805_H 52 #define NRF52805_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* ========================================== nrf52805 Specific Interrupt Numbers ========================================== */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87 TWIM0_TWIS0_TWI0_IRQn = 3, /*!< 3 TWIM0_TWIS0_TWI0 */ 88 SPIM0_SPIS0_SPI0_IRQn = 4, /*!< 4 SPIM0_SPIS0_SPI0 */ 89 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 90 SAADC_IRQn = 7, /*!< 7 SAADC */ 91 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 92 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 93 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 94 RTC0_IRQn = 11, /*!< 11 RTC0 */ 95 TEMP_IRQn = 12, /*!< 12 TEMP */ 96 RNG_IRQn = 13, /*!< 13 RNG */ 97 ECB_IRQn = 14, /*!< 14 ECB */ 98 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 99 WDT_IRQn = 16, /*!< 16 WDT */ 100 RTC1_IRQn = 17, /*!< 17 RTC1 */ 101 QDEC_IRQn = 18, /*!< 18 QDEC */ 102 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 103 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 104 SWI2_IRQn = 22, /*!< 22 SWI2 */ 105 SWI3_IRQn = 23, /*!< 23 SWI3 */ 106 SWI4_IRQn = 24, /*!< 24 SWI4 */ 107 SWI5_IRQn = 25 /*!< 25 SWI5 */ 108 } IRQn_Type; 109 110 111 112 /* =========================================================================================================================== */ 113 /* ================ Processor and Core Peripheral Section ================ */ 114 /* =========================================================================================================================== */ 115 116 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 117 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 118 #define __DSP_PRESENT 1 /*!< DSP present or not */ 119 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 120 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 122 #define __MPU_PRESENT 1 /*!< MPU present */ 123 #define __FPU_PRESENT 0 /*!< FPU present */ 124 125 126 /** @} */ /* End of group Configuration_of_CMSIS */ 127 128 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 129 #include "system_nrf52805.h" /*!< nrf52805 System */ 130 131 #ifndef __IM /*!< Fallback for older CMSIS versions */ 132 #define __IM __I 133 #endif 134 #ifndef __OM /*!< Fallback for older CMSIS versions */ 135 #define __OM __O 136 #endif 137 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 138 #define __IOM __IO 139 #endif 140 141 142 /* ======================================== Start of section using anonymous unions ======================================== */ 143 #if defined (__CC_ARM) 144 #pragma push 145 #pragma anon_unions 146 #elif defined (__ICCARM__) 147 #pragma language=extended 148 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 149 #pragma clang diagnostic push 150 #pragma clang diagnostic ignored "-Wc11-extensions" 151 #pragma clang diagnostic ignored "-Wreserved-id-macro" 152 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 153 #pragma clang diagnostic ignored "-Wnested-anon-types" 154 #elif defined (__GNUC__) 155 /* anonymous unions are enabled by default */ 156 #elif defined (__TMS470__) 157 /* anonymous unions are enabled by default */ 158 #elif defined (__TASKING__) 159 #pragma warning 586 160 #elif defined (__CSMC__) 161 /* anonymous unions are enabled by default */ 162 #else 163 #warning Not supported compiler type 164 #endif 165 166 167 /* =========================================================================================================================== */ 168 /* ================ Device Specific Cluster Section ================ */ 169 /* =========================================================================================================================== */ 170 171 172 /** @addtogroup Device_Peripheral_clusters 173 * @{ 174 */ 175 176 177 /** 178 * @brief FICR_INFO [INFO] (Device info) 179 */ 180 typedef struct { 181 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 182 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part variant, hardware version and production 183 configuration */ 184 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 185 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 186 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 187 } FICR_INFO_Type; /*!< Size = 20 (0x14) */ 188 189 190 /** 191 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 192 */ 193 typedef struct { 194 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 195 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 196 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 197 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 198 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 199 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 200 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 201 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 202 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 203 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 204 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 205 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 206 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 207 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 208 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 209 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 210 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 211 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 212 213 214 /** 215 * @brief POWER_RAM [RAM] (Unspecified) 216 */ 217 typedef struct { 218 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register. 219 The RAM size will vary depending on product 220 variant, and the RAMn register will only 221 be present if the corresponding RAM AHB 222 slave is present on the device. */ 223 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ 224 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear 225 register */ 226 __IM uint32_t RESERVED; 227 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 228 229 230 /** 231 * @brief UART_PSEL [PSEL] (Unspecified) 232 */ 233 typedef struct { 234 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 235 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 236 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 237 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 238 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 239 240 241 /** 242 * @brief UARTE_PSEL [PSEL] (Unspecified) 243 */ 244 typedef struct { 245 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 246 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 247 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 248 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 249 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 250 251 252 /** 253 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 254 */ 255 typedef struct { 256 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 257 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 258 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 259 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 260 261 262 /** 263 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 264 */ 265 typedef struct { 266 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 267 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 268 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 269 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 270 271 272 /** 273 * @brief TWI_PSEL [PSEL] (Unspecified) 274 */ 275 typedef struct { 276 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 277 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 278 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 279 280 281 /** 282 * @brief TWIM_PSEL [PSEL] (Unspecified) 283 */ 284 typedef struct { 285 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 286 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 287 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 288 289 290 /** 291 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 292 */ 293 typedef struct { 294 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 295 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 296 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 297 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 298 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 299 300 301 /** 302 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 303 */ 304 typedef struct { 305 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 306 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 307 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 308 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 309 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 310 311 312 /** 313 * @brief TWIS_PSEL [PSEL] (Unspecified) 314 */ 315 typedef struct { 316 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 317 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 318 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 319 320 321 /** 322 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 323 */ 324 typedef struct { 325 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 326 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 327 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 328 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 329 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 330 331 332 /** 333 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 334 */ 335 typedef struct { 336 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 337 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 338 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 339 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 340 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 341 342 343 /** 344 * @brief SPI_PSEL [PSEL] (Unspecified) 345 */ 346 typedef struct { 347 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 348 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 349 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 350 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 351 352 353 /** 354 * @brief SPIM_PSEL [PSEL] (Unspecified) 355 */ 356 typedef struct { 357 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 358 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 359 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 360 } SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ 361 362 363 /** 364 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 365 */ 366 typedef struct { 367 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 368 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 369 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 370 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 371 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 372 373 374 /** 375 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 376 */ 377 typedef struct { 378 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 379 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 380 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 381 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 382 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 383 384 385 /** 386 * @brief SPIS_PSEL [PSEL] (Unspecified) 387 */ 388 typedef struct { 389 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 390 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 391 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 392 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 393 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 394 395 396 /** 397 * @brief SPIS_RXD [RXD] (Unspecified) 398 */ 399 typedef struct { 400 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 401 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 402 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 403 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 404 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 405 406 407 /** 408 * @brief SPIS_TXD [TXD] (Unspecified) 409 */ 410 typedef struct { 411 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 412 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 413 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 414 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 415 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 416 417 418 /** 419 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 420 */ 421 typedef struct { 422 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 423 above CH[n].LIMIT.HIGH */ 424 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 425 below CH[n].LIMIT.LOW */ 426 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 427 428 429 /** 430 * @brief SAADC_CH [CH] (Unspecified) 431 */ 432 typedef struct { 433 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 434 for CH[n] */ 435 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 436 for CH[n] */ 437 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 438 CH[n] */ 439 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 440 monitoring a channel */ 441 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 442 443 444 /** 445 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 446 */ 447 typedef struct { 448 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 449 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 450 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 451 START */ 452 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 453 454 455 /** 456 * @brief QDEC_PSEL [PSEL] (Unspecified) 457 */ 458 typedef struct { 459 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 460 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 461 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 462 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 463 464 465 /** 466 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 467 */ 468 typedef struct { 469 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 470 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 471 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 472 473 474 /** 475 * @brief PPI_CH [CH] (PPI Channel) 476 */ 477 typedef struct { 478 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ 479 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ 480 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 481 482 483 /** 484 * @brief PPI_FORK [FORK] (Fork) 485 */ 486 typedef struct { 487 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ 488 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 489 490 491 /** @} */ /* End of group Device_Peripheral_clusters */ 492 493 494 /* =========================================================================================================================== */ 495 /* ================ Device Specific Peripheral Section ================ */ 496 /* =========================================================================================================================== */ 497 498 499 /** @addtogroup Device_Peripheral_peripherals 500 * @{ 501 */ 502 503 504 505 /* =========================================================================================================================== */ 506 /* ================ FICR ================ */ 507 /* =========================================================================================================================== */ 508 509 510 /** 511 * @brief Factory information configuration registers (FICR) 512 */ 513 514 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 515 __IM uint32_t RESERVED[4]; 516 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 517 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 518 __IM uint32_t RESERVED1[18]; 519 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ 520 __IM uint32_t RESERVED2[6]; 521 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word 522 n */ 523 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity root, word n */ 524 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 525 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ 526 __IM uint32_t RESERVED3[21]; 527 __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 528 __IM uint32_t RESERVED4[188]; 529 __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 530 coefficients */ 531 } NRF_FICR_Type; /*!< Size = 1096 (0x448) */ 532 533 534 535 /* =========================================================================================================================== */ 536 /* ================ UICR ================ */ 537 /* =========================================================================================================================== */ 538 539 540 /** 541 * @brief User information configuration registers (UICR) 542 */ 543 544 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 545 __IM uint32_t RESERVED[5]; 546 __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware 547 design */ 548 __IM uint32_t RESERVED1[2]; 549 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware 550 design */ 551 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ 552 __IM uint32_t RESERVED2[64]; 553 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET 554 function (see POWER chapter for details) */ 555 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 556 } NRF_UICR_Type; /*!< Size = 524 (0x20c) */ 557 558 559 560 /* =========================================================================================================================== */ 561 /* ================ BPROT ================ */ 562 /* =========================================================================================================================== */ 563 564 565 /** 566 * @brief Block Protect (BPROT) 567 */ 568 569 typedef struct { /*!< (@ 0x40000000) BPROT Structure */ 570 __IM uint32_t RESERVED[384]; 571 __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ 572 __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ 573 __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug mode */ 574 } NRF_BPROT_Type; /*!< Size = 1548 (0x60c) */ 575 576 577 578 /* =========================================================================================================================== */ 579 /* ================ CLOCK ================ */ 580 /* =========================================================================================================================== */ 581 582 583 /** 584 * @brief Clock control (CLOCK) 585 */ 586 587 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 588 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ 589 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ 590 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ 591 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 592 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 593 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 594 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 595 __IM uint32_t RESERVED[57]; 596 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ 597 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 598 __IM uint32_t RESERVED1; 599 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ 600 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 601 __IM uint32_t RESERVED2[124]; 602 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 603 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 604 __IM uint32_t RESERVED3[63]; 605 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 606 triggered */ 607 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 608 __IM uint32_t RESERVED4; 609 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 610 triggered */ 611 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 612 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 613 task was triggered */ 614 __IM uint32_t RESERVED5[62]; 615 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 616 __IM uint32_t RESERVED6[7]; 617 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 618 } NRF_CLOCK_Type; /*!< Size = 1340 (0x53c) */ 619 620 621 622 /* =========================================================================================================================== */ 623 /* ================ POWER ================ */ 624 /* =========================================================================================================================== */ 625 626 627 /** 628 * @brief Power control (POWER) 629 */ 630 631 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 632 __IM uint32_t RESERVED[30]; 633 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 634 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ 635 __IM uint32_t RESERVED1[34]; 636 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 637 __IM uint32_t RESERVED2[2]; 638 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 639 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 640 __IM uint32_t RESERVED3[122]; 641 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 642 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 643 __IM uint32_t RESERVED4[61]; 644 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 645 __IM uint32_t RESERVED5[63]; 646 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 647 __IM uint32_t RESERVED6[3]; 648 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ 649 __IM uint32_t RESERVED7[2]; 650 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 651 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 652 __IM uint32_t RESERVED8[21]; 653 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ 654 __IM uint32_t RESERVED9[225]; 655 __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ 656 } NRF_POWER_Type; /*!< Size = 2432 (0x980) */ 657 658 659 660 /* =========================================================================================================================== */ 661 /* ================ P0 ================ */ 662 /* =========================================================================================================================== */ 663 664 665 /** 666 * @brief GPIO Port (P0) 667 */ 668 669 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 670 __IM uint32_t RESERVED[321]; 671 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 672 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 673 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 674 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 675 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 676 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 677 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 678 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 679 have met the criteria set in the PIN_CNF[n].SENSE 680 registers */ 681 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior 682 and LDETECT mode */ 683 __IM uint32_t RESERVED1[118]; 684 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO 685 pins */ 686 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 687 688 689 690 /* =========================================================================================================================== */ 691 /* ================ RADIO ================ */ 692 /* =========================================================================================================================== */ 693 694 695 /** 696 * @brief 2.4 GHz radio (RADIO) 697 */ 698 699 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 700 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 701 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 702 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 703 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 704 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 705 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 706 the receive signal strength */ 707 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 708 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 709 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 710 __IM uint32_t RESERVED[55]; 711 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 712 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 713 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 714 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 715 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 716 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 717 packet */ 718 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 719 received packet */ 720 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 721 __IM uint32_t RESERVED1[2]; 722 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 723 __IM uint32_t RESERVED2; 724 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 725 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 726 __IM uint32_t RESERVED3[7]; 727 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 728 TX path */ 729 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 730 RX path */ 731 __IM uint32_t RESERVED4[4]; 732 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received 733 from air */ 734 __IM uint32_t RESERVED5[36]; 735 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 736 __IM uint32_t RESERVED6[64]; 737 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 738 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 739 __IM uint32_t RESERVED7[61]; 740 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 741 __IM uint32_t RESERVED8; 742 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 743 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 744 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 745 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 746 __IM uint32_t RESERVED9[59]; 747 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 748 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 749 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 750 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 751 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 752 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 753 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 754 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 755 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 756 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 757 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 758 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 759 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 760 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 761 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 762 __IM uint32_t RESERVED10; 763 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 764 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 765 __IM uint32_t RESERVED11; 766 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 767 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 768 __IM uint32_t RESERVED12[2]; 769 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 770 __IM uint32_t RESERVED13[39]; 771 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment 772 n */ 773 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix 774 n */ 775 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 776 __IM uint32_t RESERVED14[3]; 777 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 778 __IM uint32_t RESERVED15[618]; 779 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 780 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 781 782 783 784 /* =========================================================================================================================== */ 785 /* ================ UART0 ================ */ 786 /* =========================================================================================================================== */ 787 788 789 /** 790 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 791 */ 792 793 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 794 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 795 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 796 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 797 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 798 __IM uint32_t RESERVED[3]; 799 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 800 __IM uint32_t RESERVED1[56]; 801 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 802 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 803 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 804 __IM uint32_t RESERVED2[4]; 805 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 806 __IM uint32_t RESERVED3; 807 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 808 __IM uint32_t RESERVED4[7]; 809 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 810 __IM uint32_t RESERVED5[46]; 811 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 812 __IM uint32_t RESERVED6[64]; 813 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 814 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 815 __IM uint32_t RESERVED7[93]; 816 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 817 __IM uint32_t RESERVED8[31]; 818 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 819 __IM uint32_t RESERVED9; 820 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 821 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 822 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 823 __IM uint32_t RESERVED10; 824 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 825 selected. */ 826 __IM uint32_t RESERVED11[17]; 827 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 828 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 829 830 831 832 /* =========================================================================================================================== */ 833 /* ================ UARTE0 ================ */ 834 /* =========================================================================================================================== */ 835 836 837 /** 838 * @brief UART with EasyDMA (UARTE0) 839 */ 840 841 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 842 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 843 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 844 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 845 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 846 __IM uint32_t RESERVED[7]; 847 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 848 __IM uint32_t RESERVED1[52]; 849 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 850 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 851 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 852 transferred to Data RAM) */ 853 __IM uint32_t RESERVED2; 854 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 855 __IM uint32_t RESERVED3[2]; 856 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 857 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 858 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 859 __IM uint32_t RESERVED4[7]; 860 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 861 __IM uint32_t RESERVED5; 862 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 863 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 864 __IM uint32_t RESERVED6; 865 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 866 __IM uint32_t RESERVED7[41]; 867 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 868 __IM uint32_t RESERVED8[63]; 869 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 870 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 871 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 872 __IM uint32_t RESERVED9[93]; 873 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one 874 to clear. */ 875 __IM uint32_t RESERVED10[31]; 876 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 877 __IM uint32_t RESERVED11; 878 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 879 __IM uint32_t RESERVED12[3]; 880 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 881 selected. */ 882 __IM uint32_t RESERVED13[3]; 883 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 884 __IM uint32_t RESERVED14; 885 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 886 __IM uint32_t RESERVED15[7]; 887 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 888 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 889 890 891 892 /* =========================================================================================================================== */ 893 /* ================ TWI0 ================ */ 894 /* =========================================================================================================================== */ 895 896 897 /** 898 * @brief I2C compatible Two-Wire Interface (TWI0) 899 */ 900 901 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 902 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 903 __IM uint32_t RESERVED; 904 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 905 __IM uint32_t RESERVED1[2]; 906 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 907 __IM uint32_t RESERVED2; 908 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 909 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 910 __IM uint32_t RESERVED3[56]; 911 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 912 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 913 __IM uint32_t RESERVED4[4]; 914 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 915 __IM uint32_t RESERVED5; 916 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 917 __IM uint32_t RESERVED6[4]; 918 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 919 that is sent or received */ 920 __IM uint32_t RESERVED7[3]; 921 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 922 __IM uint32_t RESERVED8[45]; 923 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 924 __IM uint32_t RESERVED9[64]; 925 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 926 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 927 __IM uint32_t RESERVED10[110]; 928 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 929 __IM uint32_t RESERVED11[14]; 930 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 931 __IM uint32_t RESERVED12; 932 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 933 __IM uint32_t RESERVED13[2]; 934 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 935 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 936 __IM uint32_t RESERVED14; 937 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 938 source selected. */ 939 __IM uint32_t RESERVED15[24]; 940 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 941 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 942 943 944 945 /* =========================================================================================================================== */ 946 /* ================ TWIM0 ================ */ 947 /* =========================================================================================================================== */ 948 949 950 /** 951 * @brief I2C compatible Two-Wire Master Interface with EasyDMA (TWIM0) 952 */ 953 954 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 955 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 956 __IM uint32_t RESERVED; 957 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 958 __IM uint32_t RESERVED1[2]; 959 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 960 TWI master is not suspended. */ 961 __IM uint32_t RESERVED2; 962 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 963 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 964 __IM uint32_t RESERVED3[56]; 965 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 966 __IM uint32_t RESERVED4[7]; 967 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 968 __IM uint32_t RESERVED5[8]; 969 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 970 now suspended. */ 971 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 972 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 973 __IM uint32_t RESERVED6[2]; 974 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 975 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 976 byte */ 977 __IM uint32_t RESERVED7[39]; 978 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 979 __IM uint32_t RESERVED8[63]; 980 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 981 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 982 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 983 __IM uint32_t RESERVED9[110]; 984 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 985 __IM uint32_t RESERVED10[14]; 986 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 987 __IM uint32_t RESERVED11; 988 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 989 __IM uint32_t RESERVED12[5]; 990 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 991 source selected. */ 992 __IM uint32_t RESERVED13[3]; 993 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 994 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 995 __IM uint32_t RESERVED14[13]; 996 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 997 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 998 999 1000 1001 /* =========================================================================================================================== */ 1002 /* ================ TWIS0 ================ */ 1003 /* =========================================================================================================================== */ 1004 1005 1006 /** 1007 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA (TWIS0) 1008 */ 1009 1010 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1011 __IM uint32_t RESERVED[5]; 1012 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1013 __IM uint32_t RESERVED1; 1014 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1015 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1016 __IM uint32_t RESERVED2[3]; 1017 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1018 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1019 __IM uint32_t RESERVED3[51]; 1020 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1021 __IM uint32_t RESERVED4[7]; 1022 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1023 __IM uint32_t RESERVED5[9]; 1024 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1025 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1026 __IM uint32_t RESERVED6[4]; 1027 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1028 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1029 __IM uint32_t RESERVED7[37]; 1030 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1031 __IM uint32_t RESERVED8[63]; 1032 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1033 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1034 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1035 __IM uint32_t RESERVED9[113]; 1036 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1037 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1038 a match */ 1039 __IM uint32_t RESERVED10[10]; 1040 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1041 __IM uint32_t RESERVED11; 1042 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1043 __IM uint32_t RESERVED12[9]; 1044 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1045 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1046 __IM uint32_t RESERVED13[13]; 1047 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1048 __IM uint32_t RESERVED14; 1049 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1050 mechanism */ 1051 __IM uint32_t RESERVED15[10]; 1052 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1053 of an over-read of the transmit buffer. */ 1054 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1055 1056 1057 1058 /* =========================================================================================================================== */ 1059 /* ================ SPI0 ================ */ 1060 /* =========================================================================================================================== */ 1061 1062 1063 /** 1064 * @brief Serial Peripheral Interface (SPI0) 1065 */ 1066 1067 typedef struct { /*!< (@ 0x40004000) SPI0 Structure */ 1068 __IM uint32_t RESERVED[66]; 1069 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1070 __IM uint32_t RESERVED1[126]; 1071 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1072 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1073 __IM uint32_t RESERVED2[125]; 1074 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1075 __IM uint32_t RESERVED3; 1076 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1077 __IM uint32_t RESERVED4; 1078 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1079 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1080 __IM uint32_t RESERVED5; 1081 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1082 source selected. */ 1083 __IM uint32_t RESERVED6[11]; 1084 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1085 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1086 1087 1088 1089 /* =========================================================================================================================== */ 1090 /* ================ SPIM0 ================ */ 1091 /* =========================================================================================================================== */ 1092 1093 1094 /** 1095 * @brief Serial Peripheral Interface Master with EasyDMA (SPIM0) 1096 */ 1097 1098 typedef struct { /*!< (@ 0x40004000) SPIM0 Structure */ 1099 __IM uint32_t RESERVED[4]; 1100 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1101 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1102 __IM uint32_t RESERVED1; 1103 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1104 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1105 __IM uint32_t RESERVED2[56]; 1106 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1107 __IM uint32_t RESERVED3[2]; 1108 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1109 __IM uint32_t RESERVED4; 1110 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1111 __IM uint32_t RESERVED5; 1112 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1113 __IM uint32_t RESERVED6[10]; 1114 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1115 __IM uint32_t RESERVED7[44]; 1116 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1117 __IM uint32_t RESERVED8[64]; 1118 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1119 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1120 __IM uint32_t RESERVED9[125]; 1121 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1122 __IM uint32_t RESERVED10; 1123 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1124 __IM uint32_t RESERVED11[4]; 1125 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1126 source selected. */ 1127 __IM uint32_t RESERVED12[3]; 1128 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1129 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1130 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1131 __IM uint32_t RESERVED13[26]; 1132 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in 1133 case and over-read of the TXD buffer. */ 1134 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1135 1136 1137 1138 /* =========================================================================================================================== */ 1139 /* ================ SPIS0 ================ */ 1140 /* =========================================================================================================================== */ 1141 1142 1143 /** 1144 * @brief SPI Slave (SPIS0) 1145 */ 1146 1147 typedef struct { /*!< (@ 0x40004000) SPIS0 Structure */ 1148 __IM uint32_t RESERVED[9]; 1149 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1150 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1151 to acquire it */ 1152 __IM uint32_t RESERVED1[54]; 1153 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1154 __IM uint32_t RESERVED2[2]; 1155 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1156 __IM uint32_t RESERVED3[5]; 1157 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1158 __IM uint32_t RESERVED4[53]; 1159 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1160 __IM uint32_t RESERVED5[64]; 1161 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1162 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1163 __IM uint32_t RESERVED6[61]; 1164 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1165 __IM uint32_t RESERVED7[15]; 1166 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1167 __IM uint32_t RESERVED8[47]; 1168 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1169 __IM uint32_t RESERVED9; 1170 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1171 __IM uint32_t RESERVED10[7]; 1172 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1173 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1174 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1175 __IM uint32_t RESERVED11; 1176 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1177 of an ignored transaction. */ 1178 __IM uint32_t RESERVED12[24]; 1179 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1180 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1181 1182 1183 1184 /* =========================================================================================================================== */ 1185 /* ================ GPIOTE ================ */ 1186 /* =========================================================================================================================== */ 1187 1188 1189 /** 1190 * @brief GPIO Tasks and Events (GPIOTE) 1191 */ 1192 1193 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1194 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1195 specified in CONFIG[n].PSEL. Action on pin 1196 is configured in CONFIG[n].POLARITY. */ 1197 __IM uint32_t RESERVED[4]; 1198 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1199 specified in CONFIG[n].PSEL. Action on pin 1200 is to set it high. */ 1201 __IM uint32_t RESERVED1[4]; 1202 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1203 specified in CONFIG[n].PSEL. Action on pin 1204 is to set it low. */ 1205 __IM uint32_t RESERVED2[32]; 1206 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 1207 pin specified in CONFIG[n].PSEL */ 1208 __IM uint32_t RESERVED3[23]; 1209 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1210 with SENSE mechanism enabled */ 1211 __IM uint32_t RESERVED4[97]; 1212 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1213 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1214 __IM uint32_t RESERVED5[129]; 1215 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 1216 SET[n], and CLR[n] tasks and IN[n] event */ 1217 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1218 1219 1220 1221 /* =========================================================================================================================== */ 1222 /* ================ SAADC ================ */ 1223 /* =========================================================================================================================== */ 1224 1225 1226 /** 1227 * @brief Analog to Digital Converter (SAADC) 1228 */ 1229 1230 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1231 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 1232 RAM */ 1233 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 1234 are sampled */ 1235 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ 1236 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1237 __IM uint32_t RESERVED[60]; 1238 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 1239 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 1240 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1241 on the mode, multiple conversions might 1242 be needed for a result to be transferred 1243 to RAM. */ 1244 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ 1245 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1246 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 1247 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 1248 __IM uint32_t RESERVED1[106]; 1249 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1250 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1251 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1252 __IM uint32_t RESERVED2[61]; 1253 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1254 __IM uint32_t RESERVED3[63]; 1255 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 1256 __IM uint32_t RESERVED4[3]; 1257 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1258 __IM uint32_t RESERVED5[24]; 1259 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1260 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 1261 not be combined with SCAN. The RESOLUTION 1262 is applied before averaging, thus for high 1263 OVERSAMPLE a higher RESOLUTION should be 1264 used. */ 1265 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1266 __IM uint32_t RESERVED6[12]; 1267 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1268 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1269 1270 1271 1272 /* =========================================================================================================================== */ 1273 /* ================ TIMER0 ================ */ 1274 /* =========================================================================================================================== */ 1275 1276 1277 /** 1278 * @brief Timer/Counter 0 (TIMER0) 1279 */ 1280 1281 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1282 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1283 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1284 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1285 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1286 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1287 __IM uint32_t RESERVED[11]; 1288 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 1289 CC[n] register */ 1290 __IM uint32_t RESERVED1[58]; 1291 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1292 match */ 1293 __IM uint32_t RESERVED2[42]; 1294 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1295 __IM uint32_t RESERVED3[64]; 1296 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1297 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1298 __IM uint32_t RESERVED4[126]; 1299 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1300 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1301 __IM uint32_t RESERVED5; 1302 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1303 __IM uint32_t RESERVED6[11]; 1304 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 1305 n */ 1306 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1307 1308 1309 1310 /* =========================================================================================================================== */ 1311 /* ================ RTC0 ================ */ 1312 /* =========================================================================================================================== */ 1313 1314 1315 /** 1316 * @brief Real time counter 0 (RTC0) 1317 */ 1318 1319 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1320 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1321 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1322 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1323 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1324 __IM uint32_t RESERVED[60]; 1325 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1326 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1327 __IM uint32_t RESERVED1[14]; 1328 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 1329 match */ 1330 __IM uint32_t RESERVED2[109]; 1331 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1332 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1333 __IM uint32_t RESERVED3[13]; 1334 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1335 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1336 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1337 __IM uint32_t RESERVED4[110]; 1338 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1339 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1340 t be written when RTC is stopped */ 1341 __IM uint32_t RESERVED5[13]; 1342 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 1343 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1344 1345 1346 1347 /* =========================================================================================================================== */ 1348 /* ================ TEMP ================ */ 1349 /* =========================================================================================================================== */ 1350 1351 1352 /** 1353 * @brief Temperature Sensor (TEMP) 1354 */ 1355 1356 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1357 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1358 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1359 __IM uint32_t RESERVED[62]; 1360 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1361 __IM uint32_t RESERVED1[128]; 1362 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1363 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1364 __IM uint32_t RESERVED2[127]; 1365 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1366 __IM uint32_t RESERVED3[5]; 1367 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ 1368 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ 1369 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ 1370 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ 1371 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ 1372 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ 1373 __IM uint32_t RESERVED4[2]; 1374 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ 1375 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ 1376 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ 1377 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ 1378 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ 1379 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ 1380 __IM uint32_t RESERVED5[2]; 1381 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ 1382 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ 1383 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ 1384 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ 1385 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ 1386 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1387 1388 1389 1390 /* =========================================================================================================================== */ 1391 /* ================ RNG ================ */ 1392 /* =========================================================================================================================== */ 1393 1394 1395 /** 1396 * @brief Random Number Generator (RNG) 1397 */ 1398 1399 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1400 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1401 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1402 __IM uint32_t RESERVED[62]; 1403 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1404 written to the VALUE register */ 1405 __IM uint32_t RESERVED1[63]; 1406 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1407 __IM uint32_t RESERVED2[64]; 1408 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1409 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1410 __IM uint32_t RESERVED3[126]; 1411 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1412 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1413 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1414 1415 1416 1417 /* =========================================================================================================================== */ 1418 /* ================ ECB ================ */ 1419 /* =========================================================================================================================== */ 1420 1421 1422 /** 1423 * @brief AES ECB Mode Encryption (ECB) 1424 */ 1425 1426 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1427 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1428 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1429 __IM uint32_t RESERVED[62]; 1430 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1431 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1432 task or due to an error */ 1433 __IM uint32_t RESERVED1[127]; 1434 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1435 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1436 __IM uint32_t RESERVED2[126]; 1437 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1438 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1439 1440 1441 1442 /* =========================================================================================================================== */ 1443 /* ================ AAR ================ */ 1444 /* =========================================================================================================================== */ 1445 1446 1447 /** 1448 * @brief Accelerated Address Resolver (AAR) 1449 */ 1450 1451 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1452 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1453 in the IRK data structure */ 1454 __IM uint32_t RESERVED; 1455 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1456 __IM uint32_t RESERVED1[61]; 1457 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1458 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1459 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1460 __IM uint32_t RESERVED2[126]; 1461 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1462 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1463 __IM uint32_t RESERVED3[61]; 1464 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1465 __IM uint32_t RESERVED4[63]; 1466 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1467 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1468 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1469 __IM uint32_t RESERVED5; 1470 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1471 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1472 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1473 1474 1475 1476 /* =========================================================================================================================== */ 1477 /* ================ CCM ================ */ 1478 /* =========================================================================================================================== */ 1479 1480 1481 /** 1482 * @brief AES CCM Mode Encryption (CCM) 1483 */ 1484 1485 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1486 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation 1487 will stop by itself when completed. */ 1488 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1489 stop by itself when completed. */ 1490 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1491 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1492 the contents of the RATEOVERRIDE register 1493 for any ongoing encryption/decryption */ 1494 __IM uint32_t RESERVED[60]; 1495 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ 1496 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1497 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1498 __IM uint32_t RESERVED1[61]; 1499 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1500 __IM uint32_t RESERVED2[64]; 1501 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1502 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1503 __IM uint32_t RESERVED3[61]; 1504 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 1505 __IM uint32_t RESERVED4[63]; 1506 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 1507 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 1508 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 1509 NONCE vector */ 1510 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 1511 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 1512 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1513 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH 1514 = Extended. */ 1515 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 1516 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 1517 1518 1519 1520 /* =========================================================================================================================== */ 1521 /* ================ WDT ================ */ 1522 /* =========================================================================================================================== */ 1523 1524 1525 /** 1526 * @brief Watchdog Timer (WDT) 1527 */ 1528 1529 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 1530 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 1531 __IM uint32_t RESERVED[63]; 1532 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 1533 __IM uint32_t RESERVED1[128]; 1534 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1535 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1536 __IM uint32_t RESERVED2[61]; 1537 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 1538 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 1539 __IM uint32_t RESERVED3[63]; 1540 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 1541 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 1542 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 1543 __IM uint32_t RESERVED4[60]; 1544 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 1545 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 1546 1547 1548 1549 /* =========================================================================================================================== */ 1550 /* ================ QDEC ================ */ 1551 /* =========================================================================================================================== */ 1552 1553 1554 /** 1555 * @brief Quadrature Decoder (QDEC) 1556 */ 1557 1558 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 1559 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 1560 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 1561 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 1562 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 1563 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 1564 __IM uint32_t RESERVED[59]; 1565 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 1566 written to the SAMPLE register */ 1567 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 1568 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 1569 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 1570 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 1571 __IM uint32_t RESERVED1[59]; 1572 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1573 __IM uint32_t RESERVED2[64]; 1574 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1575 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1576 __IM uint32_t RESERVED3[125]; 1577 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 1578 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 1579 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 1580 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 1581 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 1582 and DBLRDY events can be generated */ 1583 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 1584 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 1585 READCLRACC or RDCLRACC task */ 1586 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 1587 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 1588 __IM uint32_t RESERVED4[5]; 1589 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 1590 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 1591 double transitions */ 1592 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 1593 or RDCLRDBL task */ 1594 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 1595 1596 1597 1598 /* =========================================================================================================================== */ 1599 /* ================ EGU0 ================ */ 1600 /* =========================================================================================================================== */ 1601 1602 1603 /** 1604 * @brief Event generator unit 0 (EGU0) 1605 */ 1606 1607 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 1608 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 1609 the corresponding TRIGGERED[n] event */ 1610 __IM uint32_t RESERVED[48]; 1611 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 1612 by triggering the corresponding TRIGGER[n] 1613 task */ 1614 __IM uint32_t RESERVED1[112]; 1615 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1616 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1617 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1618 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 1619 1620 1621 1622 /* =========================================================================================================================== */ 1623 /* ================ SWI0 ================ */ 1624 /* =========================================================================================================================== */ 1625 1626 1627 /** 1628 * @brief Software interrupt 0 (SWI0) 1629 */ 1630 1631 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 1632 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 1633 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 1634 1635 1636 1637 /* =========================================================================================================================== */ 1638 /* ================ NVMC ================ */ 1639 /* =========================================================================================================================== */ 1640 1641 1642 /** 1643 * @brief Non Volatile Memory Controller (NVMC) 1644 */ 1645 1646 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 1647 __IM uint32_t RESERVED[256]; 1648 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 1649 __IM uint32_t RESERVED1[64]; 1650 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1651 1652 union { 1653 __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 1654 __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 1655 page in code area, equivalent to ERASEPAGE */ 1656 }; 1657 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 1658 __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 1659 page in code area, equivalent to ERASEPAGE */ 1660 __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 1661 registers */ 1662 __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 1663 area */ 1664 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 1665 } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ 1666 1667 1668 1669 /* =========================================================================================================================== */ 1670 /* ================ PPI ================ */ 1671 /* =========================================================================================================================== */ 1672 1673 1674 /** 1675 * @brief Programmable Peripheral Interconnect (PPI) 1676 */ 1677 1678 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 1679 __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 1680 __IM uint32_t RESERVED[308]; 1681 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 1682 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 1683 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 1684 __IM uint32_t RESERVED1; 1685 __IOM PPI_CH_Type CH[10]; /*!< (@ 0x00000510) PPI Channel */ 1686 __IM uint32_t RESERVED2[168]; 1687 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ 1688 __IM uint32_t RESERVED3[62]; 1689 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 1690 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 1691 1692 1693 /** @} */ /* End of group Device_Peripheral_peripherals */ 1694 1695 1696 /* =========================================================================================================================== */ 1697 /* ================ Device Specific Peripheral Address Map ================ */ 1698 /* =========================================================================================================================== */ 1699 1700 1701 /** @addtogroup Device_Peripheral_peripheralAddr 1702 * @{ 1703 */ 1704 1705 #define NRF_FICR_BASE 0x10000000UL 1706 #define NRF_UICR_BASE 0x10001000UL 1707 #define NRF_BPROT_BASE 0x40000000UL 1708 #define NRF_CLOCK_BASE 0x40000000UL 1709 #define NRF_POWER_BASE 0x40000000UL 1710 #define NRF_P0_BASE 0x50000000UL 1711 #define NRF_RADIO_BASE 0x40001000UL 1712 #define NRF_UART0_BASE 0x40002000UL 1713 #define NRF_UARTE0_BASE 0x40002000UL 1714 #define NRF_TWI0_BASE 0x40003000UL 1715 #define NRF_TWIM0_BASE 0x40003000UL 1716 #define NRF_TWIS0_BASE 0x40003000UL 1717 #define NRF_SPI0_BASE 0x40004000UL 1718 #define NRF_SPIM0_BASE 0x40004000UL 1719 #define NRF_SPIS0_BASE 0x40004000UL 1720 #define NRF_GPIOTE_BASE 0x40006000UL 1721 #define NRF_SAADC_BASE 0x40007000UL 1722 #define NRF_TIMER0_BASE 0x40008000UL 1723 #define NRF_TIMER1_BASE 0x40009000UL 1724 #define NRF_TIMER2_BASE 0x4000A000UL 1725 #define NRF_RTC0_BASE 0x4000B000UL 1726 #define NRF_TEMP_BASE 0x4000C000UL 1727 #define NRF_RNG_BASE 0x4000D000UL 1728 #define NRF_ECB_BASE 0x4000E000UL 1729 #define NRF_AAR_BASE 0x4000F000UL 1730 #define NRF_CCM_BASE 0x4000F000UL 1731 #define NRF_WDT_BASE 0x40010000UL 1732 #define NRF_RTC1_BASE 0x40011000UL 1733 #define NRF_QDEC_BASE 0x40012000UL 1734 #define NRF_EGU0_BASE 0x40014000UL 1735 #define NRF_SWI0_BASE 0x40014000UL 1736 #define NRF_EGU1_BASE 0x40015000UL 1737 #define NRF_SWI1_BASE 0x40015000UL 1738 #define NRF_SWI2_BASE 0x40016000UL 1739 #define NRF_SWI3_BASE 0x40017000UL 1740 #define NRF_SWI4_BASE 0x40018000UL 1741 #define NRF_SWI5_BASE 0x40019000UL 1742 #define NRF_NVMC_BASE 0x4001E000UL 1743 #define NRF_PPI_BASE 0x4001F000UL 1744 1745 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 1746 1747 1748 /* =========================================================================================================================== */ 1749 /* ================ Peripheral declaration ================ */ 1750 /* =========================================================================================================================== */ 1751 1752 1753 /** @addtogroup Device_Peripheral_declaration 1754 * @{ 1755 */ 1756 1757 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 1758 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 1759 #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) 1760 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 1761 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 1762 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 1763 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 1764 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 1765 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 1766 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 1767 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 1768 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 1769 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 1770 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 1771 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 1772 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 1773 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 1774 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 1775 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 1776 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 1777 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 1778 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 1779 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 1780 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 1781 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 1782 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 1783 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 1784 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 1785 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 1786 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 1787 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 1788 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 1789 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 1790 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 1791 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 1792 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 1793 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 1794 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 1795 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 1796 1797 /** @} */ /* End of group Device_Peripheral_declaration */ 1798 1799 1800 /* ========================================= End of section using anonymous unions ========================================= */ 1801 #if defined (__CC_ARM) 1802 #pragma pop 1803 #elif defined (__ICCARM__) 1804 /* leave anonymous unions enabled */ 1805 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 1806 #pragma clang diagnostic pop 1807 #elif defined (__GNUC__) 1808 /* anonymous unions are enabled by default */ 1809 #elif defined (__TMS470__) 1810 /* anonymous unions are enabled by default */ 1811 #elif defined (__TASKING__) 1812 #pragma warning restore 1813 #elif defined (__CSMC__) 1814 /* anonymous unions are enabled by default */ 1815 #endif 1816 1817 1818 #ifdef __cplusplus 1819 } 1820 #endif 1821 1822 #endif /* NRF52805_H */ 1823 1824 1825 /** @} */ /* End of group nrf52805 */ 1826 1827 /** @} */ /* End of group Nordic Semiconductor */ 1828