1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5#include "nuvoton-common-npcm7xx.dtsi"
6
7/ {
8	#address-cells = <1>;
9	#size-cells = <1>;
10	interrupt-parent = <&gic>;
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15		enable-method = "nuvoton,npcm750-smp";
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-a9";
20			clocks = <&clk NPCM7XX_CLK_CPU>;
21			clock-names = "clk_cpu";
22			reg = <0>;
23			next-level-cache = <&l2>;
24		};
25
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a9";
29			clocks = <&clk NPCM7XX_CLK_CPU>;
30			clock-names = "clk_cpu";
31			reg = <1>;
32			next-level-cache = <&l2>;
33		};
34	};
35
36	soc {
37		timer@3fe600 {
38			compatible = "arm,cortex-a9-twd-timer";
39			reg = <0x3fe600 0x20>;
40			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
41						  IRQ_TYPE_LEVEL_HIGH)>;
42			clocks = <&clk NPCM7XX_CLK_AHB>;
43		};
44	};
45
46	ahb {
47		gmac1: eth@f0804000 {
48			device_type = "network";
49			compatible = "snps,dwmac";
50			reg = <0xf0804000 0x2000>;
51			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
52			interrupt-names = "macirq";
53			ethernet = <1>;
54			clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>;
55			clock-names = "stmmaceth", "clk_gmac";
56			pinctrl-names = "default";
57			pinctrl-0 = <&rg2_pins
58					&rg2mdio_pins>;
59			status = "disabled";
60		};
61	};
62};
63