1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DDR_OPTS_H 9 #define DDR_OPTS_H 10 11 #define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */ 12 13 #define DDR_BC4 4 /* burst chop */ 14 #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 15 #define DDR_BL8 8 /* burst length 8 */ 16 17 #define DDR4_RTT_OFF 0 18 #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 19 #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 20 #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 21 #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 22 #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 23 #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 24 #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 25 #define DDR4_RTT_WR_OFF 0 26 #define DDR4_RTT_WR_120_OHM 1 27 #define DDR4_RTT_WR_240_OHM 2 28 #define DDR4_RTT_WR_HZ 3 29 #define DDR4_RTT_WR_80_OHM 4 30 #define DDR_ODT_NEVER 0x0 31 #define DDR_ODT_CS 0x1 32 #define DDR_ODT_ALL_OTHER_CS 0x2 33 #define DDR_ODT_OTHER_DIMM 0x3 34 #define DDR_ODT_ALL 0x4 35 #define DDR_ODT_SAME_DIMM 0x5 36 #define DDR_ODT_CS_AND_OTHER_DIMM 0x6 37 #define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 38 #define DDR_BA_INTLV_CS01 0x40 39 #define DDR_BA_INTLV_CS0123 0x64 40 #define DDR_BA_NONE 0 41 #define DDR_256B_INTLV 0x8 42 43 struct memctl_opt { 44 int rdimm; 45 unsigned int dbw_cap_shift; 46 struct local_opts_s { 47 unsigned int auto_precharge; 48 unsigned int odt_rd_cfg; 49 unsigned int odt_wr_cfg; 50 unsigned int odt_rtt_norm; 51 unsigned int odt_rtt_wr; 52 } cs_odt[DDRC_NUM_CS]; 53 int ctlr_intlv; 54 unsigned int ctlr_intlv_mode; 55 unsigned int ba_intlv; 56 int addr_hash; 57 int ecc_mode; 58 int ctlr_init_ecc; 59 int self_refresh_in_sleep; 60 int self_refresh_irq_en; 61 int dynamic_power; 62 /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ 63 unsigned int data_bus_dimm; 64 unsigned int data_bus_used; /* on individual board */ 65 unsigned int burst_length; /* BC4, OTF and BL8 */ 66 int otf_burst_chop_en; 67 int mirrored_dimm; 68 int quad_rank_present; 69 int output_driver_impedance; 70 int ap_en; 71 int x4_en; 72 73 int caslat_override; 74 unsigned int caslat_override_value; 75 int addt_lat_override; 76 unsigned int addt_lat_override_value; 77 78 unsigned int clk_adj; 79 unsigned int cpo_sample; 80 unsigned int wr_data_delay; 81 82 unsigned int cswl_override; 83 unsigned int wrlvl_override; 84 unsigned int wrlvl_sample; 85 unsigned int wrlvl_start; 86 unsigned int wrlvl_ctl_2; 87 unsigned int wrlvl_ctl_3; 88 89 int half_strength_drive_en; 90 int twot_en; 91 int threet_en; 92 unsigned int bstopre; 93 unsigned int tfaw_ps; 94 95 int rtt_override; 96 unsigned int rtt_override_value; 97 unsigned int rtt_wr_override_value; 98 unsigned int rtt_park; 99 100 int auto_self_refresh_en; 101 unsigned int sr_it; 102 unsigned int ddr_cdr1; 103 unsigned int ddr_cdr2; 104 105 unsigned int trwt_override; 106 unsigned int trwt; 107 unsigned int twrt; 108 unsigned int trrt; 109 unsigned int twwt; 110 111 unsigned int vref_phy; 112 unsigned int vref_dimm; 113 unsigned int odt; 114 unsigned int phy_tx_impedance; 115 unsigned int phy_atx_impedance; 116 unsigned int skip2d; 117 }; 118 119 #endif /* DDR_OPTS_H */ 120