1 /*
2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/arm/sp804_delay_timer.h>
15 #include <lib/mmio.h>
16
17 #include <bcm_console.h>
18 #include <platform_def.h>
19 #include <plat/brcm/common/plat_brcm.h>
20
21 /* Data structure which holds the extents of the trusted SRAM for BL2 */
22 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
23
24 /* Weak definitions may be overridden in specific BRCM platform */
25 #pragma weak plat_bcm_bl2_platform_setup
26 #pragma weak plat_bcm_bl2_plat_arch_setup
27 #pragma weak plat_bcm_security_setup
28 #pragma weak plat_bcm_bl2_plat_handle_scp_bl2
29 #pragma weak plat_bcm_bl2_early_platform_setup
30
plat_bcm_bl2_early_platform_setup(void)31 void plat_bcm_bl2_early_platform_setup(void)
32 {
33 }
34
plat_bcm_bl2_platform_setup(void)35 void plat_bcm_bl2_platform_setup(void)
36 {
37 }
38
plat_bcm_bl2_plat_arch_setup(void)39 void plat_bcm_bl2_plat_arch_setup(void)
40 {
41 }
42
plat_bcm_security_setup(void)43 void plat_bcm_security_setup(void)
44 {
45 }
46
bcm_bl2_early_platform_setup(uintptr_t tb_fw_config,meminfo_t * mem_layout)47 void bcm_bl2_early_platform_setup(uintptr_t tb_fw_config,
48 meminfo_t *mem_layout)
49 {
50 /* Initialize the console to provide early debug support */
51 bcm_console_boot_init();
52
53 /* Setup the BL2 memory layout */
54 bl2_tzram_layout = *mem_layout;
55
56 /* Initialise the IO layer and register platform IO devices */
57 plat_brcm_io_setup();
58
59 /* Log HW reset event */
60 INFO("RESET: 0x%x\n",
61 mmio_read_32(CRMU_RESET_EVENT_LOG));
62 }
63
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)64 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
65 u_register_t arg2, u_register_t arg3)
66 {
67 /* SoC specific setup */
68 plat_bcm_bl2_early_platform_setup();
69
70 /* Initialize delay timer driver using SP804 dual timer 0 */
71 sp804_timer_init(SP804_TIMER0_BASE,
72 SP804_TIMER0_CLKMULT, SP804_TIMER0_CLKDIV);
73
74 /* BRCM platforms generic setup */
75 bcm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
76 }
77
78 /*
79 * Perform Broadcom platform setup.
80 */
bcm_bl2_platform_setup(void)81 void bcm_bl2_platform_setup(void)
82 {
83 /* Initialize the secure environment */
84 plat_bcm_security_setup();
85 }
86
bl2_platform_setup(void)87 void bl2_platform_setup(void)
88 {
89 bcm_bl2_platform_setup();
90 plat_bcm_bl2_platform_setup();
91 }
92
93 /*******************************************************************************
94 * Perform the very early platform specific architectural setup here. At the
95 * moment this is only initializes the mmu in a quick and dirty way.
96 ******************************************************************************/
bcm_bl2_plat_arch_setup(void)97 void bcm_bl2_plat_arch_setup(void)
98 {
99 #ifndef MMU_DISABLED
100 if (!(read_sctlr_el1() & SCTLR_M_BIT)) {
101 const mmap_region_t bl_regions[] = {
102 MAP_REGION_FLAT(bl2_tzram_layout.total_base,
103 bl2_tzram_layout.total_size,
104 MT_MEMORY | MT_RW | MT_SECURE),
105 MAP_REGION_FLAT(BL_CODE_BASE,
106 BL_CODE_END - BL_CODE_BASE,
107 MT_CODE | MT_SECURE),
108 MAP_REGION_FLAT(BL_RO_DATA_BASE,
109 BL_RO_DATA_END - BL_RO_DATA_BASE,
110 MT_RO_DATA | MT_SECURE),
111 #if USE_COHERENT_MEM
112 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
113 BL_COHERENT_RAM_END -
114 BL_COHERENT_RAM_BASE,
115 MT_DEVICE | MT_RW | MT_SECURE),
116 #endif
117 {0}
118 };
119
120 setup_page_tables(bl_regions, plat_brcm_get_mmap());
121 enable_mmu_el1(0);
122 }
123 #endif
124 }
125
bl2_plat_arch_setup(void)126 void bl2_plat_arch_setup(void)
127 {
128 #ifdef ENA_MMU_BEFORE_DDR_INIT
129 /*
130 * Once MMU is enabled before DDR, MEMORY TESTS
131 * get affected as read/write transaction might occures from
132 * caches. So For running memory test, one should not set this
133 * flag.
134 */
135 bcm_bl2_plat_arch_setup();
136 plat_bcm_bl2_plat_arch_setup();
137 #else
138 plat_bcm_bl2_plat_arch_setup();
139 bcm_bl2_plat_arch_setup();
140 #endif
141 }
142
bcm_bl2_handle_post_image_load(unsigned int image_id)143 int bcm_bl2_handle_post_image_load(unsigned int image_id)
144 {
145 int err = 0;
146
147 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
148
149 assert(bl_mem_params);
150
151 switch (image_id) {
152 case BL32_IMAGE_ID:
153 bl_mem_params->ep_info.spsr = brcm_get_spsr_for_bl32_entry();
154 break;
155
156 case BL33_IMAGE_ID:
157 /* BL33 expects to receive the primary CPU MPID (through r0) */
158 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
159 bl_mem_params->ep_info.spsr = brcm_get_spsr_for_bl33_entry();
160 break;
161
162 #ifdef SCP_BL2_BASE
163 case SCP_BL2_IMAGE_ID:
164 /* The subsequent handling of SCP_BL2 is platform specific */
165 err = bcm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
166 if (err)
167 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
168 break;
169 #endif
170 default:
171 /* Do nothing in default case */
172 break;
173 }
174
175 return err;
176 }
177
178 /*******************************************************************************
179 * This function can be used by the platforms to update/use image
180 * information for given `image_id`.
181 ******************************************************************************/
bcm_bl2_plat_handle_post_image_load(unsigned int image_id)182 int bcm_bl2_plat_handle_post_image_load(unsigned int image_id)
183 {
184 return bcm_bl2_handle_post_image_load(image_id);
185 }
186
bl2_plat_handle_post_image_load(unsigned int image_id)187 int bl2_plat_handle_post_image_load(unsigned int image_id)
188 {
189 return bcm_bl2_plat_handle_post_image_load(image_id);
190 }
191
192 #ifdef SCP_BL2_BASE
plat_bcm_bl2_plat_handle_scp_bl2(image_info_t * scp_bl2_image_info)193 int plat_bcm_bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
194 {
195 return 0;
196 }
197
bcm_bl2_handle_scp_bl2(image_info_t * scp_bl2_image_info)198 int bcm_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
199 {
200 return plat_bcm_bl2_plat_handle_scp_bl2(scp_bl2_image_info);
201 }
202 #endif
203