1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <inttypes.h>
10 #include <stdint.h>
11 #include <string.h>
12
13 #include <arch_helpers.h>
14 #include <bl1/tbbr/tbbr_img_desc.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/mmc.h>
19 #include <drivers/synopsys/dw_mmc.h>
20 #include <lib/mmio.h>
21 #include <plat/common/platform.h>
22
23 #include <hi6220.h>
24 #include <hikey_def.h>
25 #include <hikey_layout.h>
26
27 #include "hikey_private.h"
28
29 /* Data structure which holds the extents of the trusted RAM for BL1 */
30 static meminfo_t bl1_tzram_layout;
31 static console_t console;
32 static struct mmc_device_info mmc_info;
33
34 enum {
35 BOOT_NORMAL = 0,
36 BOOT_USB_DOWNLOAD,
37 BOOT_UART_DOWNLOAD,
38 };
39
bl1_plat_sec_mem_layout(void)40 meminfo_t *bl1_plat_sec_mem_layout(void)
41 {
42 return &bl1_tzram_layout;
43 }
44
45 /*
46 * Perform any BL1 specific platform actions.
47 */
bl1_early_platform_setup(void)48 void bl1_early_platform_setup(void)
49 {
50 /* Initialize the console to provide early debug support */
51 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
52 PL011_BAUDRATE, &console);
53
54 /* Allow BL1 to see the whole Trusted RAM */
55 bl1_tzram_layout.total_base = BL1_RW_BASE;
56 bl1_tzram_layout.total_size = BL1_RW_SIZE;
57
58 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
59 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
60 }
61
62 /*
63 * Perform the very early platform specific architecture setup here. At the
64 * moment this only does basic initialization. Later architectural setup
65 * (bl1_arch_setup()) does not do anything platform specific.
66 */
bl1_plat_arch_setup(void)67 void bl1_plat_arch_setup(void)
68 {
69 hikey_init_mmu_el3(bl1_tzram_layout.total_base,
70 bl1_tzram_layout.total_size,
71 BL1_RO_BASE,
72 BL1_RO_LIMIT,
73 BL_COHERENT_RAM_BASE,
74 BL_COHERENT_RAM_END);
75 }
76
77 /*
78 * Function which will perform any remaining platform-specific setup that can
79 * occur after the MMU and data cache have been enabled.
80 */
bl1_platform_setup(void)81 void bl1_platform_setup(void)
82 {
83 dw_mmc_params_t params;
84
85 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
86 ((SRAM_BASE + SRAM_SIZE) >=
87 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE)));
88 hikey_sp804_init();
89 hikey_gpio_init();
90 hikey_pmussi_init();
91 hikey_hi6553_init();
92
93 hikey_rtc_init();
94
95 hikey_mmc_pll_init();
96
97 memset(¶ms, 0, sizeof(dw_mmc_params_t));
98 params.reg_base = DWMMC0_BASE;
99 params.desc_base = HIKEY_BL1_MMC_DESC_BASE;
100 params.desc_size = 1 << 20;
101 params.clk_rate = 24 * 1000 * 1000;
102 params.bus_width = MMC_BUS_WIDTH_8;
103 params.flags = MMC_FLAG_CMD23;
104 mmc_info.mmc_dev_type = MMC_IS_EMMC;
105 dw_mmc_init(¶ms, &mmc_info);
106
107 hikey_io_setup();
108 }
109
110 /*
111 * The following function checks if Firmware update is needed,
112 * by checking if TOC in FIP image is valid or not.
113 */
bl1_plat_get_next_image_id(void)114 unsigned int bl1_plat_get_next_image_id(void)
115 {
116 int32_t boot_mode;
117 unsigned int ret;
118
119 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
120 switch (boot_mode) {
121 case BOOT_USB_DOWNLOAD:
122 case BOOT_UART_DOWNLOAD:
123 ret = NS_BL1U_IMAGE_ID;
124 break;
125 default:
126 WARN("Invalid boot mode is found:%d\n", boot_mode);
127 panic();
128 }
129 return ret;
130 }
131
bl1_plat_get_image_desc(unsigned int image_id)132 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id)
133 {
134 unsigned int index = 0;
135
136 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) {
137 if (bl1_tbbr_image_descs[index].image_id == image_id)
138 return &bl1_tbbr_image_descs[index];
139
140 index++;
141 }
142
143 return NULL;
144 }
145
bl1_plat_set_ep_info(unsigned int image_id,entry_point_info_t * ep_info)146 void bl1_plat_set_ep_info(unsigned int image_id,
147 entry_point_info_t *ep_info)
148 {
149 uint64_t data = 0;
150
151 if (image_id == BL2_IMAGE_ID)
152 panic();
153 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
154 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
155 do {
156 data |= 3 << 20;
157 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data));
158 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
159 } while ((data & (3 << 20)) != (3 << 20));
160 INFO("cpacr_el1:0x%" PRIx64 "\n", data);
161
162 ep_info->args.arg0 = 0xffff & read_mpidr();
163 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
164 DISABLE_ALL_EXCEPTIONS);
165 }
166