1 /*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 #include <lib/mmio.h>
15 #include <lib/psci/psci.h>
16 #include <plat/common/platform.h>
17
18 #include <rpi_hw.h>
19
20 #ifdef RPI_HAVE_GIC
21 #include <drivers/arm/gicv2.h>
22 #endif
23
24 /* Make composite power state parameter till power level 0 */
25 #if PSCI_EXTENDED_STATE_ID
26
27 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
28 (((lvl0_state) << PSTATE_ID_SHIFT) | \
29 ((type) << PSTATE_TYPE_SHIFT))
30
31 #else
32
33 #define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
34 (((lvl0_state) << PSTATE_ID_SHIFT) | \
35 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
36 ((type) << PSTATE_TYPE_SHIFT))
37
38 #endif /* PSCI_EXTENDED_STATE_ID */
39
40 #define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
41 (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \
42 rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
43
44 /*
45 * The table storing the valid idle power states. Ensure that the
46 * array entries are populated in ascending order of state-id to
47 * enable us to use binary search during power state validation.
48 * The table must be terminated by a NULL entry.
49 */
50 static const unsigned int rpi3_pm_idle_states[] = {
51 /* State-id - 0x01 */
52 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET,
53 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
54 /* State-id - 0x02 */
55 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF,
56 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
57 /* State-id - 0x22 */
58 rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF,
59 MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN),
60 0,
61 };
62
63 /*******************************************************************************
64 * Platform handler called to check the validity of the power state
65 * parameter. The power state parameter has to be a composite power state.
66 ******************************************************************************/
rpi3_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)67 static int rpi3_validate_power_state(unsigned int power_state,
68 psci_power_state_t *req_state)
69 {
70 unsigned int state_id;
71 int i;
72
73 assert(req_state != 0);
74
75 /*
76 * Currently we are using a linear search for finding the matching
77 * entry in the idle power state array. This can be made a binary
78 * search if the number of entries justify the additional complexity.
79 */
80 for (i = 0; rpi3_pm_idle_states[i] != 0; i++) {
81 if (power_state == rpi3_pm_idle_states[i]) {
82 break;
83 }
84 }
85
86 /* Return error if entry not found in the idle state array */
87 if (!rpi3_pm_idle_states[i]) {
88 return PSCI_E_INVALID_PARAMS;
89 }
90
91 i = 0;
92 state_id = psci_get_pstate_id(power_state);
93
94 /* Parse the State ID and populate the state info parameter */
95 while (state_id) {
96 req_state->pwr_domain_state[i++] = state_id &
97 PLAT_LOCAL_PSTATE_MASK;
98 state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
99 }
100
101 return PSCI_E_SUCCESS;
102 }
103
104 /*******************************************************************************
105 * Platform handler called when a CPU is about to enter standby.
106 ******************************************************************************/
rpi3_cpu_standby(plat_local_state_t cpu_state)107 static void rpi3_cpu_standby(plat_local_state_t cpu_state)
108 {
109 assert(cpu_state == PLAT_LOCAL_STATE_RET);
110
111 /*
112 * Enter standby state.
113 * dsb is good practice before using wfi to enter low power states
114 */
115 dsb();
116 wfi();
117 }
118
rpi3_pwr_domain_off(const psci_power_state_t * target_state)119 static void rpi3_pwr_domain_off(const psci_power_state_t *target_state)
120 {
121 #ifdef RPI_HAVE_GIC
122 gicv2_cpuif_disable();
123 #endif
124 }
125
126 /*******************************************************************************
127 * Platform handler called when a power domain is about to be turned on. The
128 * mpidr determines the CPU to be turned on.
129 ******************************************************************************/
rpi3_pwr_domain_on(u_register_t mpidr)130 static int rpi3_pwr_domain_on(u_register_t mpidr)
131 {
132 int rc = PSCI_E_SUCCESS;
133 unsigned int pos = plat_core_pos_by_mpidr(mpidr);
134 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
135
136 assert(pos < PLATFORM_CORE_COUNT);
137
138 hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE;
139
140 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO);
141 /* No cache maintenance here, hold_base is mapped as device memory. */
142
143 /* Make sure that the write has completed */
144 dsb();
145 isb();
146
147 sev();
148
149 return rc;
150 }
151
152 /*******************************************************************************
153 * Platform handler called when a power domain has just been powered on after
154 * being turned off earlier. The target_state encodes the low power state that
155 * each level has woken up from.
156 ******************************************************************************/
rpi3_pwr_domain_on_finish(const psci_power_state_t * target_state)157 static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state)
158 {
159 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
160 PLAT_LOCAL_STATE_OFF);
161
162 #ifdef RPI_HAVE_GIC
163 gicv2_pcpu_distif_init();
164 gicv2_cpuif_enable();
165 #endif
166 }
167
rpi3_pwr_down_wfi(const psci_power_state_t * target_state)168 static void __dead2 rpi3_pwr_down_wfi(
169 const psci_power_state_t *target_state)
170 {
171 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
172 unsigned int pos = plat_my_core_pos();
173
174 if (pos == 0) {
175 /*
176 * The secondaries will always be in a wait
177 * for warm boot on reset, but the BSP needs
178 * to be able to distinguish between waiting
179 * for warm boot (e.g. after psci_off, waiting
180 * for psci_on) and a cold boot.
181 */
182 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF);
183 /* No cache maintenance here, we run with caches off already. */
184 dsb();
185 isb();
186 }
187
188 write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
189
190 while (1) {
191 wfi();
192 }
193 }
194
195 /*******************************************************************************
196 * Platform handlers for system reset and system off.
197 ******************************************************************************/
198
199 /* 10 ticks (Watchdog timer = Timer clock / 16) */
200 #define RESET_TIMEOUT U(10)
201
rpi3_watchdog_reset(void)202 static void __dead2 rpi3_watchdog_reset(void)
203 {
204 uint32_t rstc;
205
206 console_flush();
207
208 dsbsy();
209 isb();
210
211 mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET,
212 RPI3_PM_PASSWORD | RESET_TIMEOUT);
213
214 rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET);
215 rstc &= ~RPI3_PM_RSTC_WRCFG_MASK;
216 rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET;
217 mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc);
218
219 for (;;) {
220 wfi();
221 }
222 }
223
rpi3_system_reset(void)224 static void __dead2 rpi3_system_reset(void)
225 {
226 INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n");
227
228 rpi3_watchdog_reset();
229 }
230
rpi3_system_off(void)231 static void __dead2 rpi3_system_off(void)
232 {
233 uint32_t rsts;
234
235 INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n");
236
237 /*
238 * This function doesn't actually make the Raspberry Pi turn itself off,
239 * the hardware doesn't allow it. It simply reboots it and the RSTS
240 * value tells the bootcode.bin firmware not to continue the regular
241 * bootflow and to stay in a low power mode.
242 */
243
244 rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET);
245 rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT;
246 mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts);
247
248 rpi3_watchdog_reset();
249 }
250
251 /*******************************************************************************
252 * Platform handlers and setup function.
253 ******************************************************************************/
254 static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
255 .cpu_standby = rpi3_cpu_standby,
256 .pwr_domain_off = rpi3_pwr_domain_off,
257 .pwr_domain_on = rpi3_pwr_domain_on,
258 .pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
259 .pwr_domain_pwr_down_wfi = rpi3_pwr_down_wfi,
260 .system_off = rpi3_system_off,
261 .system_reset = rpi3_system_reset,
262 .validate_power_state = rpi3_validate_power_state,
263 };
264
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)265 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
266 const plat_psci_ops_t **psci_ops)
267 {
268 uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT;
269
270 *entrypoint = sec_entrypoint;
271 *psci_ops = &plat_rpi3_psci_pm_ops;
272
273 return 0;
274 }
275