1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 xo_board: xo_board { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <19200000>; 22 }; 23 24 sleep_clk: sleep_clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <32768>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 interrupts = <GIC_PPI 9 0xf04>; 35 36 CPU0: cpu@0 { 37 compatible = "qcom,krait"; 38 enable-method = "qcom,kpss-acc-v2"; 39 device_type = "cpu"; 40 reg = <0>; 41 next-level-cache = <&L2>; 42 qcom,acc = <&acc0>; 43 qcom,saw = <&saw0>; 44 cpu-idle-states = <&CPU_SPC>; 45 }; 46 47 CPU1: cpu@1 { 48 compatible = "qcom,krait"; 49 enable-method = "qcom,kpss-acc-v2"; 50 device_type = "cpu"; 51 reg = <1>; 52 next-level-cache = <&L2>; 53 qcom,acc = <&acc1>; 54 qcom,saw = <&saw1>; 55 cpu-idle-states = <&CPU_SPC>; 56 }; 57 58 CPU2: cpu@2 { 59 compatible = "qcom,krait"; 60 enable-method = "qcom,kpss-acc-v2"; 61 device_type = "cpu"; 62 reg = <2>; 63 next-level-cache = <&L2>; 64 qcom,acc = <&acc2>; 65 qcom,saw = <&saw2>; 66 cpu-idle-states = <&CPU_SPC>; 67 }; 68 69 CPU3: cpu@3 { 70 compatible = "qcom,krait"; 71 enable-method = "qcom,kpss-acc-v2"; 72 device_type = "cpu"; 73 reg = <3>; 74 next-level-cache = <&L2>; 75 qcom,acc = <&acc3>; 76 qcom,saw = <&saw3>; 77 cpu-idle-states = <&CPU_SPC>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 qcom,saw = <&saw_l2>; 84 }; 85 86 idle-states { 87 CPU_SPC: spc { 88 compatible = "qcom,idle-state-spc", 89 "arm,idle-state"; 90 entry-latency-us = <150>; 91 exit-latency-us = <200>; 92 min-residency-us = <2000>; 93 }; 94 }; 95 }; 96 97 firmware { 98 scm { 99 compatible = "qcom,scm-msm8974", "qcom,scm"; 100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101 clock-names = "core", "bus", "iface"; 102 }; 103 }; 104 105 memory { 106 device_type = "memory"; 107 reg = <0x0 0x0>; 108 }; 109 110 pmu { 111 compatible = "qcom,krait-pmu"; 112 interrupts = <GIC_PPI 7 0xf04>; 113 }; 114 115 reserved-memory { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 mpss_region: mpss@8000000 { 121 reg = <0x08000000 0x5100000>; 122 no-map; 123 }; 124 125 mba_region: mba@d100000 { 126 reg = <0x0d100000 0x100000>; 127 no-map; 128 }; 129 130 wcnss_region: wcnss@d200000 { 131 reg = <0x0d200000 0xa00000>; 132 no-map; 133 }; 134 135 adsp_region: adsp@dc00000 { 136 reg = <0x0dc00000 0x1900000>; 137 no-map; 138 }; 139 140 venus_region: memory@f500000 { 141 reg = <0x0f500000 0x500000>; 142 no-map; 143 }; 144 145 smem_region: smem@fa00000 { 146 reg = <0xfa00000 0x200000>; 147 no-map; 148 }; 149 150 tz_region: memory@fc00000 { 151 reg = <0x0fc00000 0x160000>; 152 no-map; 153 }; 154 155 rfsa_mem: memory@fd60000 { 156 reg = <0x0fd60000 0x20000>; 157 no-map; 158 }; 159 160 rmtfs@fd80000 { 161 compatible = "qcom,rmtfs-mem"; 162 reg = <0x0fd80000 0x180000>; 163 no-map; 164 165 qcom,client-id = <1>; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 172 memory-region = <&smem_region>; 173 qcom,rpm-msg-ram = <&rpm_msg_ram>; 174 175 hwlocks = <&tcsr_mutex 3>; 176 }; 177 178 smp2p-adsp { 179 compatible = "qcom,smp2p"; 180 qcom,smem = <443>, <429>; 181 182 interrupt-parent = <&intc>; 183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 184 185 qcom,ipc = <&apcs 8 10>; 186 187 qcom,local-pid = <0>; 188 qcom,remote-pid = <2>; 189 190 adsp_smp2p_out: master-kernel { 191 qcom,entry-name = "master-kernel"; 192 #qcom,smem-state-cells = <1>; 193 }; 194 195 adsp_smp2p_in: slave-kernel { 196 qcom,entry-name = "slave-kernel"; 197 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 }; 202 203 smp2p-modem { 204 compatible = "qcom,smp2p"; 205 qcom,smem = <435>, <428>; 206 207 interrupt-parent = <&intc>; 208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 209 210 qcom,ipc = <&apcs 8 14>; 211 212 qcom,local-pid = <0>; 213 qcom,remote-pid = <1>; 214 215 modem_smp2p_out: master-kernel { 216 qcom,entry-name = "master-kernel"; 217 #qcom,smem-state-cells = <1>; 218 }; 219 220 modem_smp2p_in: slave-kernel { 221 qcom,entry-name = "slave-kernel"; 222 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 }; 226 }; 227 228 smp2p-wcnss { 229 compatible = "qcom,smp2p"; 230 qcom,smem = <451>, <431>; 231 232 interrupt-parent = <&intc>; 233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 234 235 qcom,ipc = <&apcs 8 18>; 236 237 qcom,local-pid = <0>; 238 qcom,remote-pid = <4>; 239 240 wcnss_smp2p_out: master-kernel { 241 qcom,entry-name = "master-kernel"; 242 243 #qcom,smem-state-cells = <1>; 244 }; 245 246 wcnss_smp2p_in: slave-kernel { 247 qcom,entry-name = "slave-kernel"; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 }; 253 254 smsm { 255 compatible = "qcom,smsm"; 256 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 qcom,ipc-1 = <&apcs 8 13>; 261 qcom,ipc-2 = <&apcs 8 9>; 262 qcom,ipc-3 = <&apcs 8 19>; 263 264 apps_smsm: apps@0 { 265 reg = <0>; 266 267 #qcom,smem-state-cells = <1>; 268 }; 269 270 modem_smsm: modem@1 { 271 reg = <1>; 272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 273 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 }; 277 278 adsp_smsm: adsp@2 { 279 reg = <2>; 280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 281 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 }; 285 286 wcnss_smsm: wcnss@7 { 287 reg = <7>; 288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 289 290 interrupt-controller; 291 #interrupt-cells = <2>; 292 }; 293 }; 294 295 smd { 296 compatible = "qcom,smd"; 297 298 rpm { 299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 300 qcom,ipc = <&apcs 8 0>; 301 qcom,smd-edge = <15>; 302 303 rpm_requests: rpm_requests { 304 compatible = "qcom,rpm-msm8974"; 305 qcom,smd-channels = "rpm_requests"; 306 307 rpmcc: clock-controller { 308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 309 #clock-cells = <1>; 310 clocks = <&xo_board>; 311 clock-names = "xo"; 312 }; 313 }; 314 }; 315 }; 316 317 soc: soc { 318 #address-cells = <1>; 319 #size-cells = <1>; 320 ranges; 321 compatible = "simple-bus"; 322 323 intc: interrupt-controller@f9000000 { 324 compatible = "qcom,msm-qgic2"; 325 interrupt-controller; 326 #interrupt-cells = <3>; 327 reg = <0xf9000000 0x1000>, 328 <0xf9002000 0x1000>; 329 }; 330 331 apcs: syscon@f9011000 { 332 compatible = "syscon"; 333 reg = <0xf9011000 0x1000>; 334 }; 335 336 timer@f9020000 { 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges; 340 compatible = "arm,armv7-timer-mem"; 341 reg = <0xf9020000 0x1000>; 342 clock-frequency = <19200000>; 343 344 frame@f9021000 { 345 frame-number = <0>; 346 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 348 reg = <0xf9021000 0x1000>, 349 <0xf9022000 0x1000>; 350 }; 351 352 frame@f9023000 { 353 frame-number = <1>; 354 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 355 reg = <0xf9023000 0x1000>; 356 status = "disabled"; 357 }; 358 359 frame@f9024000 { 360 frame-number = <2>; 361 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 362 reg = <0xf9024000 0x1000>; 363 status = "disabled"; 364 }; 365 366 frame@f9025000 { 367 frame-number = <3>; 368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 369 reg = <0xf9025000 0x1000>; 370 status = "disabled"; 371 }; 372 373 frame@f9026000 { 374 frame-number = <4>; 375 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 376 reg = <0xf9026000 0x1000>; 377 status = "disabled"; 378 }; 379 380 frame@f9027000 { 381 frame-number = <5>; 382 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 383 reg = <0xf9027000 0x1000>; 384 status = "disabled"; 385 }; 386 387 frame@f9028000 { 388 frame-number = <6>; 389 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 390 reg = <0xf9028000 0x1000>; 391 status = "disabled"; 392 }; 393 }; 394 395 saw0: power-controller@f9089000 { 396 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 397 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 398 }; 399 400 saw1: power-controller@f9099000 { 401 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 402 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 403 }; 404 405 saw2: power-controller@f90a9000 { 406 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 407 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 408 }; 409 410 saw3: power-controller@f90b9000 { 411 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 412 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 413 }; 414 415 saw_l2: power-controller@f9012000 { 416 compatible = "qcom,saw2"; 417 reg = <0xf9012000 0x1000>; 418 regulator; 419 }; 420 421 acc0: clock-controller@f9088000 { 422 compatible = "qcom,kpss-acc-v2"; 423 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 424 }; 425 426 acc1: clock-controller@f9098000 { 427 compatible = "qcom,kpss-acc-v2"; 428 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 429 }; 430 431 acc2: clock-controller@f90a8000 { 432 compatible = "qcom,kpss-acc-v2"; 433 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 434 }; 435 436 acc3: clock-controller@f90b8000 { 437 compatible = "qcom,kpss-acc-v2"; 438 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 439 }; 440 441 sdhc_1: mmc@f9824900 { 442 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 443 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 444 reg-names = "hc", "core"; 445 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "hc_irq", "pwr_irq"; 448 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 449 <&gcc GCC_SDCC1_APPS_CLK>, 450 <&xo_board>; 451 clock-names = "iface", "core", "xo"; 452 bus-width = <8>; 453 non-removable; 454 455 status = "disabled"; 456 }; 457 458 sdhc_3: mmc@f9864900 { 459 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 460 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 461 reg-names = "hc", "core"; 462 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "hc_irq", "pwr_irq"; 465 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 466 <&gcc GCC_SDCC3_APPS_CLK>, 467 <&xo_board>; 468 clock-names = "iface", "core", "xo"; 469 bus-width = <4>; 470 471 #address-cells = <1>; 472 #size-cells = <0>; 473 474 status = "disabled"; 475 }; 476 477 sdhc_2: mmc@f98a4900 { 478 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 479 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 480 reg-names = "hc", "core"; 481 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "hc_irq", "pwr_irq"; 484 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 485 <&gcc GCC_SDCC2_APPS_CLK>, 486 <&xo_board>; 487 clock-names = "iface", "core", "xo"; 488 bus-width = <4>; 489 490 #address-cells = <1>; 491 #size-cells = <0>; 492 493 status = "disabled"; 494 }; 495 496 blsp1_uart1: serial@f991d000 { 497 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 498 reg = <0xf991d000 0x1000>; 499 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 501 clock-names = "core", "iface"; 502 status = "disabled"; 503 }; 504 505 blsp1_uart2: serial@f991e000 { 506 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 507 reg = <0xf991e000 0x1000>; 508 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 510 clock-names = "core", "iface"; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&blsp1_uart2_default>; 513 status = "disabled"; 514 }; 515 516 blsp1_i2c1: i2c@f9923000 { 517 status = "disabled"; 518 compatible = "qcom,i2c-qup-v2.1.1"; 519 reg = <0xf9923000 0x1000>; 520 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 522 clock-names = "core", "iface"; 523 pinctrl-names = "default", "sleep"; 524 pinctrl-0 = <&blsp1_i2c1_default>; 525 pinctrl-1 = <&blsp1_i2c1_sleep>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 }; 529 530 blsp1_i2c2: i2c@f9924000 { 531 status = "disabled"; 532 compatible = "qcom,i2c-qup-v2.1.1"; 533 reg = <0xf9924000 0x1000>; 534 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 536 clock-names = "core", "iface"; 537 pinctrl-names = "default", "sleep"; 538 pinctrl-0 = <&blsp1_i2c2_default>; 539 pinctrl-1 = <&blsp1_i2c2_sleep>; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 }; 543 544 blsp1_i2c3: i2c@f9925000 { 545 status = "disabled"; 546 compatible = "qcom,i2c-qup-v2.1.1"; 547 reg = <0xf9925000 0x1000>; 548 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 550 clock-names = "core", "iface"; 551 pinctrl-names = "default", "sleep"; 552 pinctrl-0 = <&blsp1_i2c3_default>; 553 pinctrl-1 = <&blsp1_i2c3_sleep>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 558 blsp1_i2c6: i2c@f9928000 { 559 status = "disabled"; 560 compatible = "qcom,i2c-qup-v2.1.1"; 561 reg = <0xf9928000 0x1000>; 562 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 564 clock-names = "core", "iface"; 565 pinctrl-names = "default", "sleep"; 566 pinctrl-0 = <&blsp1_i2c6_default>; 567 pinctrl-1 = <&blsp1_i2c6_sleep>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 }; 571 572 blsp2_dma: dma-controller@f9944000 { 573 compatible = "qcom,bam-v1.4.0"; 574 reg = <0xf9944000 0x19000>; 575 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 577 clock-names = "bam_clk"; 578 #dma-cells = <1>; 579 qcom,ee = <0>; 580 }; 581 582 blsp2_uart1: serial@f995d000 { 583 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 584 reg = <0xf995d000 0x1000>; 585 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 587 clock-names = "core", "iface"; 588 pinctrl-names = "default", "sleep"; 589 pinctrl-0 = <&blsp2_uart1_default>; 590 pinctrl-1 = <&blsp2_uart1_sleep>; 591 status = "disabled"; 592 }; 593 594 blsp2_uart2: serial@f995e000 { 595 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 596 reg = <0xf995e000 0x1000>; 597 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 599 clock-names = "core", "iface"; 600 status = "disabled"; 601 }; 602 603 blsp2_uart4: serial@f9960000 { 604 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 605 reg = <0xf9960000 0x1000>; 606 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 608 clock-names = "core", "iface"; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&blsp2_uart4_default>; 611 status = "disabled"; 612 }; 613 614 blsp2_i2c2: i2c@f9964000 { 615 status = "disabled"; 616 compatible = "qcom,i2c-qup-v2.1.1"; 617 reg = <0xf9964000 0x1000>; 618 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 620 clock-names = "core", "iface"; 621 pinctrl-names = "default", "sleep"; 622 pinctrl-0 = <&blsp2_i2c2_default>; 623 pinctrl-1 = <&blsp2_i2c2_sleep>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 }; 627 628 blsp2_i2c5: i2c@f9967000 { 629 status = "disabled"; 630 compatible = "qcom,i2c-qup-v2.1.1"; 631 reg = <0xf9967000 0x1000>; 632 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 634 clock-names = "core", "iface"; 635 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 636 dma-names = "tx", "rx"; 637 pinctrl-names = "default", "sleep"; 638 pinctrl-0 = <&blsp2_i2c5_default>; 639 pinctrl-1 = <&blsp2_i2c5_sleep>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 }; 643 644 blsp2_i2c6: i2c@f9968000 { 645 status = "disabled"; 646 compatible = "qcom,i2c-qup-v2.1.1"; 647 reg = <0xf9968000 0x1000>; 648 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 650 clock-names = "core", "iface"; 651 pinctrl-names = "default", "sleep"; 652 pinctrl-0 = <&blsp2_i2c6_default>; 653 pinctrl-1 = <&blsp2_i2c6_sleep>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 }; 657 658 usb: usb@f9a55000 { 659 compatible = "qcom,ci-hdrc"; 660 reg = <0xf9a55000 0x200>, 661 <0xf9a55200 0x200>; 662 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 664 <&gcc GCC_USB_HS_SYSTEM_CLK>; 665 clock-names = "iface", "core"; 666 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 667 assigned-clock-rates = <75000000>; 668 resets = <&gcc GCC_USB_HS_BCR>; 669 reset-names = "core"; 670 phy_type = "ulpi"; 671 dr_mode = "otg"; 672 ahb-burst-config = <0>; 673 phy-names = "usb-phy"; 674 status = "disabled"; 675 #reset-cells = <1>; 676 677 ulpi { 678 usb_hs1_phy: phy@a { 679 compatible = "qcom,usb-hs-phy-msm8974", 680 "qcom,usb-hs-phy"; 681 #phy-cells = <0>; 682 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 683 clock-names = "ref", "sleep"; 684 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 685 reset-names = "phy", "por"; 686 status = "disabled"; 687 }; 688 689 usb_hs2_phy: phy@b { 690 compatible = "qcom,usb-hs-phy-msm8974", 691 "qcom,usb-hs-phy"; 692 #phy-cells = <0>; 693 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 694 clock-names = "ref", "sleep"; 695 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>; 696 reset-names = "phy", "por"; 697 status = "disabled"; 698 }; 699 }; 700 }; 701 702 rng@f9bff000 { 703 compatible = "qcom,prng"; 704 reg = <0xf9bff000 0x200>; 705 clocks = <&gcc GCC_PRNG_AHB_CLK>; 706 clock-names = "core"; 707 }; 708 709 pronto: remoteproc@fb21b000 { 710 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 711 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 712 reg-names = "ccu", "dxe", "pmu"; 713 714 memory-region = <&wcnss_region>; 715 716 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 717 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 718 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 719 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 720 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 721 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 722 723 qcom,smem-states = <&wcnss_smp2p_out 0>; 724 qcom,smem-state-names = "stop"; 725 726 status = "disabled"; 727 728 iris { 729 compatible = "qcom,wcn3680"; 730 731 clocks = <&rpmcc RPM_SMD_CXO_A2>; 732 clock-names = "xo"; 733 }; 734 735 smd-edge { 736 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 737 738 qcom,ipc = <&apcs 8 17>; 739 qcom,smd-edge = <6>; 740 741 wcnss { 742 compatible = "qcom,wcnss"; 743 qcom,smd-channels = "WCNSS_CTRL"; 744 status = "disabled"; 745 746 qcom,mmio = <&pronto>; 747 748 bt { 749 compatible = "qcom,wcnss-bt"; 750 }; 751 752 wifi { 753 compatible = "qcom,wcnss-wlan"; 754 755 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 756 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 757 interrupt-names = "tx", "rx"; 758 759 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 760 qcom,smem-state-names = "tx-enable", 761 "tx-rings-empty"; 762 }; 763 }; 764 }; 765 }; 766 767 sram@fc190000 { 768 compatible = "qcom,msm8974-rpm-stats"; 769 reg = <0xfc190000 0x10000>; 770 }; 771 772 etf@fc307000 { 773 compatible = "arm,coresight-tmc", "arm,primecell"; 774 reg = <0xfc307000 0x1000>; 775 776 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 777 clock-names = "apb_pclk", "atclk"; 778 779 out-ports { 780 port { 781 etf_out: endpoint { 782 remote-endpoint = <&replicator_in>; 783 }; 784 }; 785 }; 786 787 in-ports { 788 port { 789 etf_in: endpoint { 790 remote-endpoint = <&merger_out>; 791 }; 792 }; 793 }; 794 }; 795 796 tpiu@fc318000 { 797 compatible = "arm,coresight-tpiu", "arm,primecell"; 798 reg = <0xfc318000 0x1000>; 799 800 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 801 clock-names = "apb_pclk", "atclk"; 802 803 in-ports { 804 port { 805 tpiu_in: endpoint { 806 remote-endpoint = <&replicator_out1>; 807 }; 808 }; 809 }; 810 }; 811 812 funnel@fc31a000 { 813 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 814 reg = <0xfc31a000 0x1000>; 815 816 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 817 clock-names = "apb_pclk", "atclk"; 818 819 in-ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 /* 824 * Not described input ports: 825 * 0 - not-connected 826 * 1 - connected trought funnel to Multimedia CPU 827 * 2 - connected to Wireless CPU 828 * 3 - not-connected 829 * 4 - not-connected 830 * 6 - not-connected 831 * 7 - connected to STM 832 */ 833 port@5 { 834 reg = <5>; 835 funnel1_in5: endpoint { 836 remote-endpoint = <&kpss_out>; 837 }; 838 }; 839 }; 840 841 out-ports { 842 port { 843 funnel1_out: endpoint { 844 remote-endpoint = <&merger_in1>; 845 }; 846 }; 847 }; 848 }; 849 850 funnel@fc31b000 { 851 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 852 reg = <0xfc31b000 0x1000>; 853 854 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 855 clock-names = "apb_pclk", "atclk"; 856 857 in-ports { 858 #address-cells = <1>; 859 #size-cells = <0>; 860 861 /* 862 * Not described input ports: 863 * 0 - connected trought funnel to Audio, Modem and 864 * Resource and Power Manager CPU's 865 * 2...7 - not-connected 866 */ 867 port@1 { 868 reg = <1>; 869 merger_in1: endpoint { 870 remote-endpoint = <&funnel1_out>; 871 }; 872 }; 873 }; 874 875 out-ports { 876 port { 877 merger_out: endpoint { 878 remote-endpoint = <&etf_in>; 879 }; 880 }; 881 }; 882 }; 883 884 replicator@fc31c000 { 885 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 886 reg = <0xfc31c000 0x1000>; 887 888 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 889 clock-names = "apb_pclk", "atclk"; 890 891 out-ports { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 port@0 { 896 reg = <0>; 897 replicator_out0: endpoint { 898 remote-endpoint = <&etr_in>; 899 }; 900 }; 901 port@1 { 902 reg = <1>; 903 replicator_out1: endpoint { 904 remote-endpoint = <&tpiu_in>; 905 }; 906 }; 907 }; 908 909 in-ports { 910 port { 911 replicator_in: endpoint { 912 remote-endpoint = <&etf_out>; 913 }; 914 }; 915 }; 916 }; 917 918 etr@fc322000 { 919 compatible = "arm,coresight-tmc", "arm,primecell"; 920 reg = <0xfc322000 0x1000>; 921 922 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 923 clock-names = "apb_pclk", "atclk"; 924 925 in-ports { 926 port { 927 etr_in: endpoint { 928 remote-endpoint = <&replicator_out0>; 929 }; 930 }; 931 }; 932 }; 933 934 etm@fc33c000 { 935 compatible = "arm,coresight-etm4x", "arm,primecell"; 936 reg = <0xfc33c000 0x1000>; 937 938 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 939 clock-names = "apb_pclk", "atclk"; 940 941 cpu = <&CPU0>; 942 943 out-ports { 944 port { 945 etm0_out: endpoint { 946 remote-endpoint = <&kpss_in0>; 947 }; 948 }; 949 }; 950 }; 951 952 etm@fc33d000 { 953 compatible = "arm,coresight-etm4x", "arm,primecell"; 954 reg = <0xfc33d000 0x1000>; 955 956 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 957 clock-names = "apb_pclk", "atclk"; 958 959 cpu = <&CPU1>; 960 961 out-ports { 962 port { 963 etm1_out: endpoint { 964 remote-endpoint = <&kpss_in1>; 965 }; 966 }; 967 }; 968 }; 969 970 etm@fc33e000 { 971 compatible = "arm,coresight-etm4x", "arm,primecell"; 972 reg = <0xfc33e000 0x1000>; 973 974 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 975 clock-names = "apb_pclk", "atclk"; 976 977 cpu = <&CPU2>; 978 979 out-ports { 980 port { 981 etm2_out: endpoint { 982 remote-endpoint = <&kpss_in2>; 983 }; 984 }; 985 }; 986 }; 987 988 etm@fc33f000 { 989 compatible = "arm,coresight-etm4x", "arm,primecell"; 990 reg = <0xfc33f000 0x1000>; 991 992 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 993 clock-names = "apb_pclk", "atclk"; 994 995 cpu = <&CPU3>; 996 997 out-ports { 998 port { 999 etm3_out: endpoint { 1000 remote-endpoint = <&kpss_in3>; 1001 }; 1002 }; 1003 }; 1004 }; 1005 1006 /* KPSS funnel, only 4 inputs are used */ 1007 funnel@fc345000 { 1008 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1009 reg = <0xfc345000 0x1000>; 1010 1011 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1012 clock-names = "apb_pclk", "atclk"; 1013 1014 in-ports { 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 1018 port@0 { 1019 reg = <0>; 1020 kpss_in0: endpoint { 1021 remote-endpoint = <&etm0_out>; 1022 }; 1023 }; 1024 port@1 { 1025 reg = <1>; 1026 kpss_in1: endpoint { 1027 remote-endpoint = <&etm1_out>; 1028 }; 1029 }; 1030 port@2 { 1031 reg = <2>; 1032 kpss_in2: endpoint { 1033 remote-endpoint = <&etm2_out>; 1034 }; 1035 }; 1036 port@3 { 1037 reg = <3>; 1038 kpss_in3: endpoint { 1039 remote-endpoint = <&etm3_out>; 1040 }; 1041 }; 1042 }; 1043 1044 out-ports { 1045 port { 1046 kpss_out: endpoint { 1047 remote-endpoint = <&funnel1_in5>; 1048 }; 1049 }; 1050 }; 1051 }; 1052 1053 gcc: clock-controller@fc400000 { 1054 compatible = "qcom,gcc-msm8974"; 1055 #clock-cells = <1>; 1056 #reset-cells = <1>; 1057 #power-domain-cells = <1>; 1058 reg = <0xfc400000 0x4000>; 1059 1060 clocks = <&xo_board>, 1061 <&sleep_clk>; 1062 clock-names = "xo", 1063 "sleep_clk"; 1064 }; 1065 1066 rpm_msg_ram: sram@fc428000 { 1067 compatible = "qcom,rpm-msg-ram"; 1068 reg = <0xfc428000 0x4000>; 1069 }; 1070 1071 bimc: interconnect@fc380000 { 1072 reg = <0xfc380000 0x6a000>; 1073 compatible = "qcom,msm8974-bimc"; 1074 #interconnect-cells = <1>; 1075 clock-names = "bus", "bus_a"; 1076 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1077 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1078 }; 1079 1080 snoc: interconnect@fc460000 { 1081 reg = <0xfc460000 0x4000>; 1082 compatible = "qcom,msm8974-snoc"; 1083 #interconnect-cells = <1>; 1084 clock-names = "bus", "bus_a"; 1085 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1086 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1087 }; 1088 1089 pnoc: interconnect@fc468000 { 1090 reg = <0xfc468000 0x4000>; 1091 compatible = "qcom,msm8974-pnoc"; 1092 #interconnect-cells = <1>; 1093 clock-names = "bus", "bus_a"; 1094 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1095 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1096 }; 1097 1098 ocmemnoc: interconnect@fc470000 { 1099 reg = <0xfc470000 0x4000>; 1100 compatible = "qcom,msm8974-ocmemnoc"; 1101 #interconnect-cells = <1>; 1102 clock-names = "bus", "bus_a"; 1103 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1104 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1105 }; 1106 1107 mmssnoc: interconnect@fc478000 { 1108 reg = <0xfc478000 0x4000>; 1109 compatible = "qcom,msm8974-mmssnoc"; 1110 #interconnect-cells = <1>; 1111 clock-names = "bus", "bus_a"; 1112 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1113 <&mmcc MMSS_S0_AXI_CLK>; 1114 }; 1115 1116 cnoc: interconnect@fc480000 { 1117 reg = <0xfc480000 0x4000>; 1118 compatible = "qcom,msm8974-cnoc"; 1119 #interconnect-cells = <1>; 1120 clock-names = "bus", "bus_a"; 1121 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1122 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1123 }; 1124 1125 tsens: thermal-sensor@fc4a9000 { 1126 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; 1127 reg = <0xfc4a9000 0x1000>, /* TM */ 1128 <0xfc4a8000 0x1000>; /* SROT */ 1129 nvmem-cells = <&tsens_mode>, 1130 <&tsens_base1>, <&tsens_base2>, 1131 <&tsens_use_backup>, 1132 <&tsens_mode_backup>, 1133 <&tsens_base1_backup>, <&tsens_base2_backup>, 1134 <&tsens_s0_p1>, <&tsens_s0_p2>, 1135 <&tsens_s1_p1>, <&tsens_s1_p2>, 1136 <&tsens_s2_p1>, <&tsens_s2_p2>, 1137 <&tsens_s3_p1>, <&tsens_s3_p2>, 1138 <&tsens_s4_p1>, <&tsens_s4_p2>, 1139 <&tsens_s5_p1>, <&tsens_s5_p2>, 1140 <&tsens_s6_p1>, <&tsens_s6_p2>, 1141 <&tsens_s7_p1>, <&tsens_s7_p2>, 1142 <&tsens_s8_p1>, <&tsens_s8_p2>, 1143 <&tsens_s9_p1>, <&tsens_s9_p2>, 1144 <&tsens_s10_p1>, <&tsens_s10_p2>, 1145 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, 1146 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, 1147 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, 1148 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, 1149 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, 1150 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, 1151 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, 1152 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, 1153 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, 1154 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, 1155 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; 1156 nvmem-cell-names = "mode", 1157 "base1", "base2", 1158 "use_backup", 1159 "mode_backup", 1160 "base1_backup", "base2_backup", 1161 "s0_p1", "s0_p2", 1162 "s1_p1", "s1_p2", 1163 "s2_p1", "s2_p2", 1164 "s3_p1", "s3_p2", 1165 "s4_p1", "s4_p2", 1166 "s5_p1", "s5_p2", 1167 "s6_p1", "s6_p2", 1168 "s7_p1", "s7_p2", 1169 "s8_p1", "s8_p2", 1170 "s9_p1", "s9_p2", 1171 "s10_p1", "s10_p2", 1172 "s0_p1_backup", "s0_p2_backup", 1173 "s1_p1_backup", "s1_p2_backup", 1174 "s2_p1_backup", "s2_p2_backup", 1175 "s3_p1_backup", "s3_p2_backup", 1176 "s4_p1_backup", "s4_p2_backup", 1177 "s5_p1_backup", "s5_p2_backup", 1178 "s6_p1_backup", "s6_p2_backup", 1179 "s7_p1_backup", "s7_p2_backup", 1180 "s8_p1_backup", "s8_p2_backup", 1181 "s9_p1_backup", "s9_p2_backup", 1182 "s10_p1_backup", "s10_p2_backup"; 1183 #qcom,sensors = <11>; 1184 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1185 interrupt-names = "uplow"; 1186 #thermal-sensor-cells = <1>; 1187 }; 1188 1189 restart@fc4ab000 { 1190 compatible = "qcom,pshold"; 1191 reg = <0xfc4ab000 0x4>; 1192 }; 1193 1194 qfprom: qfprom@fc4bc000 { 1195 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1196 reg = <0xfc4bc000 0x1000>; 1197 #address-cells = <1>; 1198 #size-cells = <1>; 1199 1200 tsens_base1: base1@d0 { 1201 reg = <0xd0 0x1>; 1202 bits = <0 8>; 1203 }; 1204 1205 tsens_s0_p1: s0-p1@d1 { 1206 reg = <0xd1 0x1>; 1207 bits = <0 6>; 1208 }; 1209 1210 tsens_s1_p1: s1-p1@d2 { 1211 reg = <0xd1 0x2>; 1212 bits = <6 6>; 1213 }; 1214 1215 tsens_s2_p1: s2-p1@d2 { 1216 reg = <0xd2 0x2>; 1217 bits = <4 6>; 1218 }; 1219 1220 tsens_s3_p1: s3-p1@d3 { 1221 reg = <0xd3 0x1>; 1222 bits = <2 6>; 1223 }; 1224 1225 tsens_s4_p1: s4-p1@d4 { 1226 reg = <0xd4 0x1>; 1227 bits = <0 6>; 1228 }; 1229 1230 tsens_s5_p1: s5-p1@d4 { 1231 reg = <0xd4 0x2>; 1232 bits = <6 6>; 1233 }; 1234 1235 tsens_s6_p1: s6-p1@d5 { 1236 reg = <0xd5 0x2>; 1237 bits = <4 6>; 1238 }; 1239 1240 tsens_s7_p1: s7-p1@d6 { 1241 reg = <0xd6 0x1>; 1242 bits = <2 6>; 1243 }; 1244 1245 tsens_s8_p1: s8-p1@d7 { 1246 reg = <0xd7 0x1>; 1247 bits = <0 6>; 1248 }; 1249 1250 tsens_mode: mode@d7 { 1251 reg = <0xd7 0x1>; 1252 bits = <6 2>; 1253 }; 1254 1255 tsens_s9_p1: s9-p1@d8 { 1256 reg = <0xd8 0x1>; 1257 bits = <0 6>; 1258 }; 1259 1260 tsens_s10_p1: s10_p1@d8 { 1261 reg = <0xd8 0x2>; 1262 bits = <6 6>; 1263 }; 1264 1265 tsens_base2: base2@d9 { 1266 reg = <0xd9 0x2>; 1267 bits = <4 8>; 1268 }; 1269 1270 tsens_s0_p2: s0-p2@da { 1271 reg = <0xda 0x2>; 1272 bits = <4 6>; 1273 }; 1274 1275 tsens_s1_p2: s1-p2@db { 1276 reg = <0xdb 0x1>; 1277 bits = <2 6>; 1278 }; 1279 1280 tsens_s2_p2: s2-p2@dc { 1281 reg = <0xdc 0x1>; 1282 bits = <0 6>; 1283 }; 1284 1285 tsens_s3_p2: s3-p2@dc { 1286 reg = <0xdc 0x2>; 1287 bits = <6 6>; 1288 }; 1289 1290 tsens_s4_p2: s4-p2@dd { 1291 reg = <0xdd 0x2>; 1292 bits = <4 6>; 1293 }; 1294 1295 tsens_s5_p2: s5-p2@de { 1296 reg = <0xde 0x2>; 1297 bits = <2 6>; 1298 }; 1299 1300 tsens_s6_p2: s6-p2@df { 1301 reg = <0xdf 0x1>; 1302 bits = <0 6>; 1303 }; 1304 1305 tsens_s7_p2: s7-p2@e0 { 1306 reg = <0xe0 0x1>; 1307 bits = <0 6>; 1308 }; 1309 1310 tsens_s8_p2: s8-p2@e0 { 1311 reg = <0xe0 0x2>; 1312 bits = <6 6>; 1313 }; 1314 1315 tsens_s9_p2: s9-p2@e1 { 1316 reg = <0xe1 0x2>; 1317 bits = <4 6>; 1318 }; 1319 1320 tsens_s10_p2: s10_p2@e2 { 1321 reg = <0xe2 0x2>; 1322 bits = <2 6>; 1323 }; 1324 1325 tsens_s5_p2_backup: s5-p2_backup@e3 { 1326 reg = <0xe3 0x2>; 1327 bits = <0 6>; 1328 }; 1329 1330 tsens_mode_backup: mode_backup@e3 { 1331 reg = <0xe3 0x1>; 1332 bits = <6 2>; 1333 }; 1334 1335 tsens_s6_p2_backup: s6-p2_backup@e4 { 1336 reg = <0xe4 0x1>; 1337 bits = <0 6>; 1338 }; 1339 1340 tsens_s7_p2_backup: s7-p2_backup@e4 { 1341 reg = <0xe4 0x2>; 1342 bits = <6 6>; 1343 }; 1344 1345 tsens_s8_p2_backup: s8-p2_backup@e5 { 1346 reg = <0xe5 0x2>; 1347 bits = <4 6>; 1348 }; 1349 1350 tsens_s9_p2_backup: s9-p2_backup@e6 { 1351 reg = <0xe6 0x2>; 1352 bits = <2 6>; 1353 }; 1354 1355 tsens_s10_p2_backup: s10_p2_backup@e7 { 1356 reg = <0xe7 0x1>; 1357 bits = <0 6>; 1358 }; 1359 1360 tsens_base1_backup: base1_backup@440 { 1361 reg = <0x440 0x1>; 1362 bits = <0 8>; 1363 }; 1364 1365 tsens_s0_p1_backup: s0-p1_backup@441 { 1366 reg = <0x441 0x1>; 1367 bits = <0 6>; 1368 }; 1369 1370 tsens_s1_p1_backup: s1-p1_backup@442 { 1371 reg = <0x441 0x2>; 1372 bits = <6 6>; 1373 }; 1374 1375 tsens_s2_p1_backup: s2-p1_backup@442 { 1376 reg = <0x442 0x2>; 1377 bits = <4 6>; 1378 }; 1379 1380 tsens_s3_p1_backup: s3-p1_backup@443 { 1381 reg = <0x443 0x1>; 1382 bits = <2 6>; 1383 }; 1384 1385 tsens_s4_p1_backup: s4-p1_backup@444 { 1386 reg = <0x444 0x1>; 1387 bits = <0 6>; 1388 }; 1389 1390 tsens_s5_p1_backup: s5-p1_backup@444 { 1391 reg = <0x444 0x2>; 1392 bits = <6 6>; 1393 }; 1394 1395 tsens_s6_p1_backup: s6-p1_backup@445 { 1396 reg = <0x445 0x2>; 1397 bits = <4 6>; 1398 }; 1399 1400 tsens_s7_p1_backup: s7-p1_backup@446 { 1401 reg = <0x446 0x1>; 1402 bits = <2 6>; 1403 }; 1404 1405 tsens_use_backup: use_backup@447 { 1406 reg = <0x447 0x1>; 1407 bits = <5 3>; 1408 }; 1409 1410 tsens_s8_p1_backup: s8-p1_backup@448 { 1411 reg = <0x448 0x1>; 1412 bits = <0 6>; 1413 }; 1414 1415 tsens_s9_p1_backup: s9-p1_backup@448 { 1416 reg = <0x448 0x2>; 1417 bits = <6 6>; 1418 }; 1419 1420 tsens_s10_p1_backup: s10_p1_backup@449 { 1421 reg = <0x449 0x2>; 1422 bits = <4 6>; 1423 }; 1424 1425 tsens_base2_backup: base2_backup@44a { 1426 reg = <0x44a 0x2>; 1427 bits = <2 8>; 1428 }; 1429 1430 tsens_s0_p2_backup: s0-p2_backup@44b { 1431 reg = <0x44b 0x3>; 1432 bits = <2 6>; 1433 }; 1434 1435 tsens_s1_p2_backup: s1-p2_backup@44c { 1436 reg = <0x44c 0x1>; 1437 bits = <0 6>; 1438 }; 1439 1440 tsens_s2_p2_backup: s2-p2_backup@44c { 1441 reg = <0x44c 0x2>; 1442 bits = <6 6>; 1443 }; 1444 1445 tsens_s3_p2_backup: s3-p2_backup@44d { 1446 reg = <0x44d 0x2>; 1447 bits = <4 6>; 1448 }; 1449 1450 tsens_s4_p2_backup: s4-p2_backup@44e { 1451 reg = <0x44e 0x1>; 1452 bits = <2 6>; 1453 }; 1454 }; 1455 1456 spmi_bus: spmi@fc4cf000 { 1457 compatible = "qcom,spmi-pmic-arb"; 1458 reg-names = "core", "intr", "cnfg"; 1459 reg = <0xfc4cf000 0x1000>, 1460 <0xfc4cb000 0x1000>, 1461 <0xfc4ca000 0x1000>; 1462 interrupt-names = "periph_irq"; 1463 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1464 qcom,ee = <0>; 1465 qcom,channel = <0>; 1466 #address-cells = <2>; 1467 #size-cells = <0>; 1468 interrupt-controller; 1469 #interrupt-cells = <4>; 1470 }; 1471 1472 bam_dmux_dma: dma-controller@fc834000 { 1473 compatible = "qcom,bam-v1.4.0"; 1474 reg = <0xfc834000 0x7000>; 1475 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1476 #dma-cells = <1>; 1477 qcom,ee = <0>; 1478 1479 num-channels = <6>; 1480 qcom,num-ees = <1>; 1481 qcom,powered-remotely; 1482 }; 1483 1484 remoteproc_mss: remoteproc@fc880000 { 1485 compatible = "qcom,msm8974-mss-pil"; 1486 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1487 reg-names = "qdsp6", "rmb"; 1488 1489 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1490 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1491 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1492 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1493 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1494 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1495 1496 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1497 <&gcc GCC_MSS_CFG_AHB_CLK>, 1498 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1499 <&xo_board>; 1500 clock-names = "iface", "bus", "mem", "xo"; 1501 1502 resets = <&gcc GCC_MSS_RESTART>; 1503 reset-names = "mss_restart"; 1504 1505 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; 1506 1507 qcom,smem-states = <&modem_smp2p_out 0>; 1508 qcom,smem-state-names = "stop"; 1509 1510 status = "disabled"; 1511 1512 mba { 1513 memory-region = <&mba_region>; 1514 }; 1515 1516 mpss { 1517 memory-region = <&mpss_region>; 1518 }; 1519 1520 bam_dmux: bam-dmux { 1521 compatible = "qcom,bam-dmux"; 1522 1523 interrupt-parent = <&modem_smsm>; 1524 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1525 interrupt-names = "pc", "pc-ack"; 1526 1527 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1528 qcom,smem-state-names = "pc", "pc-ack"; 1529 1530 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1531 dma-names = "tx", "rx"; 1532 }; 1533 1534 smd-edge { 1535 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1536 1537 qcom,ipc = <&apcs 8 12>; 1538 qcom,smd-edge = <0>; 1539 1540 label = "modem"; 1541 }; 1542 }; 1543 1544 tcsr_mutex: hwlock@fd484000 { 1545 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon"; 1546 reg = <0xfd484000 0x2000>; 1547 #hwlock-cells = <1>; 1548 }; 1549 1550 tcsr: syscon@fd4a0000 { 1551 compatible = "qcom,tcsr-msm8974", "syscon"; 1552 reg = <0xfd4a0000 0x10000>; 1553 }; 1554 1555 tlmm: pinctrl@fd510000 { 1556 compatible = "qcom,msm8974-pinctrl"; 1557 reg = <0xfd510000 0x4000>; 1558 gpio-controller; 1559 gpio-ranges = <&tlmm 0 0 146>; 1560 #gpio-cells = <2>; 1561 interrupt-controller; 1562 #interrupt-cells = <2>; 1563 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1564 1565 sdc1_off: sdc1-off-state { 1566 clk-pins { 1567 pins = "sdc1_clk"; 1568 bias-disable; 1569 drive-strength = <2>; 1570 }; 1571 1572 cmd-pins { 1573 pins = "sdc1_cmd"; 1574 bias-pull-up; 1575 drive-strength = <2>; 1576 }; 1577 1578 data-pins { 1579 pins = "sdc1_data"; 1580 bias-pull-up; 1581 drive-strength = <2>; 1582 }; 1583 }; 1584 1585 sdc2_off: sdc2-off-state { 1586 clk-pins { 1587 pins = "sdc2_clk"; 1588 bias-disable; 1589 drive-strength = <2>; 1590 }; 1591 1592 cmd-pins { 1593 pins = "sdc2_cmd"; 1594 bias-pull-up; 1595 drive-strength = <2>; 1596 }; 1597 1598 data-pins { 1599 pins = "sdc2_data"; 1600 bias-pull-up; 1601 drive-strength = <2>; 1602 }; 1603 1604 cd-pins { 1605 pins = "gpio54"; 1606 function = "gpio"; 1607 bias-disable; 1608 drive-strength = <2>; 1609 }; 1610 }; 1611 1612 blsp1_uart2_default: blsp1-uart2-default-state { 1613 rx-pins { 1614 pins = "gpio5"; 1615 function = "blsp_uart2"; 1616 drive-strength = <2>; 1617 bias-pull-up; 1618 }; 1619 1620 tx-pins { 1621 pins = "gpio4"; 1622 function = "blsp_uart2"; 1623 drive-strength = <4>; 1624 bias-disable; 1625 }; 1626 }; 1627 1628 blsp2_uart1_default: blsp2-uart1-default-state { 1629 tx-rts-pins { 1630 pins = "gpio41", "gpio44"; 1631 function = "blsp_uart7"; 1632 drive-strength = <2>; 1633 bias-disable; 1634 }; 1635 1636 rx-cts-pins { 1637 pins = "gpio42", "gpio43"; 1638 function = "blsp_uart7"; 1639 drive-strength = <2>; 1640 bias-pull-up; 1641 }; 1642 }; 1643 1644 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 1645 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1646 function = "gpio"; 1647 drive-strength = <2>; 1648 bias-pull-down; 1649 }; 1650 1651 blsp2_uart4_default: blsp2-uart4-default-state { 1652 tx-rts-pins { 1653 pins = "gpio53", "gpio56"; 1654 function = "blsp_uart10"; 1655 drive-strength = <2>; 1656 bias-disable; 1657 }; 1658 1659 rx-cts-pins { 1660 pins = "gpio54", "gpio55"; 1661 function = "blsp_uart10"; 1662 drive-strength = <2>; 1663 bias-pull-up; 1664 }; 1665 }; 1666 1667 blsp1_i2c1_default: blsp1-i2c1-default-state { 1668 pins = "gpio2", "gpio3"; 1669 function = "blsp_i2c1"; 1670 drive-strength = <2>; 1671 bias-disable; 1672 }; 1673 1674 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state { 1675 pins = "gpio2", "gpio3"; 1676 function = "blsp_i2c1"; 1677 drive-strength = <2>; 1678 bias-pull-up; 1679 }; 1680 1681 blsp1_i2c2_default: blsp1-i2c2-default-state { 1682 pins = "gpio6", "gpio7"; 1683 function = "blsp_i2c2"; 1684 drive-strength = <2>; 1685 bias-disable; 1686 }; 1687 1688 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 1689 pins = "gpio6", "gpio7"; 1690 function = "blsp_i2c2"; 1691 drive-strength = <2>; 1692 bias-pull-up; 1693 }; 1694 1695 blsp1_i2c3_default: blsp1-i2c3-default-state { 1696 pins = "gpio10", "gpio11"; 1697 function = "blsp_i2c3"; 1698 drive-strength = <2>; 1699 bias-disable; 1700 }; 1701 1702 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1703 pins = "gpio10", "gpio11"; 1704 function = "blsp_i2c3"; 1705 drive-strength = <2>; 1706 bias-pull-up; 1707 }; 1708 1709 /* BLSP1_I2C4 info is missing */ 1710 1711 /* BLSP1_I2C5 info is missing */ 1712 1713 blsp1_i2c6_default: blsp1-i2c6-default-state { 1714 pins = "gpio29", "gpio30"; 1715 function = "blsp_i2c6"; 1716 drive-strength = <2>; 1717 bias-disable; 1718 }; 1719 1720 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1721 pins = "gpio29", "gpio30"; 1722 function = "blsp_i2c6"; 1723 drive-strength = <2>; 1724 bias-pull-up; 1725 }; 1726 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1727 1728 /* BLSP2_I2C1 info is missing */ 1729 1730 blsp2_i2c2_default: blsp2-i2c2-default-state { 1731 pins = "gpio47", "gpio48"; 1732 function = "blsp_i2c8"; 1733 drive-strength = <2>; 1734 bias-disable; 1735 }; 1736 1737 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1738 pins = "gpio47", "gpio48"; 1739 function = "blsp_i2c8"; 1740 drive-strength = <2>; 1741 bias-pull-up; 1742 }; 1743 1744 /* BLSP2_I2C3 info is missing */ 1745 1746 /* BLSP2_I2C4 info is missing */ 1747 1748 blsp2_i2c5_default: blsp2-i2c5-default-state { 1749 pins = "gpio83", "gpio84"; 1750 function = "blsp_i2c11"; 1751 drive-strength = <2>; 1752 bias-disable; 1753 }; 1754 1755 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1756 pins = "gpio83", "gpio84"; 1757 function = "blsp_i2c11"; 1758 drive-strength = <2>; 1759 bias-pull-up; 1760 }; 1761 1762 blsp2_i2c6_default: blsp2-i2c6-default-state { 1763 pins = "gpio87", "gpio88"; 1764 function = "blsp_i2c12"; 1765 drive-strength = <2>; 1766 bias-disable; 1767 }; 1768 1769 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1770 pins = "gpio87", "gpio88"; 1771 function = "blsp_i2c12"; 1772 drive-strength = <2>; 1773 bias-pull-up; 1774 }; 1775 1776 cci_default: cci-default-state { 1777 cci_i2c0_default: cci-i2c0-default-pins { 1778 pins = "gpio19", "gpio20"; 1779 function = "cci_i2c0"; 1780 drive-strength = <2>; 1781 bias-disable; 1782 }; 1783 1784 cci_i2c1_default: cci-i2c1-default-pins { 1785 pins = "gpio21", "gpio22"; 1786 function = "cci_i2c1"; 1787 drive-strength = <2>; 1788 bias-disable; 1789 }; 1790 }; 1791 1792 cci_sleep: cci-sleep-state { 1793 cci_i2c0_sleep: cci-i2c0-sleep-pins { 1794 pins = "gpio19", "gpio20"; 1795 function = "gpio"; 1796 drive-strength = <2>; 1797 bias-disable; 1798 }; 1799 1800 cci_i2c1_sleep: cci-i2c1-sleep-pins { 1801 pins = "gpio21", "gpio22"; 1802 function = "gpio"; 1803 drive-strength = <2>; 1804 bias-disable; 1805 }; 1806 }; 1807 1808 spi8_default: spi8_default-state { 1809 mosi-pins { 1810 pins = "gpio45"; 1811 function = "blsp_spi8"; 1812 }; 1813 miso-pins { 1814 pins = "gpio46"; 1815 function = "blsp_spi8"; 1816 }; 1817 cs-pins { 1818 pins = "gpio47"; 1819 function = "blsp_spi8"; 1820 }; 1821 clk-pins { 1822 pins = "gpio48"; 1823 function = "blsp_spi8"; 1824 }; 1825 }; 1826 }; 1827 1828 mmcc: clock-controller@fd8c0000 { 1829 compatible = "qcom,mmcc-msm8974"; 1830 #clock-cells = <1>; 1831 #reset-cells = <1>; 1832 #power-domain-cells = <1>; 1833 reg = <0xfd8c0000 0x6000>; 1834 clocks = <&xo_board>, 1835 <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 1836 <&gcc GPLL0_VOTE>, 1837 <&gcc GPLL1_VOTE>, 1838 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1839 <&dsi0_phy 1>, 1840 <&dsi0_phy 0>, 1841 <&dsi1_phy 1>, 1842 <&dsi1_phy 0>, 1843 <0>, 1844 <0>, 1845 <0>; 1846 clock-names = "xo", 1847 "mmss_gpll0_vote", 1848 "gpll0_vote", 1849 "gpll1_vote", 1850 "gfx3d_clk_src", 1851 "dsi0pll", 1852 "dsi0pllbyte", 1853 "dsi1pll", 1854 "dsi1pllbyte", 1855 "hdmipll", 1856 "edp_link_clk", 1857 "edp_vco_div"; 1858 }; 1859 1860 mdss: display-subsystem@fd900000 { 1861 compatible = "qcom,mdss"; 1862 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1863 reg-names = "mdss_phys", "vbif_phys"; 1864 1865 power-domains = <&mmcc MDSS_GDSC>; 1866 1867 clocks = <&mmcc MDSS_AHB_CLK>, 1868 <&mmcc MDSS_AXI_CLK>, 1869 <&mmcc MDSS_VSYNC_CLK>; 1870 clock-names = "iface", "bus", "vsync"; 1871 1872 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1873 1874 interrupt-controller; 1875 #interrupt-cells = <1>; 1876 1877 status = "disabled"; 1878 1879 #address-cells = <1>; 1880 #size-cells = <1>; 1881 ranges; 1882 1883 mdp: display-controller@fd900000 { 1884 compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; 1885 reg = <0xfd900100 0x22000>; 1886 reg-names = "mdp_phys"; 1887 1888 interrupt-parent = <&mdss>; 1889 interrupts = <0>; 1890 1891 clocks = <&mmcc MDSS_AHB_CLK>, 1892 <&mmcc MDSS_AXI_CLK>, 1893 <&mmcc MDSS_MDP_CLK>, 1894 <&mmcc MDSS_VSYNC_CLK>; 1895 clock-names = "iface", "bus", "core", "vsync"; 1896 1897 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1898 interconnect-names = "mdp0-mem"; 1899 1900 ports { 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 1904 port@0 { 1905 reg = <0>; 1906 mdp5_intf1_out: endpoint { 1907 remote-endpoint = <&dsi0_in>; 1908 }; 1909 }; 1910 1911 port@1 { 1912 reg = <1>; 1913 mdp5_intf2_out: endpoint { 1914 remote-endpoint = <&dsi1_in>; 1915 }; 1916 }; 1917 }; 1918 }; 1919 1920 dsi0: dsi@fd922800 { 1921 compatible = "qcom,msm8974-dsi-ctrl", 1922 "qcom,mdss-dsi-ctrl"; 1923 reg = <0xfd922800 0x1f8>; 1924 reg-names = "dsi_ctrl"; 1925 1926 interrupt-parent = <&mdss>; 1927 interrupts = <4>; 1928 1929 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1930 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1931 1932 clocks = <&mmcc MDSS_MDP_CLK>, 1933 <&mmcc MDSS_AHB_CLK>, 1934 <&mmcc MDSS_AXI_CLK>, 1935 <&mmcc MDSS_BYTE0_CLK>, 1936 <&mmcc MDSS_PCLK0_CLK>, 1937 <&mmcc MDSS_ESC0_CLK>, 1938 <&mmcc MMSS_MISC_AHB_CLK>; 1939 clock-names = "mdp_core", 1940 "iface", 1941 "bus", 1942 "byte", 1943 "pixel", 1944 "core", 1945 "core_mmss"; 1946 1947 phys = <&dsi0_phy>; 1948 1949 status = "disabled"; 1950 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 1954 ports { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 port@0 { 1959 reg = <0>; 1960 dsi0_in: endpoint { 1961 remote-endpoint = <&mdp5_intf1_out>; 1962 }; 1963 }; 1964 1965 port@1 { 1966 reg = <1>; 1967 dsi0_out: endpoint { 1968 }; 1969 }; 1970 }; 1971 }; 1972 1973 dsi0_phy: phy@fd922a00 { 1974 compatible = "qcom,dsi-phy-28nm-hpm"; 1975 reg = <0xfd922a00 0xd4>, 1976 <0xfd922b00 0x280>, 1977 <0xfd922d80 0x30>; 1978 reg-names = "dsi_pll", 1979 "dsi_phy", 1980 "dsi_phy_regulator"; 1981 1982 #clock-cells = <1>; 1983 #phy-cells = <0>; 1984 1985 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1986 clock-names = "iface", "ref"; 1987 1988 status = "disabled"; 1989 }; 1990 1991 dsi1: dsi@fd922e00 { 1992 compatible = "qcom,msm8974-dsi-ctrl", 1993 "qcom,mdss-dsi-ctrl"; 1994 reg = <0xfd922e00 0x1f8>; 1995 reg-names = "dsi_ctrl"; 1996 1997 interrupt-parent = <&mdss>; 1998 interrupts = <4>; 1999 2000 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 2001 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 2002 2003 clocks = <&mmcc MDSS_MDP_CLK>, 2004 <&mmcc MDSS_AHB_CLK>, 2005 <&mmcc MDSS_AXI_CLK>, 2006 <&mmcc MDSS_BYTE1_CLK>, 2007 <&mmcc MDSS_PCLK1_CLK>, 2008 <&mmcc MDSS_ESC1_CLK>, 2009 <&mmcc MMSS_MISC_AHB_CLK>; 2010 clock-names = "mdp_core", 2011 "iface", 2012 "bus", 2013 "byte", 2014 "pixel", 2015 "core", 2016 "core_mmss"; 2017 2018 phys = <&dsi1_phy>; 2019 2020 status = "disabled"; 2021 2022 #address-cells = <1>; 2023 #size-cells = <0>; 2024 2025 ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 2029 port@0 { 2030 reg = <0>; 2031 dsi1_in: endpoint { 2032 remote-endpoint = <&mdp5_intf2_out>; 2033 }; 2034 }; 2035 2036 port@1 { 2037 reg = <1>; 2038 dsi1_out: endpoint { 2039 }; 2040 }; 2041 }; 2042 }; 2043 2044 dsi1_phy: phy@fd923000 { 2045 compatible = "qcom,dsi-phy-28nm-hpm"; 2046 reg = <0xfd923000 0xd4>, 2047 <0xfd923100 0x280>, 2048 <0xfd923380 0x30>; 2049 reg-names = "dsi_pll", 2050 "dsi_phy", 2051 "dsi_phy_regulator"; 2052 2053 #clock-cells = <1>; 2054 #phy-cells = <0>; 2055 2056 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 2057 clock-names = "iface", "ref"; 2058 2059 status = "disabled"; 2060 }; 2061 }; 2062 2063 cci: cci@fda0c000 { 2064 compatible = "qcom,msm8974-cci"; 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 reg = <0xfda0c000 0x1000>; 2068 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 2069 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2070 <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 2071 <&mmcc CAMSS_CCI_CCI_CLK>; 2072 clock-names = "camss_top_ahb", 2073 "cci_ahb", 2074 "cci"; 2075 2076 pinctrl-names = "default", "sleep"; 2077 pinctrl-0 = <&cci_default>; 2078 pinctrl-1 = <&cci_sleep>; 2079 2080 status = "disabled"; 2081 2082 cci_i2c0: i2c-bus@0 { 2083 reg = <0>; 2084 clock-frequency = <100000>; 2085 #address-cells = <1>; 2086 #size-cells = <0>; 2087 }; 2088 2089 cci_i2c1: i2c-bus@1 { 2090 reg = <1>; 2091 clock-frequency = <100000>; 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 }; 2095 }; 2096 2097 gpu: adreno@fdb00000 { 2098 compatible = "qcom,adreno-330.1", "qcom,adreno"; 2099 reg = <0xfdb00000 0x10000>; 2100 reg-names = "kgsl_3d0_reg_memory"; 2101 2102 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2103 interrupt-names = "kgsl_3d0_irq"; 2104 2105 clocks = <&mmcc OXILI_GFX3D_CLK>, 2106 <&mmcc OXILICX_AHB_CLK>, 2107 <&mmcc OXILICX_AXI_CLK>; 2108 clock-names = "core", "iface", "mem_iface"; 2109 2110 sram = <&gmu_sram>; 2111 power-domains = <&mmcc OXILICX_GDSC>; 2112 operating-points-v2 = <&gpu_opp_table>; 2113 2114 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 2115 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 2116 interconnect-names = "gfx-mem", "ocmem"; 2117 2118 // iommus = <&gpu_iommu 0>; 2119 2120 status = "disabled"; 2121 2122 gpu_opp_table: opp-table { 2123 compatible = "operating-points-v2"; 2124 2125 opp-320000000 { 2126 opp-hz = /bits/ 64 <320000000>; 2127 }; 2128 2129 opp-200000000 { 2130 opp-hz = /bits/ 64 <200000000>; 2131 }; 2132 2133 opp-27000000 { 2134 opp-hz = /bits/ 64 <27000000>; 2135 }; 2136 }; 2137 }; 2138 2139 sram@fdd00000 { 2140 compatible = "qcom,msm8974-ocmem"; 2141 reg = <0xfdd00000 0x2000>, 2142 <0xfec00000 0x180000>; 2143 reg-names = "ctrl", "mem"; 2144 ranges = <0 0xfec00000 0x180000>; 2145 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 2146 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 2147 clock-names = "core", "iface"; 2148 2149 #address-cells = <1>; 2150 #size-cells = <1>; 2151 2152 gmu_sram: gmu-sram@0 { 2153 reg = <0x0 0x100000>; 2154 }; 2155 }; 2156 2157 remoteproc_adsp: remoteproc@fe200000 { 2158 compatible = "qcom,msm8974-adsp-pil"; 2159 reg = <0xfe200000 0x100>; 2160 2161 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2162 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2163 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2164 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2165 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2166 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2167 2168 clocks = <&xo_board>; 2169 clock-names = "xo"; 2170 2171 memory-region = <&adsp_region>; 2172 2173 qcom,smem-states = <&adsp_smp2p_out 0>; 2174 qcom,smem-state-names = "stop"; 2175 2176 status = "disabled"; 2177 2178 smd-edge { 2179 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2180 2181 qcom,ipc = <&apcs 8 8>; 2182 qcom,smd-edge = <1>; 2183 label = "lpass"; 2184 }; 2185 }; 2186 2187 imem: sram@fe805000 { 2188 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 2189 reg = <0xfe805000 0x1000>; 2190 2191 reboot-mode { 2192 compatible = "syscon-reboot-mode"; 2193 offset = <0x65c>; 2194 }; 2195 }; 2196 }; 2197 2198 thermal-zones { 2199 cpu0-thermal { 2200 polling-delay-passive = <250>; 2201 polling-delay = <1000>; 2202 2203 thermal-sensors = <&tsens 5>; 2204 2205 trips { 2206 cpu_alert0: trip0 { 2207 temperature = <75000>; 2208 hysteresis = <2000>; 2209 type = "passive"; 2210 }; 2211 cpu_crit0: trip1 { 2212 temperature = <110000>; 2213 hysteresis = <2000>; 2214 type = "critical"; 2215 }; 2216 }; 2217 }; 2218 2219 cpu1-thermal { 2220 polling-delay-passive = <250>; 2221 polling-delay = <1000>; 2222 2223 thermal-sensors = <&tsens 6>; 2224 2225 trips { 2226 cpu_alert1: trip0 { 2227 temperature = <75000>; 2228 hysteresis = <2000>; 2229 type = "passive"; 2230 }; 2231 cpu_crit1: trip1 { 2232 temperature = <110000>; 2233 hysteresis = <2000>; 2234 type = "critical"; 2235 }; 2236 }; 2237 }; 2238 2239 cpu2-thermal { 2240 polling-delay-passive = <250>; 2241 polling-delay = <1000>; 2242 2243 thermal-sensors = <&tsens 7>; 2244 2245 trips { 2246 cpu_alert2: trip0 { 2247 temperature = <75000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 cpu_crit2: trip1 { 2252 temperature = <110000>; 2253 hysteresis = <2000>; 2254 type = "critical"; 2255 }; 2256 }; 2257 }; 2258 2259 cpu3-thermal { 2260 polling-delay-passive = <250>; 2261 polling-delay = <1000>; 2262 2263 thermal-sensors = <&tsens 8>; 2264 2265 trips { 2266 cpu_alert3: trip0 { 2267 temperature = <75000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 cpu_crit3: trip1 { 2272 temperature = <110000>; 2273 hysteresis = <2000>; 2274 type = "critical"; 2275 }; 2276 }; 2277 }; 2278 2279 q6-dsp-thermal { 2280 polling-delay-passive = <250>; 2281 polling-delay = <1000>; 2282 2283 thermal-sensors = <&tsens 1>; 2284 2285 trips { 2286 q6_dsp_alert0: trip-point0 { 2287 temperature = <90000>; 2288 hysteresis = <2000>; 2289 type = "hot"; 2290 }; 2291 }; 2292 }; 2293 2294 modemtx-thermal { 2295 polling-delay-passive = <250>; 2296 polling-delay = <1000>; 2297 2298 thermal-sensors = <&tsens 2>; 2299 2300 trips { 2301 modemtx_alert0: trip-point0 { 2302 temperature = <90000>; 2303 hysteresis = <2000>; 2304 type = "hot"; 2305 }; 2306 }; 2307 }; 2308 2309 video-thermal { 2310 polling-delay-passive = <250>; 2311 polling-delay = <1000>; 2312 2313 thermal-sensors = <&tsens 3>; 2314 2315 trips { 2316 video_alert0: trip-point0 { 2317 temperature = <95000>; 2318 hysteresis = <2000>; 2319 type = "hot"; 2320 }; 2321 }; 2322 }; 2323 2324 wlan-thermal { 2325 polling-delay-passive = <250>; 2326 polling-delay = <1000>; 2327 2328 thermal-sensors = <&tsens 4>; 2329 2330 trips { 2331 wlan_alert0: trip-point0 { 2332 temperature = <105000>; 2333 hysteresis = <2000>; 2334 type = "hot"; 2335 }; 2336 }; 2337 }; 2338 2339 gpu-top-thermal { 2340 polling-delay-passive = <250>; 2341 polling-delay = <1000>; 2342 2343 thermal-sensors = <&tsens 9>; 2344 2345 trips { 2346 gpu1_alert0: trip-point0 { 2347 temperature = <90000>; 2348 hysteresis = <2000>; 2349 type = "hot"; 2350 }; 2351 }; 2352 }; 2353 2354 gpu-bottom-thermal { 2355 polling-delay-passive = <250>; 2356 polling-delay = <1000>; 2357 2358 thermal-sensors = <&tsens 10>; 2359 2360 trips { 2361 gpu2_alert0: trip-point0 { 2362 temperature = <90000>; 2363 hysteresis = <2000>; 2364 type = "hot"; 2365 }; 2366 }; 2367 }; 2368 }; 2369 2370 timer { 2371 compatible = "arm,armv7-timer"; 2372 interrupts = <GIC_PPI 2 0xf08>, 2373 <GIC_PPI 3 0xf08>, 2374 <GIC_PPI 4 0xf08>, 2375 <GIC_PPI 1 0xf08>; 2376 clock-frequency = <19200000>; 2377 }; 2378 2379 vreg_boost: vreg-boost { 2380 compatible = "regulator-fixed"; 2381 2382 regulator-name = "vreg-boost"; 2383 regulator-min-microvolt = <3150000>; 2384 regulator-max-microvolt = <3150000>; 2385 2386 regulator-always-on; 2387 regulator-boot-on; 2388 2389 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 2390 enable-active-high; 2391 2392 pinctrl-names = "default"; 2393 pinctrl-0 = <&boost_bypass_n_pin>; 2394 }; 2395 2396 vreg_vph_pwr: vreg-vph-pwr { 2397 compatible = "regulator-fixed"; 2398 regulator-name = "vph-pwr"; 2399 2400 regulator-min-microvolt = <3600000>; 2401 regulator-max-microvolt = <3600000>; 2402 2403 regulator-always-on; 2404 }; 2405}; 2406