1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX65 SoC device tree source 4 * 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx65.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 19 interrupt-parent = <&intc>; 20 21 memory { 22 device_type = "memory"; 23 reg = <0 0>; 24 }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 clock-frequency = <76800000>; 30 clock-output-names = "xo_board"; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 #clock-cells = <0>; 39 }; 40 41 nand_clk_dummy: nand-clk-dummy { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 clocks = <&apcs>; 58 power-domains = <&rpmhpd SDX65_CX_AO>; 59 power-domain-names = "rpmhpd"; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 }; 63 64 firmware { 65 scm { 66 compatible = "qcom,scm-sdx65", "qcom,scm"; 67 }; 68 }; 69 70 mc_virt: interconnect-mc-virt { 71 compatible = "qcom,sdx65-mc-virt"; 72 #interconnect-cells = <1>; 73 qcom,bcm-voters = <&apps_bcm_voter>; 74 }; 75 76 cpu_opp_table: opp-table-cpu { 77 compatible = "operating-points-v2"; 78 opp-shared; 79 80 opp-345600000 { 81 opp-hz = /bits/ 64 <345600000>; 82 required-opps = <&rpmhpd_opp_low_svs>; 83 }; 84 85 opp-576000000 { 86 opp-hz = /bits/ 64 <576000000>; 87 required-opps = <&rpmhpd_opp_svs>; 88 }; 89 90 opp-1094400000 { 91 opp-hz = /bits/ 64 <1094400000>; 92 required-opps = <&rpmhpd_opp_nom>; 93 }; 94 95 opp-1497600000 { 96 opp-hz = /bits/ 64 <1497600000>; 97 required-opps = <&rpmhpd_opp_turbo>; 98 }; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0"; 103 method = "smc"; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 tz_heap_mem: memory@8fcad000 { 112 no-map; 113 reg = <0x8fcad000 0x40000>; 114 }; 115 116 secdata_mem: memory@8fcfd000 { 117 no-map; 118 reg = <0x8fcfd000 0x1000>; 119 }; 120 121 hyp_mem: memory@8fd00000 { 122 no-map; 123 reg = <0x8fd00000 0x80000>; 124 }; 125 126 access_control_mem: memory@8fd80000 { 127 no-map; 128 reg = <0x8fd80000 0x80000>; 129 }; 130 131 aop_mem: memory@8fe00000 { 132 no-map; 133 reg = <0x8fe00000 0x20000>; 134 }; 135 136 smem_mem: memory@8fe20000 { 137 compatible = "qcom,smem"; 138 reg = <0x8fe20000 0xc0000>; 139 hwlocks = <&tcsr_mutex 3>; 140 no-map; 141 }; 142 143 cmd_db: reserved-memory@8fee0000 { 144 compatible = "qcom,cmd-db"; 145 reg = <0x8fee0000 0x20000>; 146 no-map; 147 }; 148 149 tz_mem: memory@8ff00000 { 150 no-map; 151 reg = <0x8ff00000 0x100000>; 152 }; 153 154 tz_apps_mem: memory@90000000 { 155 no-map; 156 reg = <0x90000000 0x500000>; 157 }; 158 159 llcc_tcm_mem: memory@15800000 { 160 no-map; 161 reg = <0x15800000 0x800000>; 162 }; 163 }; 164 165 smp2p-mpss { 166 compatible = "qcom,smp2p"; 167 qcom,smem = <435>, <428>; 168 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 169 mboxes = <&apcs 14>; 170 qcom,local-pid = <0>; 171 qcom,remote-pid = <1>; 172 173 modem_smp2p_out: master-kernel { 174 qcom,entry-name = "master-kernel"; 175 #qcom,smem-state-cells = <1>; 176 }; 177 178 modem_smp2p_in: slave-kernel { 179 qcom,entry-name = "slave-kernel"; 180 interrupt-controller; 181 #interrupt-cells = <2>; 182 }; 183 184 ipa_smp2p_out: ipa-ap-to-modem { 185 qcom,entry-name = "ipa"; 186 #qcom,smem-state-cells = <1>; 187 }; 188 189 ipa_smp2p_in: ipa-modem-to-ap { 190 qcom,entry-name = "ipa"; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 }; 194 }; 195 196 soc: soc { 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges; 200 compatible = "simple-bus"; 201 202 gcc: clock-controller@100000 { 203 compatible = "qcom,gcc-sdx65"; 204 reg = <0x00100000 0x001f7400>; 205 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 206 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 207 #power-domain-cells = <1>; 208 #clock-cells = <1>; 209 #reset-cells = <1>; 210 }; 211 212 blsp1_uart3: serial@831000 { 213 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 214 reg = <0x00831000 0x200>; 215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 217 clock-names = "core", "iface"; 218 status = "disabled"; 219 }; 220 221 usb_hsphy: phy@ff4000 { 222 compatible = "qcom,sdx65-usb-hs-phy", 223 "qcom,usb-snps-hs-7nm-phy"; 224 reg = <0xff4000 0x120>; 225 #phy-cells = <0>; 226 status = "disabled"; 227 clocks = <&rpmhcc RPMH_CXO_CLK>; 228 clock-names = "ref"; 229 resets = <&gcc GCC_QUSB2PHY_BCR>; 230 }; 231 232 usb_qmpphy: phy@ff6000 { 233 compatible = "qcom,sdx65-qmp-usb3-uni-phy"; 234 reg = <0x00ff6000 0x1c8>; 235 status = "disabled"; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 ranges; 239 240 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 241 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 242 <&gcc GCC_USB3_PRIM_CLKREF_EN>; 243 clock-names = "aux", "cfg_ahb", "ref"; 244 245 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 246 <&gcc GCC_USB3_PHY_BCR>; 247 reset-names = "phy", "common"; 248 249 usb_ssphy: phy@ff6200 { 250 reg = <0x00ff6e00 0x160>, 251 <0x00ff7000 0x1ec>, 252 <0x00ff6200 0x1e00>; 253 #phy-cells = <0>; 254 #clock-cells = <0>; 255 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 256 clock-names = "pipe0"; 257 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 258 }; 259 }; 260 261 system_noc: interconnect@1620000 { 262 compatible = "qcom,sdx65-system-noc"; 263 reg = <0x01620000 0x31200>; 264 #interconnect-cells = <1>; 265 qcom,bcm-voters = <&apps_bcm_voter>; 266 }; 267 268 qpic_bam: dma-controller@1b04000 { 269 compatible = "qcom,bam-v1.7.0"; 270 reg = <0x01b04000 0x1c000>; 271 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&rpmhcc RPMH_QPIC_CLK>; 273 clock-names = "bam_clk"; 274 #dma-cells = <1>; 275 qcom,ee = <0>; 276 qcom,controlled-remotely; 277 status = "disabled"; 278 }; 279 280 qpic_nand: nand-controller@1b30000 { 281 compatible = "qcom,sdx55-nand"; 282 reg = <0x01b30000 0x10000>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clocks = <&rpmhcc RPMH_QPIC_CLK>, 286 <&nand_clk_dummy>; 287 clock-names = "core", "aon"; 288 289 dmas = <&qpic_bam 0>, 290 <&qpic_bam 1>, 291 <&qpic_bam 2>; 292 dma-names = "tx", "rx", "cmd"; 293 status = "disabled"; 294 }; 295 296 tcsr_mutex: hwlock@1f40000 { 297 compatible = "qcom,tcsr-mutex"; 298 reg = <0x01f40000 0x40000>; 299 #hwlock-cells = <1>; 300 }; 301 302 remoteproc_mpss: remoteproc@4080000 { 303 compatible = "qcom,sdx55-mpss-pas"; 304 reg = <0x04080000 0x4040>; 305 306 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 307 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 308 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 309 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 310 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 311 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 312 interrupt-names = "wdog", "fatal", "ready", "handover", 313 "stop-ack", "shutdown-ack"; 314 315 clocks = <&rpmhcc RPMH_CXO_CLK>; 316 clock-names = "xo"; 317 318 power-domains = <&rpmhpd SDX65_CX>, 319 <&rpmhpd SDX65_MSS>; 320 power-domain-names = "cx", "mss"; 321 322 qcom,smem-states = <&modem_smp2p_out 0>; 323 qcom,smem-state-names = "stop"; 324 325 status = "disabled"; 326 327 glink-edge { 328 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 329 label = "mpss"; 330 qcom,remote-pid = <1>; 331 mboxes = <&apcs 15>; 332 }; 333 }; 334 335 sdhc_1: mmc@8804000 { 336 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 337 reg = <0x08804000 0x1000>; 338 reg-names = "hc"; 339 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 341 interrupt-names = "hc_irq", "pwr_irq"; 342 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 343 <&gcc GCC_SDCC1_AHB_CLK>; 344 clock-names = "core", "iface"; 345 status = "disabled"; 346 }; 347 348 mem_noc: interconnect@9680000 { 349 compatible = "qcom,sdx65-mem-noc"; 350 reg = <0x09680000 0x27200>; 351 #interconnect-cells = <1>; 352 qcom,bcm-voters = <&apps_bcm_voter>; 353 }; 354 355 usb: usb@a6f8800 { 356 compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; 357 reg = <0x0a6f8800 0x400>; 358 status = "disabled"; 359 #address-cells = <1>; 360 #size-cells = <1>; 361 ranges; 362 363 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 364 <&gcc GCC_USB30_MASTER_CLK>, 365 <&gcc GCC_USB30_MSTR_AXI_CLK>, 366 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 367 <&gcc GCC_USB30_SLEEP_CLK>; 368 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 369 "sleep"; 370 371 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 372 <&gcc GCC_USB30_MASTER_CLK>; 373 assigned-clock-rates = <19200000>, <200000000>; 374 375 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 376 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, 377 <&pdc 18 IRQ_TYPE_EDGE_BOTH>, 378 <&pdc 19 IRQ_TYPE_EDGE_BOTH>; 379 interrupt-names = "hs_phy_irq", 380 "ss_phy_irq", 381 "dm_hs_phy_irq", 382 "dp_hs_phy_irq"; 383 384 power-domains = <&gcc USB30_GDSC>; 385 386 resets = <&gcc GCC_USB30_BCR>; 387 388 usb_dwc3: usb@a600000 { 389 compatible = "snps,dwc3"; 390 reg = <0x0a600000 0xcd00>; 391 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 392 iommus = <&apps_smmu 0x1a0 0x0>; 393 snps,dis_u2_susphy_quirk; 394 snps,dis_enblslpm_quirk; 395 phys = <&usb_hsphy>, <&usb_ssphy>; 396 phy-names = "usb2-phy", "usb3-phy"; 397 }; 398 }; 399 400 restart@c264000 { 401 compatible = "qcom,pshold"; 402 reg = <0x0c264000 0x1000>; 403 }; 404 405 spmi_bus: qcom,spmi@c440000 { 406 compatible = "qcom,spmi-pmic-arb"; 407 reg = <0xc440000 0xd00>, 408 <0xc600000 0x2000000>, 409 <0xe600000 0x100000>, 410 <0xe700000 0xa0000>, 411 <0xc40a000 0x26000>; 412 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 413 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-names = "periph_irq"; 415 interrupt-controller; 416 #interrupt-cells = <4>; 417 #address-cells = <2>; 418 #size-cells = <0>; 419 cell-index = <0>; 420 qcom,channel = <0>; 421 qcom,ee = <0>; 422 }; 423 424 tlmm: pinctrl@f100000 { 425 compatible = "qcom,sdx65-tlmm"; 426 reg = <0xf100000 0x300000>; 427 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 gpio-ranges = <&tlmm 0 0 109>; 431 interrupt-controller; 432 interrupt-parent = <&intc>; 433 #interrupt-cells = <2>; 434 }; 435 436 pdc: interrupt-controller@b210000 { 437 compatible = "qcom,sdx65-pdc", "qcom,pdc"; 438 reg = <0xb210000 0x10000>; 439 qcom,pdc-ranges = <0 147 52>, <52 266 32>; 440 #interrupt-cells = <2>; 441 interrupt-parent = <&intc>; 442 interrupt-controller; 443 }; 444 445 sram@1468f000 { 446 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd"; 447 reg = <0x1468f000 0x1000>; 448 ranges = <0x0 0x1468f000 0x1000>; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 452 pil-reloc@94c { 453 compatible = "qcom,pil-reloc-info"; 454 reg = <0x94c 0xc8>; 455 }; 456 }; 457 458 apps_smmu: iommu@15000000 { 459 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 460 reg = <0x15000000 0x40000>; 461 #iommu-cells = <2>; 462 #global-interrupts = <1>; 463 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 496 }; 497 498 intc: interrupt-controller@17800000 { 499 compatible = "qcom,msm-qgic2"; 500 interrupt-controller; 501 interrupt-parent = <&intc>; 502 #interrupt-cells = <3>; 503 reg = <0x17800000 0x1000>, 504 <0x17802000 0x1000>; 505 }; 506 507 a7pll: clock@17808000 { 508 compatible = "qcom,sdx55-a7pll"; 509 reg = <0x17808000 0x1000>; 510 clocks = <&rpmhcc RPMH_CXO_CLK>; 511 clock-names = "bi_tcxo"; 512 #clock-cells = <0>; 513 }; 514 515 apcs: mailbox@17810000 { 516 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 517 reg = <0x17810000 0x2000>; 518 #mbox-cells = <1>; 519 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 520 clock-names = "ref", "pll", "aux"; 521 #clock-cells = <0>; 522 }; 523 524 watchdog@17817000 { 525 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; 526 reg = <0x17817000 0x1000>; 527 clocks = <&sleep_clk>; 528 }; 529 530 timer@17820000 { 531 #address-cells = <1>; 532 #size-cells = <1>; 533 ranges; 534 compatible = "arm,armv7-timer-mem"; 535 reg = <0x17820000 0x1000>; 536 clock-frequency = <19200000>; 537 538 frame@17821000 { 539 frame-number = <0>; 540 interrupts = <GIC_SPI 7 0x4>, 541 <GIC_SPI 6 0x4>; 542 reg = <0x17821000 0x1000>, 543 <0x17822000 0x1000>; 544 }; 545 546 frame@17823000 { 547 frame-number = <1>; 548 interrupts = <GIC_SPI 8 0x4>; 549 reg = <0x17823000 0x1000>; 550 status = "disabled"; 551 }; 552 553 frame@17824000 { 554 frame-number = <2>; 555 interrupts = <GIC_SPI 9 0x4>; 556 reg = <0x17824000 0x1000>; 557 status = "disabled"; 558 }; 559 560 frame@17825000 { 561 frame-number = <3>; 562 interrupts = <GIC_SPI 10 0x4>; 563 reg = <0x17825000 0x1000>; 564 status = "disabled"; 565 }; 566 567 frame@17826000 { 568 frame-number = <4>; 569 interrupts = <GIC_SPI 11 0x4>; 570 reg = <0x17826000 0x1000>; 571 status = "disabled"; 572 }; 573 574 frame@17827000 { 575 frame-number = <5>; 576 interrupts = <GIC_SPI 12 0x4>; 577 reg = <0x17827000 0x1000>; 578 status = "disabled"; 579 }; 580 581 frame@17828000 { 582 frame-number = <6>; 583 interrupts = <GIC_SPI 13 0x4>; 584 reg = <0x17828000 0x1000>; 585 status = "disabled"; 586 }; 587 588 frame@17829000 { 589 frame-number = <7>; 590 interrupts = <GIC_SPI 14 0x4>; 591 reg = <0x17829000 0x1000>; 592 status = "disabled"; 593 }; 594 }; 595 596 apps_rsc: rsc@17830000 { 597 label = "apps_rsc"; 598 compatible = "qcom,rpmh-rsc"; 599 reg = <0x17830000 0x10000>, 600 <0x17840000 0x10000>; 601 reg-names = "drv-0", "drv-1"; 602 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 604 qcom,tcs-offset = <0xd00>; 605 qcom,drv-id = <1>; 606 qcom,tcs-config = <ACTIVE_TCS 2>, 607 <SLEEP_TCS 2>, 608 <WAKE_TCS 2>, 609 <CONTROL_TCS 1>; 610 611 rpmhcc: clock-controller { 612 compatible = "qcom,sdx65-rpmh-clk"; 613 #clock-cells = <1>; 614 clock-names = "xo"; 615 clocks = <&xo_board>; 616 }; 617 618 rpmhpd: power-controller { 619 compatible = "qcom,sdx65-rpmhpd"; 620 #power-domain-cells = <1>; 621 operating-points-v2 = <&rpmhpd_opp_table>; 622 623 rpmhpd_opp_table: opp-table { 624 compatible = "operating-points-v2"; 625 626 rpmhpd_opp_ret: opp1 { 627 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 628 }; 629 630 rpmhpd_opp_min_svs: opp2 { 631 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 632 }; 633 634 rpmhpd_opp_low_svs: opp3 { 635 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 636 }; 637 638 rpmhpd_opp_svs: opp4 { 639 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 640 }; 641 642 rpmhpd_opp_svs_l1: opp5 { 643 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 644 }; 645 646 rpmhpd_opp_nom: opp6 { 647 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 648 }; 649 650 rpmhpd_opp_nom_l1: opp7 { 651 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 652 }; 653 654 rpmhpd_opp_nom_l2: opp8 { 655 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 656 }; 657 658 rpmhpd_opp_turbo: opp9 { 659 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 660 }; 661 662 rpmhpd_opp_turbo_l1: opp10 { 663 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 664 }; 665 }; 666 }; 667 668 apps_bcm_voter: bcm-voter { 669 compatible = "qcom,bcm-voter"; 670 }; 671 672 }; 673 }; 674 675 timer { 676 compatible = "arm,armv7-timer"; 677 interrupts = <1 13 0xf08>, 678 <1 12 0xf08>, 679 <1 10 0xf08>, 680 <1 11 0xf08>; 681 clock-frequency = <19200000>; 682 }; 683}; 684