1 /* 2 * Renesas SCP/MCP Software 3 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef RCAR_SDS_H 9 #define RCAR_SDS_H 10 11 #include <mod_sds.h> 12 13 /* 14 * Structure identifiers. 15 */ 16 enum rcar_sds_struct_id { 17 RCAR_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 18 RCAR_SDS_ROM_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 19 RCAR_SDS_RAM_VERSION = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 20 RCAR_SDS_PLATFORM_ID = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 21 RCAR_SDS_RESET_SYNDROME = 5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 22 RCAR_SDS_FEATURE_AVAILABILITY = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 23 RCAR_SDS_CPU_BOOTCTR = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 24 RCAR_SDS_CPU_FLAGS = 8 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 25 RCAR_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS), 26 }; 27 28 enum rcar_sds_region_idx { 29 RCAR_SDS_REGION_SECURE, 30 RCAR_SDS_REGION_COUNT, 31 }; 32 33 /* 34 * Structure sizes. 35 */ 36 #define RCAR_SDS_CPU_INFO_SIZE 4 37 #define RCAR_SDS_ROM_VERSION_SIZE 4 38 #define RCAR_SDS_RAM_VERSION_SIZE 4 39 #define RCAR_SDS_PLATFORM_ID_SIZE 8 40 #define RCAR_SDS_RESET_SYNDROME_SIZE 4 41 #define RCAR_SDS_FEATURE_AVAILABILITY_SIZE 4 42 #define RCAR_SDS_CPU_BOOTCTR_SIZE 8 43 #define RCAR_SDS_CPU_FLAGS_SIZE 8 44 #define RCAR_SDS_BOOTLOADER_SIZE 12 45 46 /* 47 * Field masks and offsets for the RCAR_SDS_AP_CPU_INFO structure. 48 */ 49 #define RCAR_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF 50 #define RCAR_SDS_CPU_INFO_PRIMARY_POS 0 51 52 /* 53 * Structure, field masks and offsets for the RCAR_SDS_PLATFORM_ID structure. 54 */ 55 struct rcar_sds_platid { 56 uint32_t platform_identifier; 57 uint32_t platform_type_identifier; 58 }; 59 60 enum rcar_sds_ram_idx { 61 RCAR_SDS_RAM_VERSION_IDX, 62 RCAR_SDS_RAM_FEATURES_IDX, 63 RCAR_SDS_RAM_IDX_COUNT 64 }; 65 66 #define RCAR_SDS_PLATID_PARTNO_MASK 0xFFF 67 #define RCAR_SDS_PLATID_DESIGNER_MASK 0xFF000 68 #define RCAR_SDS_PLATID_REV_MINOR_MASK 0xF00000 69 #define RCAR_SDS_PLATID_REV_MAJOR_MASK 0xF000000 70 #define RCAR_SDS_PLATID_CONFIG_MASK 0xF0000000 71 #define RCAR_SDS_PLATID_TYPE_MASK 0xF 72 73 #define RCAR_SDS_PLATID_PARTNO_POS 0 74 #define RCAR_SDS_PLATID_DESIGNER_POS 12 75 #define RCAR_SDS_PLATID_REV_MINOR_POS 20 76 #define RCAR_SDS_PLATID_REV_MAJOR_POS 24 77 #define RCAR_SDS_PLATID_CONFIG_POS 28 78 79 #define RCAR_SDS_PLATID_TYPE_POS 0 80 81 /* 82 * Field masks and offsets for the RCAR_SDS_RESET_SYNDROME structure. 83 */ 84 #define RCAR_SDS_RESET_SYNDROME_POR_MASK 0x1 85 #define RCAR_SDS_RESET_SYNDROME_WDOGSCP_MASK 0x2 86 #define RCAR_SDS_RESET_SYNDROME_WDOGAP_MASK 0x4 87 #define RCAR_SDS_RESET_SYNDROME_SYSRESET_MASK 0x8 88 #define RCAR_SDS_RESET_SYNDROME_M3LOCKUP_MASK 0x10 89 90 #define RCAR_SDS_RESET_SYNDROME_POR_POS 0 91 #define RCAR_SDS_RESET_SYNDROME_WDOGSCP_POS 1 92 #define RCAR_SDS_RESET_SYNDROME_WDOGAP_POS 2 93 #define RCAR_SDS_RESET_SYNDROME_SYSRESET_POS 3 94 #define RCAR_SDS_RESET_SYNDROME_M3LOCKUP_POS 4 95 96 /* 97 * Field masks and offsets for the RCAR_SDS_FEATURE_AVAILABILITY structure. 98 */ 99 #define RCAR_SDS_FEATURE_FIRMWARE_MASK 0x1 100 #define RCAR_SDS_FEATURE_DMC_MASK 0x2 101 #define RCAR_SDS_FEATURE_MESSAGING_MASK 0x4 102 103 #define RCAR_SDS_FEATURE_FIRMWARE_POS 0 104 #define RCAR_SDS_FEATURE_DMC_POS 1 105 #define RCAR_SDS_FEATURE_MESSAGING_POS 2 106 107 /* 108 * Field masks and offsets for the RCAR_SDS_CPU_BOOTCTR structure. 109 */ 110 #define RCAR_SDS_CPU_BOOTCTR_CPU0_MASK 0xFF 111 #define RCAR_SDS_CPU_BOOTCTR_CPU1_MASK 0xFF00 112 #define RCAR_SDS_CPU_BOOTCTR_CPU2_MASK 0xFF0000 113 #define RCAR_SDS_CPU_BOOTCTR_CPU3_MASK 0xFF000000 114 #define RCAR_SDS_CPU_BOOTCTR_CPU4_MASK 0xFF 115 #define RCAR_SDS_CPU_BOOTCTR_CPU5_MASK 0xFF00 116 #define RCAR_SDS_CPU_BOOTCTR_CPU6_MASK 0xFF0000 117 #define RCAR_SDS_CPU_BOOTCTR_CPU7_MASK 0xFF000000 118 119 120 #define RCAR_SDS_CPU_BOOTCTR_CPU0_POS 0 121 #define RCAR_SDS_CPU_BOOTCTR_CPU1_POS 8 122 #define RCAR_SDS_CPU_BOOTCTR_CPU2_POS 16 123 #define RCAR_SDS_CPU_BOOTCTR_CPU3_POS 24 124 #define RCAR_SDS_CPU_BOOTCTR_CPU4_POS 0 125 #define RCAR_SDS_CPU_BOOTCTR_CPU5_POS 8 126 #define RCAR_SDS_CPU_BOOTCTR_CPU6_POS 16 127 #define RCAR_SDS_CPU_BOOTCTR_CPU7_POS 24 128 129 /* 130 * Field masks and offsets for the RCAR_SDS_CPU_FLAGS structure. 131 */ 132 #define RCAR_SDS_CPU_FLAGS_CPU0_WFI_MASK 0x1 133 #define RCAR_SDS_CPU_FLAGS_CPU1_WFI_MASK 0x100 134 #define RCAR_SDS_CPU_FLAGS_CPU2_WFI_MASK 0x10000 135 #define RCAR_SDS_CPU_FLAGS_CPU3_WFI_MASK 0x1000000 136 #define RCAR_SDS_CPU_FLAGS_CPU4_WFI_MASK 0x1 137 #define RCAR_SDS_CPU_FLAGS_CPU5_WFI_MASK 0x100 138 #define RCAR_SDS_CPU_FLAGS_CPU6_WFI_MASK 0x10000 139 #define RCAR_SDS_CPU_FLAGS_CPU7_WFI_MASK 0x1000000 140 141 #define RCAR_SDS_CPU_FLAGS_CPU0_WFI_POS 0 142 #define RCAR_SDS_CPU_FLAGS_CPU1_WFI_POS 8 143 #define RCAR_SDS_CPU_FLAGS_CPU2_WFI_POS 16 144 #define RCAR_SDS_CPU_FLAGS_CPU3_WFI_POS 24 145 #define RCAR_SDS_CPU_FLAGS_CPU4_WFI_POS 0 146 #define RCAR_SDS_CPU_FLAGS_CPU5_WFI_POS 8 147 #define RCAR_SDS_CPU_FLAGS_CPU6_WFI_POS 16 148 #define RCAR_SDS_CPU_FLAGS_CPU7_WFI_POS 24 149 150 /* 151 * Field masks and offsets for the RCAR_SDS_BOOTLOADER structure. 152 */ 153 #define RCAR_SDS_BOOTLOADER_VALID_MASK 0x1 154 #define RCAR_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF 155 #define RCAR_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF 156 157 #define RCAR_SDS_BOOTLOADER_VALID_POS 0 158 #define RCAR_SDS_BOOTLOADER_OFFSET_POS 0 159 #define RCAR_SDS_BOOTLOADER_SIZE_POS 0 160 161 #define RCAR_SDS_FEATURE_FIRMWARE_INIT 0x0 162 #define RCAR_SDS_SCP_RAM_SIZE 2048 163 #define RCAR_SDS_SCP_RAM_BASE_OFFSET 0x800 164 165 #endif /* RCAR_SDS_H */ 166