1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * SCP PIK registers 9 */ 10 11 #ifndef RDN1E1_PIK_SCP_H 12 #define RDN1E1_PIK_SCP_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 /*! 19 * \brief SCP PIK register definitions 20 */ 21 struct pik_scp_reg { 22 uint8_t RESERVED0[0x10 - 0x0]; 23 FWK_RW uint32_t RESET_SYNDROME; 24 uint8_t RESERVED1[0x20 - 0x14]; 25 FWK_RW uint32_t SURVIVAL_RESET_STATUS; 26 uint8_t RESERVED2[0x34 - 0x24]; 27 FWK_RW uint32_t ADDR_TRANS; 28 FWK_RW uint32_t DBG_ADDR_TRANS; 29 uint8_t RESERVED3[0x40 - 0x3C]; 30 FWK_RW uint32_t WS1_TIMER_MATCH; 31 FWK_RW uint32_t WS1_TIMER_EN; 32 uint8_t RESERVED4[0x200 - 0x48]; 33 FWK_R uint32_t SS_RESET_STATUS; 34 FWK_W uint32_t SS_RESET_SET; 35 FWK_W uint32_t SS_RESET_CLR; 36 uint8_t RESERVED5[0x810 - 0x20C]; 37 FWK_RW uint32_t CORECLK_CTRL; 38 FWK_RW uint32_t CORECLK_DIV1; 39 uint8_t RESERVED6[0x820 - 0x818]; 40 FWK_RW uint32_t ACLK_CTRL; 41 FWK_RW uint32_t ACLK_DIV1; 42 uint8_t RESERVED7[0x830 - 0x828]; 43 FWK_RW uint32_t GTSYNCCLK_CTRL; 44 FWK_RW uint32_t GTSYNCCLK_DIV1; 45 uint8_t RESERVED8[0xA10 - 0x838]; 46 FWK_R uint32_t PLL_STATUS[17]; 47 uint8_t RESERVED9[0xA60 - 0xA54]; 48 FWK_R uint32_t CONS_MMUTCU_INT_STATUS; 49 FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; 50 FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; 51 FWK_W uint32_t CONS_MMUTCU_INT_CLR; 52 FWK_W uint32_t CONS_MMUTBU_INT_CLR0; 53 FWK_W uint32_t CONS_MMUTBU_INT_CLR1; 54 uint8_t RESERVED10[0xB00 - 0xA78]; 55 FWK_R uint32_t MHU_NS_INT_STATUS; 56 FWK_R uint32_t MHU_S_INT_STATUS; 57 uint8_t RESERVED11[0xB20 - 0xB08]; 58 FWK_R uint32_t CPU_PPU_INT_STATUS[8]; 59 FWK_R uint32_t CLUS_PPU_INT_STATUS; 60 uint8_t RESERVED12[0xB60 - 0xB44]; 61 FWK_R uint32_t TIMER_INT_STATUS[8]; 62 FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; 63 uint8_t RESERVED13[0xBC0 - 0xBA0]; 64 FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; 65 uint8_t RESERVED14[0xBF0 - 0xBE0]; 66 FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; 67 FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; 68 uint8_t RESERVED15[0xC00 - 0xBF8]; 69 FWK_R uint32_t CLUS_FAULT_INT_STATUS; 70 uint8_t RESERVED16[0xC30 - 0xC04]; 71 FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; 72 uint8_t RESERVED17[0xD00 - 0xC34]; 73 FWK_R uint32_t DMC0_4_INT_STATUS; 74 FWK_R uint32_t DMC1_5_INT_STATUS; 75 FWK_R uint32_t DMC2_6_INT_STATUS; 76 FWK_R uint32_t DMC3_7_INT_STATUS; 77 uint8_t RESERVED18[0xFC0 - 0xD10]; 78 FWK_R uint32_t PCL_CFG; 79 uint8_t RESERVED19[0xFD0 - 0xFC4]; 80 FWK_R uint32_t PID4; 81 FWK_R uint32_t PID5; 82 FWK_R uint32_t PID6; 83 FWK_R uint32_t PID7; 84 FWK_R uint32_t PID0; 85 FWK_R uint32_t PID1; 86 FWK_R uint32_t PID2; 87 FWK_R uint32_t PID3; 88 FWK_R uint32_t ID0; 89 FWK_R uint32_t ID1; 90 FWK_R uint32_t ID2; 91 FWK_R uint32_t ID3; 92 }; 93 94 #define PLL_STATUS_0_REFCLK UINT32_C(0x00000001) 95 #define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002) 96 #define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004) 97 #define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008) 98 99 #define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32))) 100 101 #endif /* RDN1E1_PIK_SCP_H */ 102