1 /**
2 ******************************************************************************
3 * @file rtl8721d_gdma.h
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for the GDMA firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #ifndef _RTL8710B_GDMA_H_
20 #define _RTL8710B_GDMA_H_
21
22 /** @addtogroup AmebaD_Periph_Driver
23 * @{
24 */
25
26 /** @defgroup GDMA GDMA
27 * @{
28 */
29
30 /** @addtogroup GDMA
31 * @verbatim
32 *******************************************************************************************
33 * Introduction
34 *******************************************************************************************
35 * AmebaD supports two GDMAs, GDMA0 in KM0, and GDMA0 in KM4. GDMA0 in KM0 has four channels,
36 * while GDMA0 in KM4 has six channels. The Msize of channel 0 can be up to 256 when copy data
37 * from mem0 to mem1(between different memory), and the Msize should be no more than 8 in
38 * other situations.
39 *
40 * GDMA0 in KM0:
41 * - Base Address: GDMA0_REG_BASE(KM0)
42 *
43 * - Channel index: 0~3
44 *
45 * - Block size range: 1~4095
46 *
47 * - Transfer Type and Flow Control:
48 * TTFCMemToMem (Memory to Memory)
49 * TTFCMemToPeri (Memory to Peripheral)
50 * TTFCPeriToMem (Peripheral to Memory)
51 * TTFCPeriToPeri (Peripheral to Peripheral)
52 *
53 * - Source and destination data width:
54 * TrWidthOneByte
55 * TrWidthTwoBytes
56 * TrWidthFourBytes
57 *
58 * - Source and destination burst transaction length:
59 * MsizeOne (One Byte)
60 * MsizeFour (Four Bytes)
61 * MsizeEight (Eight Bytes)
62 * MsizeSixteen (sixteen Bytes, only channel0 supports in some situations)
63 *
64 * - IRQ:
65 * GDMA0_CHANNEL0_IRQ_LP,
66 * GDMA0_CHANNEL1_IRQ_LP,
67 * GDMA0_CHANNEL2_IRQ_LP,
68 * GDMA0_CHANNEL3_IRQ_LP,
69 *
70 * - GDMA handshake interface with peripherals:
71 * GDMA_HANDSHAKE_INTERFACE_UART3_TX
72 * GDMA_HANDSHAKE_INTERFACE_UART3_TX
73 * GDMA_HANDSHAKE_INTERFACE_I2C0_TX
74 * GDMA_HANDSHAKE_INTERFACE_I2C0_RX
75 * GDMA_HANDSHAKE_INTERFACE_ADC_RX
76 * GDMA_HANDSHAKE_INTERFACE_SGPIO_TX
77 *
78 *
79 * GDMA0 in KM4:
80 * - Base Address: GDMA0_REG_BASE(KM4)
81 *
82 * - Channel index: 0~5
83 *
84 * - Block size range: 1~4095
85 *
86 * - Transfer Type and Flow Control:
87 * TTFCMemToMem (Memory to Memory)
88 * TTFCMemToPeri (Memory to Peripheral)
89 * TTFCPeriToMem (Peripheral to Memory)
90 * TTFCPeriToPeri (Peripheral to Peripheral)
91 *
92 * - Source and destination data width:
93 * TrWidthOneByte
94 * TrWidthTwoBytes
95 * TrWidthFourBytes
96 *
97 * - Source and destination burst transaction length:
98 * MsizeOne (One Byte)
99 * MsizeFour (Four Bytes)
100 * MsizeEight (Eight Bytes)
101 * MsizeSixteen (sixteen Bytes, only channel0 supports in some situations)
102 * - IRQ:
103 * GDMA0_CHANNEL0_IRQ,
104 * GDMA0_CHANNEL1_IRQ
105 * GDMA0_CHANNEL2_IRQ
106 * GDMA0_CHANNEL3_IRQ
107 * GDMA0_CHANNEL4_IRQ
108 * GDMA0_CHANNEL5_IRQ
109 *
110 * - GDMA handshake interface with peripherals:
111 * GDMA_HANDSHAKE_INTERFACE_UART0_TX
112 * GDMA_HANDSHAKE_INTERFACE_UART0_RX
113 * GDMA_HANDSHAKE_INTERFACE_UART1_TX
114 * GDMA_HANDSHAKE_INTERFACE_UART1_RX
115 * GDMA_HANDSHAKE_INTERFACE_SPI0_TX
116 * GDMA_HANDSHAKE_INTERFACE_SPI0_RX
117 * GDMA_HANDSHAKE_INTERFACE_SPI1_TX
118 * GDMA_HANDSHAKE_INTERFACE_SPI1_RX
119 * GDMA_HANDSHAKE_INTERFACE_USI0_TX
120 * GDMA_HANDSHAKE_INTERFACE_USI0_RX
121 * GDMA_HANDSHAKE_INTERFACE_AUDIO_TX
122 * GDMA_HANDSHAKE_INTERFACE_AUDIO_RX
123 *
124 *****************************************************************************************
125 * how to use GDMA
126 *****************************************************************************************
127 * To use the GDMA, the following steps are mandatory:
128 *
129 * 1. Allocate a GDMA channel using the follwoing function.
130 * GDMA_ChnlAlloc(u32 GDMA_Index, IRQ_FUN IrqFun, u32 IrqData, u32 IrqPriority)
131 *
132 * @note This function also includes the following operation:
133 * - register irq handler if use interrupt mode
134 * - enable NVIC interrupt
135 * - register the GDMA channel to use
136 * - enable GDMA peripheral clock
137 *
138 * 2. Program GDMA index, GDMA channel, data width, Msize, transfer direction, address increment mode,
139 * hardware handshake interface, reload control, interrupt type, block size, multi-block configuration
140 * and the source and destination address using the GDMA_Init() function.
141 *
142 * 3. Enable the corresponding interrupt using the function.
143 * GDMA_INTConfig() and register the uart irq handler if you need to use interrupt mode.
144 *
145 * @note This step is included in the "step 2"(GDMA_Init()).
146 *
147 * 4. Enable GDMA using function GDMA_Cmd().
148 *
149 *
150 * @endverbatim
151 */
152
153
154 /* Exported Types --------------------------------------------------------*/
155
156 /** @defgroup GDMA_Exported_Types GDMA Exported Types
157 * @{
158 */
159
160 /**
161 * @brief GDMA Init structure definition
162 */
163 typedef struct {
164 u8 GDMA_Index; /*!< Specifies the GDMA index.
165 This parameter can be the value 0.
166 @note AmebaD supports two GDMAs, GDMA0 in KM0, and GDMA0 in KM4.*/
167
168 u8 GDMA_ChNum; /*!< Specifies the GDMA channel number.
169 This parameter can be the value 0 ~ 5.
170 @note GDMA in KM0 has four channels, channel0 ~ channel3,
171 while GDMA in KM4 has six channels, channel0 ~ channel5.*/
172
173 u32 GDMA_DIR; /*!< Specifies the GDMA transmission direction.
174 This parameter can be a value of @ref GDMA_data_transfer_direction */
175
176 u32 GDMA_DstDataWidth; /*!< Specifies the GDMA destination transfer width.
177 This parameter can be a value of @ref GDMA_source_data_size */
178
179 u32 GDMA_SrcDataWidth; /*!< Specifies the GDMA transfer width.
180 This parameter can be a value of @ref GDMA_source_data_size */
181
182 u32 GDMA_DstInc; /*!< Specifies the GDMA destination address increment mode.
183 This parameter can be a value of @ref GDMA_incremented_mode */
184
185 u32 GDMA_SrcInc; /*!< Specifies the GDMA source address increment mode.
186 This parameter can be a value of @ref GDMA_incremented_mode */
187
188 u32 GDMA_DstMsize; /*!< Specifies the GDMA destination burst transaction length.
189 This parameter can be a value of @ref GDMA_Msize */
190
191 u32 GDMA_SrcMsize; /*!< Specifies the GDMA source burst transaction length.
192 This parameter can be a value of @ref GDMA_Msize */
193
194 u32 GDMA_SrcAddr; /*!< Specifies the GDMA source address.
195 This parameter can be a value of the memory or peripheral space address,
196 depending on the GDMA data transfer direction.If this address is configured,
197 GDMA will move data from here to the destination address space*/
198
199 u32 GDMA_DstAddr; /*!< Specifies the GDMA destination address.
200 This parameter can be a value of the memory or peripheral space address,
201 depending on the GDMA data transfer direction.If this address is configured,
202 GDMA will move data here from source address space*/
203
204 u16 GDMA_BlockSize; /*!< Specifies the GDMA block transfer size.
205 This parameter can be a value between 0 ~ 4095.
206 @note This parameter indicates the total number of single transactions for
207 every block transfer. The field for this parameter locates in CTLx[43:32], so
208 the value of this parameter must be no more than 0xffff.*/
209
210 u32 GDMA_IsrType; /*!< Specifies the GDMA interrupt types.
211 This parameter can be a value of @ref DMA_interrupts_definition */
212
213 u32 GDMA_ReloadSrc; /*!< Specifies the GDMA automatic source reload .
214 This parameter can be the 0 or 1.(0 : disable / 1 : enable).
215 @note if this value is setted 1, source address register can be automatically
216 reloaded from its initial value at the end of every block for multi-block transfers.
217 this parameter is only valid in multi block transmission mode*/
218
219 u32 GDMA_ReloadDst; /*!< Specifies the GDMA automatic destination reload .
220 This parameter can be the 0 or 1.(0 : disable / 1 : enable).
221 @note if this parameter is set 1, destination address register can be automatically
222 reloaded from its initial value at the end of every block for multi-block transfers.
223 this parameter is only valid in multi block transmission mode*/
224
225 u32 GDMA_LlpDstEn; /*!< Specifies the GDMA whether block chaining is enabled or disabled on the destination
226 side only.
227 @note this parameter is only valid in multi-block transmission mode*/
228
229 u32 GDMA_LlpSrcEn; /*!< Specifies the GDMA whether block chaining is enabled or disabled on the source
230 side only.
231 @note this parameter is only valid in multi-block transmission mode*/
232
233 u32 GDMA_SrcHandshakeInterface; /*!< Specifies the GDMA hardware handshaking interface for the source
234 peripheral of a GDMA channel.
235 This parameter can be a value of @ref DMA_HS_Interface_definition */
236
237 u32 GDMA_DstHandshakeInterface; /*!< Specifies the GDMA hardware handshaking interface for the destination
238 peripheral of a GDMA channel.
239 This parameter can be a value of @ref DMA_HS_Interface_definition */
240
241 u32 MuliBlockCunt; /*!< Specifies the GDMA Multi-block counter.
242 This parameter is used in multi-block transmission.*/
243
244 u32 MaxMuliBlock; /*!< Specifies the GDMA Max block number in Multi-block transmission.
245 This parameter is used in multi-block transmission.*/
246 u32 SecureTransfer; /*!< Specifies the GDMA secure transmission.
247 This parameter is used in secure world of trustzone.*/
248 } GDMA_InitTypeDef, *PGDMA_InitTypeDef;
249
250 /**
251 * @brief GDMA LLI ELE structure definition
252 */
253 typedef struct {
254 u32 Sarx; /*!< Specifies the GDMA channel x Source Address Register (SARx) value field of a block descriptor
255 in block chaining.
256 This parameter stores the source address of the current block transfer.*/
257
258 u32 Darx; /*!< Specifies the GDMA channel x Destination Address Register(DARx) value field of a block descriptor
259 in block chaining.
260 This parameter stores the destination address of the current block transfer.*/
261
262 u32 Llpx; /*!< Specifies the GDMA channel x Linked List Pointer Register(LLPx) value field of a block descriptor
263 in block chaining.
264 This parameter is a address, which points to the next block descriptor.*/
265
266 u32 CtlxLow; /*!< Specifies the GDMA channel x Control Register(CTRx) Low 32 bit value field of a block descriptor
267 in block chaining.
268 This parameter stores the DMA control parameters of the current block transfer.*/
269
270 u32 CtlxUp; /*!< Specifies the GDMA channel x Control Register(CTRx) High 32 bit value field of a block descriptor
271 in block chaining.
272 This parameter stores the DMA control parameters of the current block transfer.*/
273
274 u32 Temp; /*!< Specifies the reserved GDMA channel x register value field of a block descriptor
275 in block chaining.*/
276 }GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
277
278 /**
279 * @brief GDMA CH LLI structure definition
280 */
281 struct GDMA_CH_LLI {
282 GDMA_CH_LLI_ELE LliEle; /*!< Specifies the GDMA Linked List Item Element structure field of Linked List Item
283 in block chaining.
284 This structure variable stores the necessary parameters of a block descriptor.*/
285
286 u32 BlockSize; /*!< Specifies the GDMA block size of one block in block chaining.
287 This parameter indicates the block size of the current block transfer.*/
288
289 struct GDMA_CH_LLI *pNextLli; /*!< Specifies the GDMA Linked List Item pointer.
290 This parameter stores the address pointing to the next Linked List Item
291 in block chaining.*/
292 };
293
294 /**
295 * @}
296 */
297
298 /** @defgroup GDMA_Exported_Constants GDMA Exported Constants
299 * @{
300 */
301 #if defined (ARM_CORE_CM4)
302 #define MAX_GDMA_INDX (0)
303 #define MAX_GDMA_CHNL (5)
304 #else
305 #define MAX_GDMA_INDX (0)
306 #define MAX_GDMA_CHNL (3)
307 #endif
308 #define IS_GDMA_ChannelNum(NUM) ((NUM) <= MAX_GDMA_CHNL)
309 #define IS_GDMA_Index(NUM) ((NUM) <= MAX_GDMA_INDX)
310
311 /** @defgroup GDMA_data_transfer_direction GDMA Data Transfer Direction
312 * @{
313 */
314 #define TTFCMemToMem ((u32)0x00000000)
315 #define TTFCMemToPeri ((u32)0x00000001)
316 #define TTFCPeriToMem ((u32)0x00000002)
317 #define TTFCPeriToPeri ((u32)0x00000003)
318 #define TTFCPeriToMem_PerCtrl ((u32)0x00000004)
319 #define IS_GDMA_DIR(DIR) (((DIR) == TTFCMemToMem) || \
320 ((DIR) == TTFCMemToPeri) || \
321 ((DIR) == TTFCPeriToMem) ||\
322 ((DIR) == TTFCPeriToPeri) ||\
323 ((DIR) == TTFCPeriToMem_PerCtrl))
324
325 /**
326 * @}
327 */
328
329 /** @defgroup GDMA_source_data_size GDMA Source Data Size
330 * @{
331 */
332 #define TrWidthOneByte ((u32)0x00000000)
333 #define TrWidthTwoBytes ((u32)0x00000001)
334 #define TrWidthFourBytes ((u32)0x00000002)
335 #define IS_GDMA_DATA_SIZE(SIZE) (((SIZE) == TrWidthOneByte) || \
336 ((SIZE) == TrWidthTwoBytes) || \
337 ((SIZE) == TrWidthFourBytes))
338 /**
339 * @}
340 */
341
342 /** @defgroup GDMA_Msize GDMA Msize
343 * @{
344 */
345 #define MsizeOne ((u32)0x00000000)
346 #define MsizeFour ((u32)0x00000001)
347 #define MsizeEight ((u32)0x00000002)
348 #define MsizeSixteen ((u32)0x00000003)
349 #define IS_GDMA_MSIZE(SIZE) (((SIZE) == MsizeOne) || \
350 ((SIZE) == MsizeFour) || \
351 ((SIZE) == MsizeEight)||\
352 ((SIZE) == MsizeSixteen))
353
354
355 /**
356 * @}
357 */
358
359 /** @defgroup GDMA_incremented_mode GDMA Source Incremented Mode
360 * @{
361 */
362 #define IncType ((u32)0x00000000)
363 #define DecType ((u32)0x00000001)
364 #define NoChange ((u32)0x00000002)
365 #define IS_GDMA_IncMode(STATE) (((STATE) == IncType) || \
366 ((STATE) == DecType) || \
367 ((STATE) == NoChange))
368
369 /**
370 * @}
371 */
372
373 /** @defgroup GDMA_interrupts_definition GDMA Interrupts Definition
374 * @{
375 */
376 #define TransferType ((u32)0x00000001)
377 #define BlockType ((u32)0x00000002)
378 #define SrcTransferType ((u32)0x00000004)
379 #define DstTransferType ((u32)0x00000008)
380 #define ErrType ((u32)0x000000010)
381
382 #define IS_GDMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFE0) == 0x00) && ((IT) != 0x00))
383 /**
384 * @}
385 */
386
387 /** @defgroup GDMA_Reload_definition GDMA Reload Definition
388 * @{
389 */
390 #define CLEAN_RELOAD_SRC ((u32)0x00000001)
391 #define CLEAN_RELOAD_DST ((u32)0x00000002)
392 #define CLEAN_RELOAD_SRC_DST ((u32)0x00000003)
393 /**
394 * @}
395 */
396
397 /** @defgroup GDMA0_HS_Interface_definition GDMA HandShake Interface Definition
398 * @{
399 */
400 #define GDMA_HANDSHAKE_INTERFACE_UART0_TX (0)
401 #define GDMA_HANDSHAKE_INTERFACE_UART0_RX (1)
402 #define GDMA_HANDSHAKE_INTERFACE_UART1_TX (2)
403 #define GDMA_HANDSHAKE_INTERFACE_UART1_RX (3)
404 #define GDMA_HANDSHAKE_INTERFACE_UART3_TX (6)
405 #define GDMA_HANDSHAKE_INTERFACE_UART3_RX (7)
406 #define GDMA_HANDSHAKE_INTERFACE_SPI0_TX (4)
407 #define GDMA_HANDSHAKE_INTERFACE_SPI0_RX (5)
408 #define GDMA_HANDSHAKE_INTERFACE_SPI1_TX (6)
409 #define GDMA_HANDSHAKE_INTERFACE_SPI1_RX (7)
410 #define GDMA_HANDSHAKE_INTERFACE_I2C0_TX (2)
411 #define GDMA_HANDSHAKE_INTERFACE_I2C0_RX (3)
412 #define GDMA_HANDSHAKE_INTERFACE_ADC_RX (5)
413 #define GDMA_HANDSHAKE_INTERFACE_AUDIO_TX (10)
414 #define GDMA_HANDSHAKE_INTERFACE_AUDIO_RX (11)
415 #define GDMA_HANDSHAKE_INTERFACE_USI0_TX (8)
416 #define GDMA_HANDSHAKE_INTERFACE_USI0_RX (9)
417 #define GDMA_HANDSHAKE_INTERFACE_SGPIO_TX (4)
418 /**
419 * @}
420 */
421 /** @defgroup GDMA1_HS_Interface_definition GDMA HandShake Interface Definition.
422 ** @brief this definition is not supported in the amebaD
423 * @{
424 */
425 #define GDMA_HANDSHAKE_TIMER_CAPTURE_UP (0)
426 #define GDMA_HANDSHAKE_TIMER_CAPTURE_CH0 (1)
427 #define GDMA_HANDSHAKE_TIMER_PWM_UP (2)
428 #define GDMA_HANDSHAKE_TIMER_PWM_CH0 (3)
429 #define GDMA_HANDSHAKE_TIMER_PWM_CH1 (4)
430 #define GDMA_HANDSHAKE_TIMER_PWM_CH2 (5)
431 #define GDMA_HANDSHAKE_TIMER_PWM_CH3 (6)
432 #define GDMA_HANDSHAKE_TIMER_PWM_CH4 (7)
433 #define GDMA_HANDSHAKE_TIMER_PWM_CH5 (8)
434 /**
435 * @}
436 */
437
438 /**
439 * @}
440 */
441
442
443 /** @defgroup GDMA_Exported_Functions GDMA Exported Functions
444 * @{
445 */
446 _LONG_CALL_ void GDMA_StructInit(PGDMA_InitTypeDef GDMA_InitStruct);
447 _LONG_CALL_ void GDMA_Init(u8 GDMA_Index, u8 GDMA_ChNum, PGDMA_InitTypeDef GDMA_InitStruct);
448 _LONG_CALL_ void GDMA_SetLLP(u8 GDMA_Index, u8 GDMA_ChNum, u32 MultiBlockCount, struct GDMA_CH_LLI *pGdmaChLli);
449 _LONG_CALL_ void GDMA_Cmd(u8 GDMA_Index, u8 GDMA_ChNum, u32 NewState);
450 _LONG_CALL_ void GDMA_INTConfig(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT, u32 NewState);
451 _LONG_CALL_ u32 GDMA_ClearINTPendingBit(u8 GDMA_Index, u8 GDMA_ChNum, u32 GDMA_IT);
452 _LONG_CALL_ u32 GDMA_ClearINT(u8 GDMA_Index, u8 GDMA_ChNum);
453 _LONG_CALL_ void GDMA_ChCleanAutoReload(u8 GDMA_Index, u8 GDMA_ChNum, u32 CleanType);
454
455 _LONG_CALL_ void GDMA_SetSrcAddr(u8 GDMA_Index, u8 GDMA_ChNum, u32 SrcAddr);
456 _LONG_CALL_ u32 GDMA_GetSrcAddr(u8 GDMA_Index, u8 GDMA_ChNum);
457 _LONG_CALL_ u32 GDMA_GetDstAddr(u8 GDMA_Index, u8 GDMA_ChNum);
458 _LONG_CALL_ void GDMA_SetDstAddr(u8 GDMA_Index, u8 GDMA_ChNum, u32 DstAddr);
459 _LONG_CALL_ void GDMA_SetBlkSize(u8 GDMA_Index, u8 GDMA_ChNum, u32 BlkSize);
460 _LONG_CALL_ u32 GDMA_GetBlkSize(u8 GDMA_Index, u8 GDMA_ChNum);
461
462 _LONG_CALL_ BOOL GDMA_ChnlRegister (u8 GDMA_Index, u8 GDMA_ChNum);
463 _LONG_CALL_ void GDMA_ChnlUnRegister (u8 GDMA_Index, u8 GDMA_ChNum);
464 _LONG_CALL_ u8 GDMA_ChnlAlloc(u32 GDMA_Index, IRQ_FUN IrqFun, u32 IrqData, u32 IrqPriority);
465 _LONG_CALL_ void GDMA_ChnlFree(u8 GDMA_Index, u8 GDMA_ChNum);
466 _LONG_CALL_ u8 GDMA_GetIrqNum(u8 GDMA_Index, u8 GDMA_ChNum);
467
468
469 /**
470 * @}
471 */
472
473 /* Registers Definitions ----------------------------------------------------------------*/
474 /** @defgroup GDMA_Register_Definitions GDMA Register Definitions
475 * @{
476 */
477 /**************************************************************************//**
478 * @defgroup GDMA_CTL
479 * @{
480 *****************************************************************************/
481 /******************** Bits definition for CTL register *******************/
482 #define BIT_CTLX_LO_INT_EN ((u32)(0x00000001 << 0)) /*Lower word Bit[0].Interrupt Enable Bit.*/
483 #define BIT_CTLX_LO_LLP_DST_EN ((u32)(0x00000001 << 27)) /*Lower word Bit[27].Block chaining is enabled on the destination side only*/
484 #define BIT_CTLX_LO_LLP_SRC_EN ((u32)(0x00000001 << 28)) /*Lower word Bit[28].Block chaining is enabled on the source side only*/
485
486 #define BIT_CTLX_LO_DST_TR_WIDTH ((u32)(0x00000007 << 1)) /*Lower word Bit[3:1].Destination Transfer Width*/
487 #define BIT_CTLX_LO_SRC_TR_WIDTH ((u32)(0x00000007 << 4)) /*Lower word Bit[6:4].Source Transfer Width*/
488
489 #define BIT_CTLX_LO_DINC ((u32)(0x00000003 << 7)) /*Lower word Bit[8:7].Destination Address Increment*/
490 #define BIT_CTLX_LO_SINC ((u32)(0x00000003 << 9)) /*Lower word Bit[10:9].Source Address Increment*/
491
492 #define BIT_CTLX_LO_DEST_MSIZE ((u32)(0x00000007 << 11)) /*Lower word Bit[13:11].Destination Burst Transaction Length*/
493 #define BIT_CTLX_LO_SRC_MSIZE ((u32)(0x00000007 << 14)) /*Lower word Bit[16:14].Source Burst Transaction Length*/
494
495 #define BIT_CTLX_LO_SRC_GATHER_EN ((u32)(0x00000001 << 17)) /*Lower word Bit[17].Source gather enable bit*/
496 #define BIT_CTLX_LO_DST_SCATTER_EN ((u32)(0x00000001 << 18)) /*Lower word Bit[18].Destination gather enable bit*/
497
498 #define BIT_CTLX_LO_TT_FC ((u32)(0x00000007 << 20)) /*Lower word Bit[22:20].Transfer Type and Flow Control*/
499
500 #define BIT_CTLX_LO_DMS ((u32)(0x00000003 << 23)) /*Lower word Bit[24:23].Destination Master Select*/
501 #define BIT_CTLX_LO_SMS ((u32)(0x00000003 << 25)) /*Lower word Bit[26:25].Source Master Select*/
502
503 //#define BIT_CTLX_UP_DONE ((u32)(0x00000001 << 12)) /*Upper word Bit[12].Done bit, RTK DMAC dont have this bit */
504 #define BIT_CTLX_UP_BLOCK_BS ((u32)(0x00000FFF << 0)) /*Upper word Bit[11:0].Block Transfer Size.*/
505 /** @} */
506
507 /**************************************************************************//**
508 * @defgroup GDMA_CFG
509 * @{
510 *****************************************************************************/
511 /******************** Bits definition for CFG register *******************/
512 #define BIT_CFGX_LO_RELOAD_SRC ((u32)(0x00000001 << 30)) /*Lower word Bit[30].Automatic Source Reload bit*/
513 #define BIT_CFGX_LO_RELOAD_DST ((u32)(0x00000001 << 31)) /*Lower word Bit[31].Automatic Destination Reload bit*/
514
515 #define BIT_CFGX_UP_SEC_DISABLE ((u32)(0x00000001 << 3)) /*Upper word Bit[10:7]. write 0 to enable secure transfer, default is 0 */
516 #define BIT_CFGX_UP_SRC_PER ((u32)(0x0000000F << 7)) /*Upper word Bit[10:7].hardware handshaking interface for source peripheral*/
517 #define BIT_CFGX_UP_DEST_PER ((u32)(0x0000000F << 11)) /*Upper word Bit[14:11].hardware handshaking interface for destination peripheral*/
518 #define BIT_CFGX_UP_FIFO_MODE ((u32)(0x00000001<<1 )) /*Upper word Bit[1].hardware FIFO Mode Select, write 1 to enable*/
519 /** @} */
520
521 /**
522 * @}
523 */
524
525 /**
526 * @}
527 */
528
529 /**
530 * @}
531 */
532
533 /* Register Address Offset Definitions --------------------------------------------------------*/
534 /******************** Address Offset Definition for GDMA Registers *******************/
535 #define REG_GDMA_CH_OFF (0x058) /*address space value between two DMA channels*/
536 #define REG_GDMA_CH_SAR (0x000) /*Source Address Register(SAR) address offset*/
537 #define REG_GDMA_CH_DAR (0x008) /*Destination Address Register(DAR) address offset*/
538 #define REG_GDMA_CH_LLP (0x010) /*Linked List Pointer(LLP) Register address offset*/
539 #define REG_GDMA_CH_CTL (0x018) /*Control Register(CTR) address offset*/
540 #define REG_GDMA_CH_SSTAT (0x020) /*Source Status(SSTAT) Register address offset*/
541 #define REG_GDMA_CH_DSTAT (0x028) /*Destination Status(DSTAT) Register address offset*/
542 #define REG_GDMA_CH_SSTATAR (0x030) /*Source Status Address(SSTATA) Register address offset*/
543 #define REG_GDMA_CH_DSTATAR (0x038) /*Destination Status Address(DSTATA) Register address offset*/
544 #define REG_GDMA_CH_CFG (0x040) /*Configuration(CFG) Register address offset*/
545 #define REG_GDMA_CH_SGR (0x048) /*Source Gather Register(SGR) address offset*/
546 #define REG_GDMA_CH_DSR (0x050) /*Destination Scatter Register(DSR) address offset*/
547
548 /********************** Address Offset Definition for Interrupt Raw Status Registers *******************/
549 #define REG_GDMA_RAW_INT_BASE (0x2C0) /*Base address for Interrupt Raw Status Registers*/
550 #define REG_GDMA_RAW_INT_TFR (0x2C0) /*address offset for DMA Transfer Complete Interrupt Raw Status Register(RawTfr)*/
551 #define REG_GDMA_RAW_INT_BLOCK (0x2c8) /*address offset for Block Transfer Complete Interrupt Raw Status Register(RawBlock)*/
552 #define REG_GDMA_RAW_INT_SRC_TRAN (0x2D0) /*address offset for Source Transaction Complete Interrupt Raw Status Register(RawSrcTran)*/
553 #define REG_GDMA_RAW_INT_DST_TRAN (0x2D8) /*address offset for Destination Transaction Complete Interrupt Raw Status Register(RawDstTran)*/
554 #define REG_GDMA_RAW_INT_ERR (0x2E0) /*address offset for Error Interrupt Raw Status Register(RawDstTran)*/
555
556 /********************** Address Offset Definition for Interrupt Status Registers *******************/
557 #define REG_GDMA_STATUS_INT_BASE (0x2E8) /*Base address for Interrupt Status Registers*/
558 #define REG_GDMA_STATUS_INT_TFR (0x2E8) /*address offset for DMA Transfer Complete Interrupt Status Register(StatusTfr)*/
559 #define REG_GDMA_STATUS_INT_BLOCK (0x2F0) /*address offset for Block Transfer Complete Interrupt Status Register(StatusBlock)*/
560 #define REG_GDMA_STATUS_INT_SRC_TRAN (0x2F8) /*address offset for Source Transaction Complete Interrupt Status Register(StatusSrcTran)*/
561 #define REG_GDMA_STATUS_INT_DST_TRAN (0x300) /*address offset for Destination Transaction Complete Interrupt Status Register(StatusDstTran)*/
562 #define REG_GDMA_STATUS_INT_ERR (0x308) /*address offset for Error Interrupt Status Register(StatusErr)*/
563
564 /********************** Address Offset Definition for Interrupt Mask Registers *******************/
565 #define REG_GDMA_MASK_INT_BASE (0x310) /*Base address for Interrupt Mask Registers*/
566 #define REG_GDMA_MASK_INT_TFR (0x310) /*address offset for DMA Transfer Complete Interrupt Mask Register(MaskTfr)*/
567 #define REG_GDMA_MASK_INT_BLOCK (0x318) /*address offset for Block Transfer Complete Interrupt Mask Register(MaskBlock)*/
568 #define REG_GDMA_MASK_INT_SRC_TRAN (0x320) /*address offset for Source Transaction Complete Interrupt Mask Register(MaskSrcTran)*/
569 #define REG_GDMA_MASK_INT_DST_TRAN (0x328) /*address offset for Destination Transaction Complete Interrupt Mask Register(MaskDstTran)*/
570 #define REG_GDMA_MASK_INT_INT_ERR (0x330) /*address offset for Error Interrupt Mask Register(MaskErr)*/
571
572 /********************** Address Offset Definition for Interrupt Clear Registers *******************/
573 #define REG_GDMA_CLEAR_INT_BASE (0x338) /*Base address for Interrupt Clear Registers*/
574 #define REG_GDMA_CLEAR_INT_TFR (0x338) /*address offset for DMA Transfer Complete Interrupt Clear Register(ClearTfr)*/
575 #define REG_GDMA_CLEAR_INT_BLOCK (0x340) /*address offset for Block Transfer Complete Interrupt Clear Register(ClearBlock)*/
576 #define REG_GDMA_CLEAR_INT_SRC_TRAN (0x348) /*address offset for Source Transaction Complete Interrupt Clear Register(ClearSrcTran)*/
577 #define REG_GDMA_CLEAR_INT_DST_TRAN (0x350) /*address offset for Destination Transaction Complete Interrupt Clear Register(ClearDstTran)*/
578 #define REG_GDMA_CLEAR_INT_ERR (0x358) /*address offset for Error Interrupt Clear Register(ClearErr)*/
579
580 /********************* Address Offset Definition for Combined Interrupt Status Register ***********/
581 #define REG_GDMA_STATUS_INT (0x360) /*address offset for Combined Interrupt Status Register*/
582
583 /********************** Address Offset Definition for Software Handshaking Registers *************/
584 #define REG_GDMA_REQ_SRC (0x368) /*address offset for Source Software Transaction Request Register(ReqSrcReg)*/
585 #define REG_GDMA_REQ_DST (0x370) /*address offset for Destination Software Transaction Request Register(ReqDstReg)*/
586 #define REG_GDMA_REQ_SGL_REQ (0x378) /*address offset for Single Source Transaction Request Register(SglReqSrcReg)*/
587 #define REG_GDMA_REQ_DST_REQ (0x380) /*address offset for Single Destination Transaction Request Register(SglReqDstReg)*/
588 #define REG_GDMA_REQ_LST_SRC (0x388) /*address offset for Last Source Transaction Request Register(LstSrcReg)*/
589 #define REG_GDMA_REQ_LST_DST (0x390) /*address offset for Last Destination Transaction Request Register(LstDstReg)*/
590
591 /********************** Address Offset Definition for Miscellaneous Registers *************/
592 #define REG_GDMA_DMAC_CFG (0x398) /*address offset for DMA Configuration Register(DmaCfgReg)*/
593 #define REG_GDMA_CH_EN (0x3A0) /*address offset for DMA Channel Enable Register(ChEnReg)*/
594 #define REG_GDMA_DMA_ID (0x3A8) /*address offset for DMA ID Register(DmaIdReg)*/
595 #define REG_GDMA_DMA_TEST (0x3B0) /*address offset for DMA Test Register(DmaTestReg)*/
596 #define REG_GDMA_DMA_COM_PARAMS6 (0x3C8) /*address offset for DMA Component Parameters Register 6(DMA_COMP_PARAMS_6)*/
597 #define REG_GDMA_DMA_COM_PARAMS5 (0x3D0) /*address offset for DMA Component Parameters Register 5(DMA_COMP_PARAMS_5)*/
598 #define REG_GDMA_DMA_COM_PARAMS4 (0x3D8) /*address offset for DMA Component Parameters Register 4(DMA_COMP_PARAMS_4)*/
599 #define REG_GDMA_DMA_COM_PARAMS3 (0x3E0) /*address offset for DMA Component Parameters Register 3(DMA_COMP_PARAMS_3)*/
600 #define REG_GDMA_DMA_COM_PARAMS2 (0x3E8) /*address offset for DMA Component Parameters Register 2(DMA_COMP_PARAMS_2)*/
601 #define REG_GDMA_DMA_COM_PARAMS1 (0x3F0) /*address offset for DMA Component Parameters Register 1(DMA_COMP_PARAMS_1)*/
602 #define REG_GDMA_DMA_COM_PARAMS0 (0x3F8) /*address offset for DMA Component ID Register. Bit[63:32]: DMA_COMP_VERSION
603 Bit[31:0]:DMA_COMP_TYPE*/
GDMA_BurstEnable(u32 ch_num,u32 NewState)604 __STATIC_INLINE void GDMA_BurstEnable(u32 ch_num, u32 NewState) {
605 GDMA_TypeDef* GDMA = ((GDMA_TypeDef *) GDMA_BASE);
606 u32 ValTemp = 0;
607
608 if (TrustZone_IsSecure()) {
609 GDMA = ((GDMA_TypeDef *) GDMA0S_REG_BASE);
610 }
611
612 ValTemp=GDMA->CH[ch_num].CFG_HIGH;
613
614 if (NewState == ENABLE) {
615 ValTemp |=BIT_CFGX_UP_FIFO_MODE;
616 } else {
617 ValTemp &= (~ BIT_CFGX_UP_FIFO_MODE);
618 }
619
620 GDMA->CH[ch_num].CFG_HIGH=ValTemp;
621 }
622 /* Other Definitions -------------------------------------------------------------------*/
623 #endif //_RTL8710B_GDMA_H_
624
625 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
626