1 /** 2 ****************************************************************************** 3 * @file rtl8721d_i2c.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the I2C firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8710B_I2C_H_ 20 #define _RTL8710B_I2C_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @addtogroup I2C I2C 27 * @{ 28 */ 29 30 /** @addtogroup I2C 31 * @verbatim 32 ***************************************************************************************** 33 * Introduction 34 ***************************************************************************************** 35 * I2C0: 36 * - Base Address: I2C0_DEV 37 * - IPclk: 62.5Mhz 38 * - Speed: Standard (up to 100 kHz) and Fast (up to 400 kHz) Modes 39 * - Address: 7/10-bit Address Mode 40 * - SocPs: SleepMode (clock gating & power gating) 41 * - Slave: Slave0 42 * - IRQ: I2C0_IRQ 43 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_I2C0_TX 44 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_I2C0_RX 45 * 46 ***************************************************************************************** 47 * How to use Normal I2C 48 ***************************************************************************************** 49 * To use the normal i2c mode, the following steps are mandatory: 50 * 51 * 1. Enable peripheral clock using the follwoing functions.(it is enabled by default) 52 * RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE); 53 * 54 * 2. configure the I2C pinmux. 55 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C) 56 * 57 * 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports 58 * I2C_StructInit() 59 * 60 * 4. Init Hardware use step3 parameters: 61 * I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct) 62 * 63 * 5. Enable the NVIC and the corresponding interrupt using following function if you need 64 * to use interrupt mode. 65 * I2C_INTConfig(): I2C IRQ Mask set 66 * InterruptRegister(): register the i2c irq handler 67 * InterruptEn(): Enable the NVIC interrupt 68 * 69 * 6. Enable i2c module using I2C_Cmd(). 70 * 71 ***************************************************************************************** 72 * How to use i2c in DMA Register mode 73 ***************************************************************************************** 74 * To use the i2c in DMA mode, the following steps are mandatory: 75 * 76 * 1. Enable peripheral clock using the follwoing functions.(it is enabled by default) 77 * RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE); 78 * 79 * 2. configure the I2C pinmux. 80 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C) 81 * 82 * 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports 83 * I2C_StructInit() 84 * 85 * 4. Init Hardware use step3 parameters: 86 * I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct) 87 * 88 * 5. Enable i2c module using I2C_Cmd(). 89 * 90 * 6. GDMA related configurations(source address/destination address/block size etc.) 91 * I2C_TXGDMA_Init():Init and Enable I2C TX GDMA 92 * I2C_RXGDMA_Init():Init and Enable I2C RX GDMA 93 * 94 * 7. I2C DMA Mode Register mode set. 95 * I2C_DmaMode1Config():Configures the I2Cx Control Register DMA mode 96 * 97 * 8. Active the I2C TX/RX DMA Request using I2C_DMAControl(). 98 * 99 ***************************************************************************************** 100 * How to use i2c in Sleep mode 101 ***************************************************************************************** 102 * To use the i2c in Low Power mode, the following steps are mandatory: 103 * 104 * 1. Enable peripheral clock using the follwoing functions.(it is enabled by default) 105 * RCC_PeriphClockCmd(APBPeriph_I2Cx, APBPeriph_I2Cx_CLOCK, ENABLE); 106 * 107 * 2. configure the I2C pinmux. 108 * Pinmux_Config(Pin_Num, PINMUX_FUNCTION_I2C) 109 * 110 * 3. Program Role, Address Mode, Speed Mode, I2C CLK, Slave address, Threshold, Feature Supports 111 * I2C_StructInit() 112 * 113 * 4. Init Hardware use step3 parameters: 114 * I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct) 115 * 116 * 5. Enable the NVIC and the corresponding interrupt using following function if you need 117 * to use interrupt mode. 118 * I2C_INTConfig(): I2C IRQ Mask set 119 * InterruptRegister(): register the i2c irq handler 120 * InterruptEn(): Enable the NVIC interrupt 121 * 122 * 6. Enable address matching interrupts for wake up 123 * I2C_INTConfig(): I2C Addr match IRQ Mask set 124 * BIT_IC_INTR_MASK_M_ADDR_1_MATCH refer to refer to I2C Slave0 Address Match 125 * 126 * 7. Set wake up event using the follwoing functions. 127 * SOCPS_SetWakeEvent() 128 * 129 * 8. Set power ext option BIT_SYSON_PMOPT_SLP_ANACK_EN to Enable ANA clock and 130 * BIT_SYSON_PMOPT_SLP_ANACK_SEL to select 4M clock for power save mode, then hardware 131 * will automatically switch to the 4M clock when enter sleep state. 132 * SOCPS_PWROptionExt() 133 * 134 * 9. Clear address matching interrupts after address matching interrupts 135 * I2C_WakeUp() 136 * 137 ***************************************************************************************** 138 * @endverbatim 139 */ 140 141 /* Exported types --------------------------------------------------------*/ 142 /** @defgroup I2C_Exported_Types I2C Exported Types 143 * @{ 144 */ 145 146 /** 147 * @brief I2C Init structure definition 148 */ 149 typedef struct { 150 u32 I2CIdx; /*!< Specifies the I2C Device Index. 151 This parameter should be 0 */ 152 153 u32 I2CMaster; /*!< Specifies the I2C Role. 154 This parameter can be a value of @ref I2C_Role_definitions */ 155 156 u32 I2CAddrMod; /*!< Specifies the I2C Addressing Mode. 157 This parameter can be a value of @ref I2C_Addr_Mode_definitions */ 158 159 u32 I2CSpdMod; /*!< Specifies the I2C Speed Mode. Now the circuit don't support High Speed Mode. 160 This parameter can be a value of @ref I2C_Speed_Mode_definitions */ 161 162 u32 I2CRXTL; /*!< Specifies the I2C RX FIFO Threshold. It controls the level of 163 entries(or above) that triggers the RX_FULL interrupt. 164 This parameter must be set to a value in the 0-255 range. A value of 0 sets 165 the threshold for 1 entry, and a value of 255 sets the threshold for 256 entry*/ 166 167 u32 I2CTXTL; /*!< Specifies the I2C TX FIFO Threshold.It controls the level of 168 entries(or below) that triggers the TX_EMPTY interrupt. 169 This parameter must be set to a value in the 0-255 range. A value of 0 sets 170 the threshold for 0 entry, and a value of 255 sets the threshold for 255 entry*/ 171 u32 I2CMstReSTR; /*!< Specifies the I2C Restart Support of Master. */ 172 173 u32 I2CMstGC; /*!< Specifies the I2C General Call Support of Master. */ 174 175 u32 I2CMstStartB; /*!< Specifies the I2C Start Byte Support of Master. */ 176 177 u32 I2CSlvNoAck; /*!< Specifies the I2C Slave No Ack Support. */ 178 179 u32 I2CSlvAckGC; /*!< Specifies the I2C Slave Acks to General Call. */ 180 181 u32 I2CAckAddr; /*!< Specifies the I2C Target Address in I2C Master Mode or 182 Ack Address in I2C Slave0 Mode. 183 This parameter must be set to a value in the 0-127 range if the I2C_ADDR_7BIT 184 is selected or 0-1023 range if the I2C_ADDR_10BIT is selected. */ 185 186 u32 I2CSlvSetup; /*!< Specifies the I2C SDA Setup Time. It controls the amount of time delay 187 introduced in the rising edge of SCL��relative to SDA changing��by holding SCL low 188 when I2C Device operating as a slave transmitter, in units of ic_clk period. 189 This parameter must be set to a value in the 0-255 range. It must be set larger than I2CSdaHd */ 190 191 u32 I2CSdaHd; /*!< Specifies the I2C SDA Hold Time. It controls the amount of 192 hold time on the SDA signal after a negative edge of SCL in both master 193 and slave mode, in units of ic_clk period. 194 This parameter must be set to a value in the 0-0xFFFF range. */ 195 196 u32 I2CClk; /*!< Specifies the I2C Bus Clock (in kHz). It is closely related to I2CSpdMod */ 197 198 u32 I2CIPClk; /*!< Specifies the I2C IP Clock (in Hz). */ 199 200 u32 I2CFilter; /*!< Specifies the I2C SCL/SDA Spike Filter. */ 201 202 u32 I2CTxDMARqLv; /*!< Specifies the I2C TX DMA Empty Level. dma_tx_req signal is generated when 203 the number of valid data entries in the transmit FIFO is equal to or below the DMA 204 Transmit Data Level Register. The value of DMA Transmit Data Level Register is equal 205 to this value. This parameter must be set to a value in the 0-31 range. */ 206 207 u32 I2CRxDMARqLv; /*!< Specifies the I2C RX DMA Full Level. dma_rx_req signal is generated when 208 the number of valid data entries in the transmit FIFO is equal to or above the DMA 209 Receive Data Level Register. The value of DMA Receive Data Level Register is equal to 210 this value+1. This parameter must be set to a value in the 0-31 range. */ 211 212 u32 I2CDMAMod; /*!< Specifies the I2C DMA Mode. 213 This parameter can be a value of @ref I2C_DMA_Mode_definitions */ 214 215 u32 I2CAckAddr1; /*!< Specifies the I2C Ack Address in I2C Slave1 Mode. I2C Slave1 only 216 support I2C_ADDR_7BIT mode. This parameter must be set to a value in the 0-127 range. */ 217 }I2C_InitTypeDef; 218 /** 219 * @} 220 */ 221 222 /* Exported constants --------------------------------------------------------*/ 223 /** @defgroup I2C_Exported_Constants I2C Exported Constants 224 * @{ 225 */ 226 227 /** @defgroup I2C_Peripheral_definitions 228 * @{ 229 */ 230 #define IS_I2C_ALL_PERIPH(PERIPH) ((PERIPH) == I2C0_DEV) 231 /** 232 * @} 233 */ 234 235 /** @defgroup I2C_Addr_Mode_definitions 236 * @{ 237 */ 238 #define I2C_ADDR_7BIT ((u32)0x00000000) 239 #define I2C_ADDR_10BIT ((u32)0x00000001) 240 #define IS_I2C_ADDR_MODE(MODE) (((MODE) == I2C_ADDR_7BIT) || \ 241 ((MODE) == I2C_ADDR_10BIT)) 242 /** 243 * @} 244 */ 245 246 /** @defgroup I2C_Speed_Mode_definitions 247 * @{ 248 */ 249 #define I2C_SS_MODE ((u32)0x00000001) 250 #define I2C_FS_MODE ((u32)0x00000002) 251 #define I2C_HS_MODE ((u32)0x00000003) 252 #define IS_I2C_SPEED_MODE(MODE) (((MODE) == I2C_SS_MODE) || \ 253 ((MODE) == I2C_FS_MODE) || \ 254 ((MODE) == I2C_HS_MODE)) 255 /** 256 * @} 257 */ 258 259 /** @defgroup I2C_Role_definitions 260 * @{ 261 */ 262 #define I2C_SLAVE_MODE ((u32)0x00000000) 263 #define I2C_MASTER_MODE ((u32)0x00000001) 264 /** 265 * @} 266 */ 267 268 /** @defgroup I2C_DMA_Mode_definitions 269 * @{ 270 */ 271 #define I2C_DMA_LEGACY ((u32)0x00000000) 272 #define I2C_DMA_REGISTER ((u32)0x00000001) 273 #define I2C_DMA_DESCRIPTOR ((u32)0x00000002) 274 #define IS_I2C_DMA_MODE(MODE) (((MODE) == I2C_DMA_LEGACY) || \ 275 ((MODE) == I2C_DMA_REGISTER) || \ 276 ((MODE) == I2C_DMA_DESCRIPTOR)) 277 /** 278 * @} 279 */ 280 281 /** @defgroup I2C_DMA_DATA_LENGTH 282 * @{ 283 */ 284 #define IS_I2C_DMA_DATA_LEN(LENGTH) ((LENGTH) <= 0xFFFF) 285 /** 286 * @} 287 */ 288 289 /** 290 * @} 291 */ 292 293 /* Exported functions --------------------------------------------------------*/ 294 /** @defgroup I2C_Exported_Functions I2C Exported Functions 295 * @{ 296 */ 297 298 /** @defgroup I2C_Exported_Normal_Functions I2C Exported Normal Functions 299 * @{ 300 */ 301 _LONG_CALL_ void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef* I2C_InitStruct); 302 _LONG_CALL_ void I2C_Cmd(I2C_TypeDef *I2Cx, u8 NewState); 303 _LONG_CALL_ void I2C_ClearAllINT(I2C_TypeDef *I2Cx); 304 _LONG_CALL_ u32 I2C_GetRawINT(I2C_TypeDef *I2Cx); 305 _LONG_CALL_ u32 I2C_GetINT(I2C_TypeDef *I2Cx); 306 _LONG_CALL_ u8 I2C_CheckFlagState(I2C_TypeDef *I2Cx, u32 I2C_FLAG); 307 _LONG_CALL_ void I2C_INTConfig(I2C_TypeDef *I2Cx, u32 I2C_IT, u32 NewState); 308 _LONG_CALL_ void I2C_ClearINT(I2C_TypeDef *I2Cx, u32 INTrAddr); 309 _LONG_CALL_ void I2C_SetSpeed(I2C_TypeDef *I2Cx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk); 310 _LONG_CALL_ void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); 311 _LONG_CALL_ u8 I2C_ReceiveData(I2C_TypeDef *I2Cx); 312 /** 313 * @} 314 */ 315 316 /** @defgroup I2C_Exported_Master_Functions I2C Exported Master Functions 317 * @{ 318 */ 319 _LONG_CALL_ void I2C_MasterSendNullData(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR); 320 _LONG_CALL_ void I2C_MasterSend(I2C_TypeDef *I2Cx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR); 321 _LONG_CALL_ void I2C_MasterWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len); 322 _LONG_CALL_ void I2C_MasterReadDW(I2C_TypeDef *I2Cx, u8* pBuf, u8 len); 323 _LONG_CALL_ u8 I2C_MasterRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len); 324 _LONG_CALL_ void I2C_MasterRepeatRead(I2C_TypeDef* I2Cx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen); 325 _LONG_CALL_ void I2C_SetSlaveAddress(I2C_TypeDef *I2Cx, u16 Address); 326 /** 327 * @} 328 */ 329 330 /** @defgroup I2C_Exported_Slave_Functions I2C Exported Slave Functions 331 * @{ 332 */ 333 _LONG_CALL_ void I2C_SlaveWrite(I2C_TypeDef *I2Cx, u8* pBuf, u8 len); 334 _LONG_CALL_ void I2C_SlaveRead(I2C_TypeDef *I2Cx, u8* pBuf, u8 len); 335 _LONG_CALL_ void I2C_SlaveSend(I2C_TypeDef *I2Cx, u8 Data); 336 /** 337 * @} 338 */ 339 340 /** @defgroup I2C_Exported_DMA_Functions I2C Exported DMA Functions 341 * @{ 342 */ 343 _LONG_CALL_ void I2C_DMAControl(I2C_TypeDef *I2Cx, u32 DmaCtrl, u8 NewState); 344 _LONG_CALL_ void I2C_DmaMode1Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen); 345 _LONG_CALL_ void I2C_DmaMode2Config(I2C_TypeDef *I2Cx, u32 I2C_DmaCmd, u32 I2C_DmaBLen); 346 _LONG_CALL_ BOOL I2C_TXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pTxBuf, int TxCount); 347 _LONG_CALL_ BOOL I2C_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8 *pRxBuf, int RxCount); 348 /** 349 * @} 350 */ 351 352 /** @defgroup I2C_Exported_PowerSave_Functions I2C Exported PowerSave Functions 353 * @{ 354 */ 355 _LONG_CALL_ void I2C_Sleep_Cmd(I2C_TypeDef *I2Cx, u32 NewStatus); 356 _LONG_CALL_ void I2C_WakeUp(I2C_TypeDef *I2Cx); 357 /** 358 * @} 359 */ 360 361 /** 362 * @} 363 */ 364 365 366 /* Registers Definitions --------------------------------------------------------*/ 367 /**************************************************************************//** 368 * @defgroup I2C_Register_Definitions I2C Register Definitions 369 * @{ 370 *****************************************************************************/ 371 372 /**************************************************************************//** 373 * @defgroup IC_CON 374 * @{ 375 *****************************************************************************/ 376 #define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE_1 ((u32)0x00000001 << 7) 377 #define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE ((u32)0x00000001 << 6) 378 #define BIT_CTRL_IC_CON_IC_RESTART_EN ((u32)0x00000001 << 5) 379 #define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE ((u32)0x00000001 << 3) 380 #define BIT_CTRL_IC_CON_SPEED ((u32)0x00000003 << 1) 381 #define BIT_CTRL_IC_CON_MASTER_MODE ((u32)0x00000001) 382 /** @} */ 383 384 /**************************************************************************//** 385 * @defgroup IC_TAR 386 * @{ 387 *****************************************************************************/ 388 #define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER ((u32)0x00000001 << 12) 389 #define BIT_CTRL_IC_TAR_SPECIAL ((u32)0x00000001 << 11) 390 #define BIT_CTRL_IC_TAR_GC_OR_START ((u32)0x00000001 << 10) 391 #define BIT_CTRL_IC_TAR ((u32)0x000003ff) 392 /** @} */ 393 394 /**************************************************************************//** 395 * @defgroup IC_SAR 396 * @{ 397 *****************************************************************************/ 398 #define BIT_CTRL_IC_SAR ((u32)0x000003ff) 399 /** @} */ 400 401 /**************************************************************************//** 402 * @defgroup IC_DATA_CMD 403 * @{ 404 *****************************************************************************/ 405 #define BIT_CTRL_IC_DATA_CMD_NULLDATA ((u32)0x00000001 << 11) 406 #define BIT_CTRL_IC_DATA_CMD_RESTART ((u32)0x00000001 << 10) 407 #define BIT_CTRL_IC_DATA_CMD_STOP ((u32)0x00000001 << 9) 408 #define BIT_CTRL_IC_DATA_CMD_CMD ((u32)0x00000001 << 8) 409 #define BIT_CTRL_IC_DATA_CMD_DAT ((u32)0x000000ff) 410 /** @} */ 411 412 /**************************************************************************//** 413 * @defgroup IC_INTR_STAT 414 * @{ 415 *****************************************************************************/ 416 #define BIT_IC_INTR_STAT_R_DMA_I2C_DONE ((u32)0x00000001 << 15) 417 #define BIT_IC_INTR_STAT_R_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */ 418 #define BIT_IC_INTR_STAT_R_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */ 419 #define BIT_IC_INTR_STAT_R_GEN_CALL ((u32)0x00000001 << 11) 420 #define BIT_IC_INTR_STAT_R_START_DET ((u32)0x00000001 << 10) 421 #define BIT_IC_INTR_STAT_R_STOP_DET ((u32)0x00000001 << 9) 422 #define BIT_IC_INTR_STAT_R_ACTIVITY ((u32)0x00000001 << 8) 423 #define BIT_IC_INTR_STAT_R_RX_DONE ((u32)0x00000001 << 7) 424 #define BIT_IC_INTR_STAT_R_TX_ABRT ((u32)0x00000001 << 6) 425 #define BIT_IC_INTR_STAT_R_RD_REQ ((u32)0x00000001 << 5) 426 #define BIT_IC_INTR_STAT_R_TX_EMPTY ((u32)0x00000001 << 4) 427 #define BIT_IC_INTR_STAT_R_TX_OVER ((u32)0x00000001 << 3) 428 #define BIT_IC_INTR_STAT_R_RX_FULL ((u32)0x00000001 << 2) 429 #define BIT_IC_INTR_STAT_R_RX_OVER ((u32)0x00000001 << 1) 430 #define BIT_IC_INTR_STAT_R_RX_UNDER ((u32)0x00000001) 431 /** @} */ 432 433 /**************************************************************************//** 434 * @defgroup IC_INTR_MASK 435 * @{ 436 *****************************************************************************/ 437 #define BIT_IC_INTR_MASK_M_DMA_I2C_DONE ((u32)0x00000001 << 15) 438 #define BIT_IC_INTR_MASK_M_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */ 439 #define BIT_IC_INTR_MASK_M_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */ 440 #define BIT_IC_INTR_MASK_M_GEN_CALL ((u32)0x00000001 << 11) 441 #define BIT_IC_INTR_MASK_M_START_DET ((u32)0x00000001 << 10) 442 #define BIT_IC_INTR_MASK_M_STOP_DET ((u32)0x00000001 << 9) 443 #define BIT_IC_INTR_MASK_M_ACTIVITY ((u32)0x00000001 << 8) 444 #define BIT_IC_INTR_MASK_M_RX_DONE ((u32)0x00000001 << 7) 445 #define BIT_IC_INTR_MASK_M_TX_ABRT ((u32)0x00000001 << 6) 446 #define BIT_IC_INTR_MASK_M_RD_REQ ((u32)0x00000001 << 5) 447 #define BIT_IC_INTR_MASK_M_TX_EMPTY ((u32)0x00000001 << 4) 448 #define BIT_IC_INTR_MASK_M_TX_OVER ((u32)0x00000001 << 3) 449 #define BIT_IC_INTR_MASK_M_RX_FULL ((u32)0x00000001 << 2) 450 #define BIT_IC_INTR_MASK_M_RX_OVER ((u32)0x00000001 << 1) 451 #define BIT_IC_INTR_MASK_M_RX_UNDER ((u32)0x00000001) 452 /** @} */ 453 454 /**************************************************************************//** 455 * @defgroup IC_RAW_INTR_STAT 456 * @{ 457 *****************************************************************************/ 458 #define BIT_IC_RAW_INTR_STAT_DMA_I2C_DONE ((u32)0x00000001 << 15) 459 #define BIT_IC_RAW_INTR_STAT_ADDR_2_MATCH ((u32)0x00000001 << 13) /* refer to I2C Slave1 Address Match */ 460 #define BIT_IC_RAW_INTR_STAT_ADDR_1_MATCH ((u32)0x00000001 << 12) /* refer to I2C Slave0 Address Match */ 461 #define BIT_IC_RAW_INTR_STAT_GEN_CALL ((u32)0x00000001 << 11) 462 #define BIT_IC_RAW_INTR_STAT_START_DET ((u32)0x00000001 << 10) 463 #define BIT_IC_RAW_INTR_STAT_STOP_DET ((u32)0x00000001 << 9) 464 #define BIT_IC_RAW_INTR_STAT_ACTIVITY ((u32)0x00000001 << 8) 465 #define BIT_IC_RAW_INTR_STAT_RX_DONE ((u32)0x00000001 << 7) 466 #define BIT_IC_RAW_INTR_STAT_TX_ABRT ((u32)0x00000001 << 6) 467 #define BIT_IC_RAW_INTR_STAT_RD_REQ ((u32)0x00000001 << 5) 468 #define BIT_IC_RAW_INTR_STAT_TX_EMPTY ((u32)0x00000001 << 4) 469 #define BIT_IC_RAW_INTR_STAT_TX_OVER ((u32)0x00000001 << 3) 470 #define BIT_IC_RAW_INTR_STAT_RX_FULL ((u32)0x00000001 << 2) 471 #define BIT_IC_RAW_INTR_STAT_RX_OVER ((u32)0x00000001 << 1) 472 #define BIT_IC_RAW_INTR_STAT_RX_UNDER ((u32)0x00000001) 473 /** @} */ 474 475 /**************************************************************************//** 476 * @defgroup IC_ENABLE 477 * @{ 478 *****************************************************************************/ 479 #define BIT_CTRL_IC_ENABLE ((u32)0x00000001) 480 /** @} */ 481 482 /**************************************************************************//** 483 * @defgroup IC_STATUS 484 * @{ 485 *****************************************************************************/ 486 #define BIT_IC_STATUS_BUS_BUSY ((u32)0x00000001 << 7) 487 #define BIT_IC_STATUS_SLV_ACTIVITY ((u32)0x00000001 << 6) 488 #define BIT_IC_STATUS_MST_ACTIVITY ((u32)0x00000001 << 5) 489 #define BIT_IC_STATUS_RFF ((u32)0x00000001 << 4) 490 #define BIT_IC_STATUS_RFNE ((u32)0x00000001 << 3) 491 #define BIT_IC_STATUS_TFE ((u32)0x00000001 << 2) 492 #define BIT_IC_STATUS_TFNF ((u32)0x00000001 << 1) 493 #define BIT_IC_STATUS_ACTIVITY ((u32)0x00000001) 494 /** @} */ 495 496 /**************************************************************************//** 497 * @defgroup IC_SDA_HOLD 498 * @{ 499 *****************************************************************************/ 500 #define BIT_CTRL_IC_SDA_HOLD ((u32)0x0000ffff) 501 /** @} */ 502 503 /**************************************************************************//** 504 * @defgroup IC_TX_ABRT_SOURCE 505 * @{ 506 *****************************************************************************/ 507 #define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX ((u32)0x00000001 << 15) 508 #define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST ((u32)0x00000001 << 14) 509 #define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO ((u32)0x00000001 << 13) 510 #define BIT_IC_TX_ABRT_SOURCE_ARB_LOST ((u32)0x00000001 << 12) 511 #define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS ((u32)0x00000001 << 11) 512 #define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT ((u32)0x00000001 << 10) 513 #define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT ((u32)0x00000001 << 9) 514 #define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT ((u32)0x00000001 << 8) 515 #define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET ((u32)0x00000001 << 7) 516 #define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET ((u32)0x00000001 << 6) 517 #define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ ((u32)0x00000001 << 5) 518 #define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK ((u32)0x00000001 << 4) 519 #define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK ((u32)0x00000001 << 3) 520 #define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK ((u32)0x00000001 << 2) 521 #define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK ((u32)0x00000001 << 1) 522 #define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK ((u32)0x00000001) 523 /** @} */ 524 525 /**************************************************************************//** 526 * @defgroup IC_SLV_DATA_NACK_ONLY 527 * @{ 528 *****************************************************************************/ 529 #define BIT_CTRL_IC_SLV_DATA_NACK_ONLY ((u32)0x00000001) 530 /** @} */ 531 532 /**************************************************************************//** 533 * @defgroup IC_DMA_CR 534 * @{ 535 *****************************************************************************/ 536 #define BIT_IC_DMA_CR_TDMAE ((u32)0x00000001 << 1) 537 #define BIT_IC_DMA_CR_RDMAE ((u32)0x00000001) 538 /** @} */ 539 540 /**************************************************************************//** 541 * @defgroup IC_SDA_SETUP 542 * @{ 543 *****************************************************************************/ 544 #define BIT_CTRL_IC_SDA_SETUP ((u32)0x000000ff) 545 /** @} */ 546 547 /**************************************************************************//** 548 * @defgroup IC_ACK_GENERAL_CALL 549 * @{ 550 *****************************************************************************/ 551 #define BIT_CTRL_IC_ACK_GENERAL_CALL ((u32)0x00000001) 552 /** @} */ 553 554 /**************************************************************************//** 555 * @defgroup IC_DMA_CMD 556 * @{ 557 *****************************************************************************/ 558 #define BIT_IC_DMA_CMD_RESTART ((u32)0x00000001 << 7) 559 #define BIT_IC_DMA_CMD_STOP ((u32)0x00000001 << 6) 560 #define BIT_IC_DMA_CMD_RW ((u32)0x00000001 << 5) /* 0 is write, 1 is read */ 561 #define BIT_IC_DMA_CMD_ENABLE ((u32)0x00000001) /* HW auto clear after transfer done */ 562 /** @} */ 563 564 /**************************************************************************//** 565 * @defgroup IC_DMA_MOD 566 * @{ 567 *****************************************************************************/ 568 #define BIT_IC_DMA_MOD ((u32)0x00000003) 569 /** @} */ 570 571 /**************************************************************************//** 572 * @defgroup IC_SLEEP 573 * @{ 574 *****************************************************************************/ 575 #define BIT_IC_SLEEP_CLOCK_GATED ((u32)0x00000001 << 1) 576 #define BIT_IC_SLEEP_CLOCK_CONTROL ((u32)0x00000001) 577 /** @} */ 578 579 /**************************************************************************//** 580 * @defgroup IC_FILTER 581 * @{ 582 *****************************************************************************/ 583 #define BIT_IC_FILTER_DIG_FLTR_SEL ((u32)0x00000001 << 8) 584 #define BIT_CTRL_IC_FILTER_DIG_FLTR_DEG ((u32)0x0000000F) 585 /** @} */ 586 587 /**************************************************************************//** 588 * @defgroup IC_SAR1 589 * @{ 590 *****************************************************************************/ 591 #define BIT_CTRL_IC_SAR1 ((u32)0x0000007F) 592 /** @} */ 593 /** @} */ 594 595 /** 596 * @} 597 */ 598 599 /** 600 * @} 601 */ 602 603 /* Other Definitions --------------------------------------------------------*/ 604 //I2C Timing Parameters 605 #define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns. 606 #define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns. 607 608 #define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns. 609 #define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns. 610 611 #define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf 612 #define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf 613 614 #define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf 615 #define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf 616 617 typedef struct 618 { 619 I2C_TypeDef* I2Cx; 620 u32 Tx_HandshakeInterface; 621 u32 Rx_HandshakeInterface; 622 IRQn_Type IrqNum; 623 } I2C_DevTable; 624 625 extern const I2C_DevTable I2C_DEV_TABLE[1]; 626 extern u32 I2C_SLAVEWRITE_PATCH; 627 extern u32 IC_FS_SCL_HCNT_TRIM; 628 extern u32 IC_FS_SCL_LCNT_TRIM; 629 630 #endif 631 632 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 633