1 /**************************************************************************//**
2 * @file rtl8721dhp_system.c
3 * @brief CMSIS Device System Source File for
4 * ARMCM3 Device Series
5 * @version V1.08
6 * @date 23. November 2012
7 *
8 * @note
9 *
10 ******************************************************************************/
11 /* Copyright (c) 2011 - 2012 ARM LIMITED
12
13 All rights reserved.
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 - Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 - Neither the name of ARM nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24 *
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36 ---------------------------------------------------------------------------*/
37
38
39 #include "basic_types.h"
40 #include "ameba_soc.h"
41
42 /*----------------------------------------------------------------------------
43 Define clocks
44 *----------------------------------------------------------------------------*/
45 #define __SYSTEM_CLOCK PLATFORM_CLOCK
46
47 /*----------------------------------------------------------------------------
48 Clock Variable definitions
49 *----------------------------------------------------------------------------*/
50 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
51
52 u32
SystemGetCpuClk(void)53 SystemGetCpuClk(void)
54 {
55 return CPU_ClkGet(IS_FPGA_VERIF);
56 }
57
58 /*----------------------------------------------------------------------------
59 Clock functions
60 *----------------------------------------------------------------------------*/
SystemCoreClockUpdate(void)61 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
62 {
63 SystemCoreClock = SystemGetCpuClk();
64 }
65
66 /**
67 * @brief Set CPU clock.
68 * @param CpuClk: This parameter can be one of the following values
69 * @arg CLK_KM4_200M
70 * @arg CLK_KM4_100M
71 * @arg CLK_KM4_50M
72 * @arg CLK_KM4_25M
73 * @arg CLK_KM4_XTAL
74 */
SystemSetCpuClk(u8 CpuClk)75 void SystemSetCpuClk(u8 CpuClk)
76 {
77 CPU_ClkSet(CpuClk);
78 SystemCoreClockUpdate();
79 }
80
81 /**
82 * Initialize the system
83 *
84 * @param none
85 * @return none
86 *
87 * @brief Setup the microcontroller system.
88 * Initialize the System.
89 */
SystemInit(void)90 void SystemInit (void)
91 {
92 DiagPrintf("---SystemInit--\r\n");
93 // TODO: Hardware initial
94 #ifdef UNALIGNED_SUPPORT_DISABLE
95 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
96 #endif
97
98 SystemCoreClockUpdate();
99 }
100
101 /**
102 * @brief Generate random seed
103 * @param none
104 * @return value: random seed value
105 */
Gen_RandomSeed(VOID)106 u32 Gen_RandomSeed(VOID)
107 {
108 #ifdef AMEBAD_TODO
109 u32 adc_tmp, isr, AdcTempDat;
110 u8 random_tmp, random[4];
111 ADC_TypeDef *adc = ADC;
112 int i, j;
113
114 /* init ADC*/
115 ADC_InitTypeDef AdcInitStruct;
116 ADC_InitStruct(&AdcInitStruct);
117 AdcInitStruct.ADC_BurstSz = 2;
118 ADC_AnaparAd[1] = 0x41004;
119
120 InterruptDis(ADC_IRQ);
121 PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, ENABLE);
122 ADC_Init(&AdcInitStruct);
123
124 /* Clear ADC Status */
125 ADC_INTClear();
126 ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, ENABLE);
127 ADC_Cmd(ENABLE);
128
129 /* B CUT ADD patch for reset fail */
130 AdcTempDat = adc->ANAPAR_AD1;
131 AdcTempDat |= BIT(0);
132 adc->ANAPAR_AD1 = AdcTempDat;
133
134 for(i = 0; i < 4; i++){
135 retry:
136 random_tmp = 0;
137 for (j = 0; j < 8; j++){
138 while (1) {
139 isr = ADC_GetISR();
140 if (isr & (BIT_ADC_FIFO_FULL | BIT_ADC_FIFO_RD_REQ)) {
141 adc_tmp = ADC_Read();
142 ADC_Read();
143
144 ADC_INTClear();
145 ADC_INTConfig(BIT_ADC_FIFO_FULL_EN|BIT_ADC_FIFO_RD_REQ_EN, DISABLE);
146
147 break;
148 }
149 }
150 random_tmp |= ((adc_tmp & 0x1) << j);
151 }
152
153 if((random_tmp == 0x00) || (random_tmp == 0xff)){
154 goto retry;
155 }
156
157 random[i] = random_tmp;
158 }
159
160 /* B CUT ADD patch for reset fail */
161 AdcTempDat = adc->ANAPAR_AD1;
162 AdcTempDat &= ~ BIT(0);
163 adc->ANAPAR_AD1 = AdcTempDat;
164
165 /* disable ADC*/
166 ADC_Cmd(DISABLE);
167 ADC_INTClear();
168 PLL2_Set(BIT_SYS_SYSPLL_CK_ADC_EN, DISABLE);
169
170 return *(u32*)random;
171 #else
172
173 return 0;
174 #endif
175 }
176
177 /**
178 * @brief get the state of rdp, enable or disable
179 * @retval : This parameter can be one of the following values:
180 * @arg TRUE: rdp is enable
181 * @arg FALSE: rdp is disable
182 */
IsRDPenabled(void)183 u32 IsRDPenabled(void)
184 {
185 return FALSE;
186 }
187
188