1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 status = "disabled"; 130 }; 131 132 usb1: ohci@400000 { 133 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 134 reg = <0x00400000 0x100000>; 135 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 137 clock-names = "ohci_clk", "hclk", "uhpck"; 138 status = "disabled"; 139 }; 140 141 usb2: ehci@500000 { 142 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 143 reg = <0x00500000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 146 clock-names = "usb_clk", "ehci_clk"; 147 status = "disabled"; 148 }; 149 150 L2: cache-controller@a00000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x00a00000 0x1000>; 153 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 ebi: ebi@10000000 { 159 compatible = "atmel,sama5d3-ebi"; 160 #address-cells = <2>; 161 #size-cells = <1>; 162 atmel,smc = <&hsmc>; 163 reg = <0x10000000 0x10000000 164 0x60000000 0x30000000>; 165 ranges = <0x0 0x0 0x10000000 0x10000000 166 0x1 0x0 0x60000000 0x10000000 167 0x2 0x0 0x70000000 0x10000000 168 0x3 0x0 0x80000000 0x10000000>; 169 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 170 status = "disabled"; 171 172 nand_controller: nand-controller { 173 compatible = "atmel,sama5d3-nand-controller"; 174 atmel,nfc-sram = <&nfc_sram>; 175 atmel,nfc-io = <&nfc_io>; 176 ecc-engine = <&pmecc>; 177 #address-cells = <2>; 178 #size-cells = <1>; 179 ranges; 180 status = "disabled"; 181 }; 182 }; 183 184 sdmmc0: sdio-host@a0000000 { 185 compatible = "atmel,sama5d2-sdhci"; 186 reg = <0xa0000000 0x300>; 187 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 189 clock-names = "hclock", "multclk", "baseclk"; 190 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 191 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 192 assigned-clock-rates = <480000000>; 193 status = "disabled"; 194 }; 195 196 sdmmc1: sdio-host@b0000000 { 197 compatible = "atmel,sama5d2-sdhci"; 198 reg = <0xb0000000 0x300>; 199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 201 clock-names = "hclock", "multclk", "baseclk"; 202 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 203 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 204 assigned-clock-rates = <480000000>; 205 status = "disabled"; 206 }; 207 208 nfc_io: nfc-io@c0000000 { 209 compatible = "atmel,sama5d3-nfc-io", "syscon"; 210 reg = <0xc0000000 0x8000000>; 211 }; 212 213 apb { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 hlcdc: hlcdc@f0000000 { 220 compatible = "atmel,sama5d2-hlcdc"; 221 reg = <0xf0000000 0x2000>; 222 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 224 clock-names = "periph_clk","sys_clk", "slow_clk"; 225 status = "disabled"; 226 227 hlcdc-display-controller { 228 compatible = "atmel,hlcdc-display-controller"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 }; 237 }; 238 239 hlcdc_pwm: hlcdc-pwm { 240 compatible = "atmel,hlcdc-pwm"; 241 #pwm-cells = <3>; 242 }; 243 }; 244 245 isc: isc@f0008000 { 246 compatible = "atmel,sama5d2-isc"; 247 reg = <0xf0008000 0x4000>; 248 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 250 clock-names = "hclock", "iscck", "gck"; 251 #clock-cells = <0>; 252 clock-output-names = "isc-mck"; 253 status = "disabled"; 254 }; 255 256 ramc0: ramc@f000c000 { 257 compatible = "atmel,sama5d3-ddramc"; 258 reg = <0xf000c000 0x200>; 259 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 260 clock-names = "ddrck", "mpddr"; 261 }; 262 263 dma0: dma-controller@f0010000 { 264 compatible = "atmel,sama5d4-dma"; 265 reg = <0xf0010000 0x1000>; 266 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 269 clock-names = "dma_clk"; 270 }; 271 272 /* Place dma1 here despite its address */ 273 dma1: dma-controller@f0004000 { 274 compatible = "atmel,sama5d4-dma"; 275 reg = <0xf0004000 0x1000>; 276 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 277 #dma-cells = <1>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 279 clock-names = "dma_clk"; 280 }; 281 282 pmc: pmc@f0014000 { 283 compatible = "atmel,sama5d2-pmc", "syscon"; 284 reg = <0xf0014000 0x160>; 285 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 286 #clock-cells = <2>; 287 clocks = <&clk32k>, <&main_xtal>; 288 clock-names = "slow_clk", "main_xtal"; 289 status = "disabled"; 290 secure-status = "okay"; 291 }; 292 293 qspi0: spi@f0020000 { 294 compatible = "atmel,sama5d2-qspi"; 295 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 296 reg-names = "qspi_base", "qspi_mmap"; 297 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 298 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 qspi1: spi@f0024000 { 305 compatible = "atmel,sama5d2-qspi"; 306 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 307 reg-names = "qspi_base", "qspi_mmap"; 308 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 309 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 sha@f0028000 { 316 compatible = "atmel,at91sam9g46-sha"; 317 reg = <0xf0028000 0x100>; 318 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 319 dmas = <&dma0 320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 321 AT91_XDMAC_DT_PERID(30))>; 322 dma-names = "tx"; 323 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 324 clock-names = "sha_clk"; 325 status = "okay"; 326 }; 327 328 aes@f002c000 { 329 compatible = "atmel,at91sam9g46-aes"; 330 reg = <0xf002c000 0x100>; 331 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 332 dmas = <&dma0 333 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 334 AT91_XDMAC_DT_PERID(26))>, 335 <&dma0 336 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 337 AT91_XDMAC_DT_PERID(27))>; 338 dma-names = "tx", "rx"; 339 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 340 clock-names = "aes_clk"; 341 status = "okay"; 342 }; 343 344 spi0: spi@f8000000 { 345 compatible = "atmel,at91rm9200-spi"; 346 reg = <0xf8000000 0x100>; 347 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 348 dmas = <&dma0 349 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 350 AT91_XDMAC_DT_PERID(6))>, 351 <&dma0 352 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 353 AT91_XDMAC_DT_PERID(7))>; 354 dma-names = "tx", "rx"; 355 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 356 clock-names = "spi_clk"; 357 atmel,fifo-size = <16>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 ssc0: ssc@f8004000 { 364 compatible = "atmel,at91sam9g45-ssc"; 365 reg = <0xf8004000 0x4000>; 366 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 367 dmas = <&dma0 368 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 369 AT91_XDMAC_DT_PERID(21))>, 370 <&dma0 371 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 372 AT91_XDMAC_DT_PERID(22))>; 373 dma-names = "tx", "rx"; 374 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 375 clock-names = "pclk"; 376 status = "disabled"; 377 }; 378 379 macb0: ethernet@f8008000 { 380 compatible = "atmel,sama5d2-gem"; 381 reg = <0xf8008000 0x1000>; 382 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 383 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 384 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 388 clock-names = "hclk", "pclk"; 389 status = "disabled"; 390 }; 391 392 tcb0: timer@f800c000 { 393 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0xf800c000 0x100>; 397 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 399 clock-names = "t0_clk", "gclk", "slow_clk"; 400 }; 401 402 tcb1: timer@f8010000 { 403 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0xf8010000 0x100>; 407 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 408 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 409 clock-names = "t0_clk", "gclk", "slow_clk"; 410 status = "disabled"; 411 secure-status = "okay"; 412 }; 413 414 hsmc: hsmc@f8014000 { 415 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 416 reg = <0xf8014000 0x1000>; 417 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 418 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 ranges; 422 423 pmecc: ecc-engine@f8014070 { 424 compatible = "atmel,sama5d2-pmecc"; 425 reg = <0xf8014070 0x490>, 426 <0xf8014500 0x100>; 427 }; 428 }; 429 430 pdmic: pdmic@f8018000 { 431 compatible = "atmel,sama5d2-pdmic"; 432 reg = <0xf8018000 0x124>; 433 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 434 dmas = <&dma0 435 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 436 | AT91_XDMAC_DT_PERID(50))>; 437 dma-names = "rx"; 438 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 439 clock-names = "pclk", "gclk"; 440 status = "disabled"; 441 }; 442 443 uart0: serial@f801c000 { 444 compatible = "atmel,at91sam9260-usart"; 445 reg = <0xf801c000 0x100>; 446 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 447 dmas = <&dma0 448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 449 AT91_XDMAC_DT_PERID(35))>, 450 <&dma0 451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 452 AT91_XDMAC_DT_PERID(36))>; 453 dma-names = "tx", "rx"; 454 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 455 clock-names = "usart"; 456 status = "disabled"; 457 }; 458 459 uart1: serial@f8020000 { 460 compatible = "atmel,at91sam9260-usart"; 461 reg = <0xf8020000 0x100>; 462 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 463 dmas = <&dma0 464 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 465 AT91_XDMAC_DT_PERID(37))>, 466 <&dma0 467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 468 AT91_XDMAC_DT_PERID(38))>; 469 dma-names = "tx", "rx"; 470 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 471 clock-names = "usart"; 472 status = "disabled"; 473 }; 474 475 uart2: serial@f8024000 { 476 compatible = "atmel,at91sam9260-usart"; 477 reg = <0xf8024000 0x100>; 478 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 479 dmas = <&dma0 480 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 481 AT91_XDMAC_DT_PERID(39))>, 482 <&dma0 483 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 484 AT91_XDMAC_DT_PERID(40))>; 485 dma-names = "tx", "rx"; 486 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 487 clock-names = "usart"; 488 status = "disabled"; 489 }; 490 491 i2c0: i2c@f8028000 { 492 compatible = "atmel,sama5d2-i2c"; 493 reg = <0xf8028000 0x100>; 494 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 495 dmas = <&dma0 496 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 497 AT91_XDMAC_DT_PERID(0))>, 498 <&dma0 499 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 500 AT91_XDMAC_DT_PERID(1))>; 501 dma-names = "tx", "rx"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 505 atmel,fifo-size = <16>; 506 status = "disabled"; 507 }; 508 509 pwm0: pwm@f802c000 { 510 compatible = "atmel,sama5d2-pwm"; 511 reg = <0xf802c000 0x4000>; 512 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 513 #pwm-cells = <3>; 514 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 515 status = "disabled"; 516 }; 517 518 sfr: sfr@f8030000 { 519 compatible = "atmel,sama5d2-sfr", "syscon"; 520 reg = <0xf8030000 0x98>; 521 status = "disabled"; 522 secure-status = "okay"; 523 }; 524 525 flx0: flexcom@f8034000 { 526 compatible = "atmel,sama5d2-flexcom"; 527 reg = <0xf8034000 0x200>; 528 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 ranges = <0x0 0xf8034000 0x800>; 532 status = "disabled"; 533 534 uart5: serial@200 { 535 compatible = "atmel,at91sam9260-usart"; 536 reg = <0x200 0x200>; 537 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 538 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 539 clock-names = "usart"; 540 dmas = <&dma0 541 (AT91_XDMAC_DT_MEM_IF(0) | 542 AT91_XDMAC_DT_PER_IF(1) | 543 AT91_XDMAC_DT_PERID(11))>, 544 <&dma0 545 (AT91_XDMAC_DT_MEM_IF(0) | 546 AT91_XDMAC_DT_PER_IF(1) | 547 AT91_XDMAC_DT_PERID(12))>; 548 dma-names = "tx", "rx"; 549 atmel,fifo-size = <32>; 550 status = "disabled"; 551 }; 552 553 spi2: spi@400 { 554 compatible = "atmel,at91rm9200-spi"; 555 reg = <0x400 0x200>; 556 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 560 clock-names = "spi_clk"; 561 dmas = <&dma0 562 (AT91_XDMAC_DT_MEM_IF(0) | 563 AT91_XDMAC_DT_PER_IF(1) | 564 AT91_XDMAC_DT_PERID(11))>, 565 <&dma0 566 (AT91_XDMAC_DT_MEM_IF(0) | 567 AT91_XDMAC_DT_PER_IF(1) | 568 AT91_XDMAC_DT_PERID(12))>; 569 dma-names = "tx", "rx"; 570 atmel,fifo-size = <16>; 571 status = "disabled"; 572 }; 573 574 i2c2: i2c@600 { 575 compatible = "atmel,sama5d2-i2c"; 576 reg = <0x600 0x200>; 577 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 581 dmas = <&dma0 582 (AT91_XDMAC_DT_MEM_IF(0) | 583 AT91_XDMAC_DT_PER_IF(1) | 584 AT91_XDMAC_DT_PERID(11))>, 585 <&dma0 586 (AT91_XDMAC_DT_MEM_IF(0) | 587 AT91_XDMAC_DT_PER_IF(1) | 588 AT91_XDMAC_DT_PERID(12))>; 589 dma-names = "tx", "rx"; 590 atmel,fifo-size = <16>; 591 status = "disabled"; 592 }; 593 }; 594 595 flx1: flexcom@f8038000 { 596 compatible = "atmel,sama5d2-flexcom"; 597 reg = <0xf8038000 0x200>; 598 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0x0 0xf8038000 0x800>; 602 status = "disabled"; 603 604 uart6: serial@200 { 605 compatible = "atmel,at91sam9260-usart"; 606 reg = <0x200 0x200>; 607 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 608 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 609 clock-names = "usart"; 610 dmas = <&dma0 611 (AT91_XDMAC_DT_MEM_IF(0) | 612 AT91_XDMAC_DT_PER_IF(1) | 613 AT91_XDMAC_DT_PERID(13))>, 614 <&dma0 615 (AT91_XDMAC_DT_MEM_IF(0) | 616 AT91_XDMAC_DT_PER_IF(1) | 617 AT91_XDMAC_DT_PERID(14))>; 618 dma-names = "tx", "rx"; 619 atmel,fifo-size = <32>; 620 status = "disabled"; 621 }; 622 623 spi3: spi@400 { 624 compatible = "atmel,at91rm9200-spi"; 625 reg = <0x400 0x200>; 626 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 630 clock-names = "spi_clk"; 631 dmas = <&dma0 632 (AT91_XDMAC_DT_MEM_IF(0) | 633 AT91_XDMAC_DT_PER_IF(1) | 634 AT91_XDMAC_DT_PERID(13))>, 635 <&dma0 636 (AT91_XDMAC_DT_MEM_IF(0) | 637 AT91_XDMAC_DT_PER_IF(1) | 638 AT91_XDMAC_DT_PERID(14))>; 639 dma-names = "tx", "rx"; 640 atmel,fifo-size = <16>; 641 status = "disabled"; 642 }; 643 644 i2c3: i2c@600 { 645 compatible = "atmel,sama5d2-i2c"; 646 reg = <0x600 0x200>; 647 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 651 dmas = <&dma0 652 (AT91_XDMAC_DT_MEM_IF(0) | 653 AT91_XDMAC_DT_PER_IF(1) | 654 AT91_XDMAC_DT_PERID(13))>, 655 <&dma0 656 (AT91_XDMAC_DT_MEM_IF(0) | 657 AT91_XDMAC_DT_PER_IF(1) | 658 AT91_XDMAC_DT_PERID(14))>; 659 dma-names = "tx", "rx"; 660 atmel,fifo-size = <16>; 661 status = "disabled"; 662 }; 663 }; 664 665 securam: sram@f8044000 { 666 compatible = "atmel,sama5d2-securam", "mmio-sram"; 667 reg = <0xf8044000 0x1420>; 668 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 no-memory-wc; 672 ranges = <0 0xf8044000 0x1420>; 673 status = "disabled"; 674 secure-status = "okay"; 675 }; 676 677 reset_controller: rstc@f8048000 { 678 compatible = "atmel,sama5d3-rstc"; 679 reg = <0xf8048000 0x10>; 680 clocks = <&clk32k>; 681 status = "disabled"; 682 secure-status = "okay"; 683 }; 684 685 shutdown_controller: shdwc@f8048010 { 686 compatible = "atmel,sama5d2-shdwc"; 687 reg = <0xf8048010 0x10>; 688 clocks = <&clk32k>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 atmel,wakeup-rtc-timer; 692 status = "disabled"; 693 secure-status = "okay"; 694 }; 695 696 pit: timer@f8048030 { 697 compatible = "atmel,at91sam9260-pit"; 698 reg = <0xf8048030 0x10>; 699 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 700 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 701 }; 702 703 watchdog: watchdog@f8048040 { 704 compatible = "atmel,sama5d4-wdt"; 705 reg = <0xf8048040 0x10>; 706 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 707 clocks = <&clk32k>; 708 status = "disabled"; 709 secure-status = "okay"; 710 }; 711 712 clk32k: sckc@f8048050 { 713 compatible = "atmel,sama5d4-sckc"; 714 reg = <0xf8048050 0x4>; 715 716 clocks = <&slow_xtal>; 717 #clock-cells = <0>; 718 status = "disabled"; 719 secure-status = "okay"; 720 }; 721 722 rtc: rtc@f80480b0 { 723 compatible = "atmel,sama5d2-rtc"; 724 reg = <0xf80480b0 0x30>; 725 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 726 clocks = <&clk32k>; 727 status = "disabled"; 728 secure-status = "okay"; 729 }; 730 731 i2s0: i2s@f8050000 { 732 compatible = "atmel,sama5d2-i2s"; 733 reg = <0xf8050000 0x100>; 734 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 735 dmas = <&dma0 736 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 737 AT91_XDMAC_DT_PERID(31))>, 738 <&dma0 739 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 740 AT91_XDMAC_DT_PERID(32))>; 741 dma-names = "tx", "rx"; 742 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 743 clock-names = "pclk", "gclk"; 744 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 745 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 746 status = "disabled"; 747 }; 748 749 can0: can@f8054000 { 750 compatible = "bosch,m_can"; 751 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 752 reg-names = "m_can", "message_ram"; 753 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 754 <64 IRQ_TYPE_LEVEL_HIGH 7>; 755 interrupt-names = "int0", "int1"; 756 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 757 clock-names = "hclk", "cclk"; 758 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 759 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 760 assigned-clock-rates = <40000000>; 761 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 762 status = "disabled"; 763 }; 764 765 spi1: spi@fc000000 { 766 compatible = "atmel,at91rm9200-spi"; 767 reg = <0xfc000000 0x100>; 768 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 769 dmas = <&dma0 770 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 771 AT91_XDMAC_DT_PERID(8))>, 772 <&dma0 773 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 774 AT91_XDMAC_DT_PERID(9))>; 775 dma-names = "tx", "rx"; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 777 clock-names = "spi_clk"; 778 atmel,fifo-size = <16>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 uart3: serial@fc008000 { 785 compatible = "atmel,at91sam9260-usart"; 786 reg = <0xfc008000 0x100>; 787 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 788 dmas = <&dma1 789 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 790 AT91_XDMAC_DT_PERID(41))>, 791 <&dma1 792 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 793 AT91_XDMAC_DT_PERID(42))>; 794 dma-names = "tx", "rx"; 795 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 796 clock-names = "usart"; 797 status = "disabled"; 798 }; 799 800 uart4: serial@fc00c000 { 801 compatible = "atmel,at91sam9260-usart"; 802 reg = <0xfc00c000 0x100>; 803 dmas = <&dma0 804 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 805 AT91_XDMAC_DT_PERID(43))>, 806 <&dma0 807 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 808 AT91_XDMAC_DT_PERID(44))>; 809 dma-names = "tx", "rx"; 810 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 811 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 812 clock-names = "usart"; 813 status = "disabled"; 814 }; 815 816 flx2: flexcom@fc010000 { 817 compatible = "atmel,sama5d2-flexcom"; 818 reg = <0xfc010000 0x200>; 819 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 820 #address-cells = <1>; 821 #size-cells = <1>; 822 ranges = <0x0 0xfc010000 0x800>; 823 status = "disabled"; 824 825 uart7: serial@200 { 826 compatible = "atmel,at91sam9260-usart"; 827 reg = <0x200 0x200>; 828 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 829 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 830 clock-names = "usart"; 831 dmas = <&dma0 832 (AT91_XDMAC_DT_MEM_IF(0) | 833 AT91_XDMAC_DT_PER_IF(1) | 834 AT91_XDMAC_DT_PERID(15))>, 835 <&dma0 836 (AT91_XDMAC_DT_MEM_IF(0) | 837 AT91_XDMAC_DT_PER_IF(1) | 838 AT91_XDMAC_DT_PERID(16))>; 839 dma-names = "tx", "rx"; 840 atmel,fifo-size = <32>; 841 status = "disabled"; 842 }; 843 844 spi4: spi@400 { 845 compatible = "atmel,at91rm9200-spi"; 846 reg = <0x400 0x200>; 847 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 851 clock-names = "spi_clk"; 852 dmas = <&dma0 853 (AT91_XDMAC_DT_MEM_IF(0) | 854 AT91_XDMAC_DT_PER_IF(1) | 855 AT91_XDMAC_DT_PERID(15))>, 856 <&dma0 857 (AT91_XDMAC_DT_MEM_IF(0) | 858 AT91_XDMAC_DT_PER_IF(1) | 859 AT91_XDMAC_DT_PERID(16))>; 860 dma-names = "tx", "rx"; 861 atmel,fifo-size = <16>; 862 status = "disabled"; 863 }; 864 865 i2c4: i2c@600 { 866 compatible = "atmel,sama5d2-i2c"; 867 reg = <0x600 0x200>; 868 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 872 dmas = <&dma0 873 (AT91_XDMAC_DT_MEM_IF(0) | 874 AT91_XDMAC_DT_PER_IF(1) | 875 AT91_XDMAC_DT_PERID(15))>, 876 <&dma0 877 (AT91_XDMAC_DT_MEM_IF(0) | 878 AT91_XDMAC_DT_PER_IF(1) | 879 AT91_XDMAC_DT_PERID(16))>; 880 dma-names = "tx", "rx"; 881 atmel,fifo-size = <16>; 882 status = "disabled"; 883 }; 884 }; 885 886 flx3: flexcom@fc014000 { 887 compatible = "atmel,sama5d2-flexcom"; 888 reg = <0xfc014000 0x200>; 889 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 890 #address-cells = <1>; 891 #size-cells = <1>; 892 ranges = <0x0 0xfc014000 0x800>; 893 status = "disabled"; 894 895 uart8: serial@200 { 896 compatible = "atmel,at91sam9260-usart"; 897 reg = <0x200 0x200>; 898 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 899 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 900 clock-names = "usart"; 901 dmas = <&dma0 902 (AT91_XDMAC_DT_MEM_IF(0) | 903 AT91_XDMAC_DT_PER_IF(1) | 904 AT91_XDMAC_DT_PERID(17))>, 905 <&dma0 906 (AT91_XDMAC_DT_MEM_IF(0) | 907 AT91_XDMAC_DT_PER_IF(1) | 908 AT91_XDMAC_DT_PERID(18))>; 909 dma-names = "tx", "rx"; 910 atmel,fifo-size = <32>; 911 status = "disabled"; 912 }; 913 914 spi5: spi@400 { 915 compatible = "atmel,at91rm9200-spi"; 916 reg = <0x400 0x200>; 917 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 921 clock-names = "spi_clk"; 922 dmas = <&dma0 923 (AT91_XDMAC_DT_MEM_IF(0) | 924 AT91_XDMAC_DT_PER_IF(1) | 925 AT91_XDMAC_DT_PERID(17))>, 926 <&dma0 927 (AT91_XDMAC_DT_MEM_IF(0) | 928 AT91_XDMAC_DT_PER_IF(1) | 929 AT91_XDMAC_DT_PERID(18))>; 930 dma-names = "tx", "rx"; 931 atmel,fifo-size = <16>; 932 status = "disabled"; 933 }; 934 935 i2c5: i2c@600 { 936 compatible = "atmel,sama5d2-i2c"; 937 reg = <0x600 0x200>; 938 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 942 dmas = <&dma0 943 (AT91_XDMAC_DT_MEM_IF(0) | 944 AT91_XDMAC_DT_PER_IF(1) | 945 AT91_XDMAC_DT_PERID(17))>, 946 <&dma0 947 (AT91_XDMAC_DT_MEM_IF(0) | 948 AT91_XDMAC_DT_PER_IF(1) | 949 AT91_XDMAC_DT_PERID(18))>; 950 dma-names = "tx", "rx"; 951 atmel,fifo-size = <16>; 952 status = "disabled"; 953 }; 954 955 }; 956 957 flx4: flexcom@fc018000 { 958 compatible = "atmel,sama5d2-flexcom"; 959 reg = <0xfc018000 0x200>; 960 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 961 #address-cells = <1>; 962 #size-cells = <1>; 963 ranges = <0x0 0xfc018000 0x800>; 964 status = "disabled"; 965 966 uart9: serial@200 { 967 compatible = "atmel,at91sam9260-usart"; 968 reg = <0x200 0x200>; 969 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 970 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 971 clock-names = "usart"; 972 dmas = <&dma0 973 (AT91_XDMAC_DT_MEM_IF(0) | 974 AT91_XDMAC_DT_PER_IF(1) | 975 AT91_XDMAC_DT_PERID(19))>, 976 <&dma0 977 (AT91_XDMAC_DT_MEM_IF(0) | 978 AT91_XDMAC_DT_PER_IF(1) | 979 AT91_XDMAC_DT_PERID(20))>; 980 dma-names = "tx", "rx"; 981 atmel,fifo-size = <32>; 982 status = "disabled"; 983 }; 984 985 spi6: spi@400 { 986 compatible = "atmel,at91rm9200-spi"; 987 reg = <0x400 0x200>; 988 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 992 clock-names = "spi_clk"; 993 dmas = <&dma0 994 (AT91_XDMAC_DT_MEM_IF(0) | 995 AT91_XDMAC_DT_PER_IF(1) | 996 AT91_XDMAC_DT_PERID(19))>, 997 <&dma0 998 (AT91_XDMAC_DT_MEM_IF(0) | 999 AT91_XDMAC_DT_PER_IF(1) | 1000 AT91_XDMAC_DT_PERID(20))>; 1001 dma-names = "tx", "rx"; 1002 atmel,fifo-size = <16>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c6: i2c@600 { 1007 compatible = "atmel,sama5d2-i2c"; 1008 reg = <0x600 0x200>; 1009 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1013 dmas = <&dma0 1014 (AT91_XDMAC_DT_MEM_IF(0) | 1015 AT91_XDMAC_DT_PER_IF(1) | 1016 AT91_XDMAC_DT_PERID(19))>, 1017 <&dma0 1018 (AT91_XDMAC_DT_MEM_IF(0) | 1019 AT91_XDMAC_DT_PER_IF(1) | 1020 AT91_XDMAC_DT_PERID(20))>; 1021 dma-names = "tx", "rx"; 1022 atmel,fifo-size = <16>; 1023 status = "disabled"; 1024 }; 1025 }; 1026 1027 trng@fc01c000 { 1028 compatible = "atmel,at91sam9g45-trng"; 1029 reg = <0xfc01c000 0x100>; 1030 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1031 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1032 status = "disabled"; 1033 secure-status = "okay"; 1034 }; 1035 1036 aic: interrupt-controller@fc020000 { 1037 #interrupt-cells = <3>; 1038 compatible = "atmel,sama5d2-aic"; 1039 interrupt-controller; 1040 reg = <0xfc020000 0x200>; 1041 atmel,external-irqs = <49>; 1042 }; 1043 1044 saic: interrupt-controller@f803c000 { 1045 #interrupt-cells = <3>; 1046 compatible = "atmel,sama5d2-saic"; 1047 interrupt-controller; 1048 reg = <0xf803c000 0x200>; 1049 atmel,external-irqs = <49>; 1050 status = "disabled"; 1051 secure-status = "okay"; 1052 }; 1053 1054 i2c1: i2c@fc028000 { 1055 compatible = "atmel,sama5d2-i2c"; 1056 reg = <0xfc028000 0x100>; 1057 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1058 dmas = <&dma0 1059 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1060 AT91_XDMAC_DT_PERID(2))>, 1061 <&dma0 1062 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1063 AT91_XDMAC_DT_PERID(3))>; 1064 dma-names = "tx", "rx"; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1068 atmel,fifo-size = <16>; 1069 status = "disabled"; 1070 }; 1071 1072 adc: adc@fc030000 { 1073 compatible = "atmel,sama5d2-adc"; 1074 reg = <0xfc030000 0x100>; 1075 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1076 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1077 clock-names = "adc_clk"; 1078 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1079 dma-names = "rx"; 1080 atmel,min-sample-rate-hz = <200000>; 1081 atmel,max-sample-rate-hz = <20000000>; 1082 atmel,startup-time-ms = <4>; 1083 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1084 #io-channel-cells = <1>; 1085 status = "disabled"; 1086 }; 1087 1088 resistive_touch: resistive-touch { 1089 compatible = "resistive-adc-touch"; 1090 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1091 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1092 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1093 io-channel-names = "x", "y", "pressure"; 1094 touchscreen-min-pressure = <50000>; 1095 status = "disabled"; 1096 }; 1097 1098 pioA: pinctrl@fc039000 { 1099 compatible = "atmel,sama5d2-pinctrl"; 1100 reg = <0xfc039000 0x600>; 1101 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1102 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1103 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1104 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1105 interrupt-controller; 1106 #interrupt-cells = <2>; 1107 gpio-controller; 1108 #gpio-cells = <2>; 1109 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1110 }; 1111 1112 pioBU: secumod@fc040000 { 1113 compatible = "atmel,sama5d2-secumod", "syscon"; 1114 reg = <0xfc040000 0x100>; 1115 1116 gpio-controller; 1117 #gpio-cells = <2>; 1118 status = "disabled"; 1119 secure-status = "okay"; 1120 }; 1121 1122 tdes@fc044000 { 1123 compatible = "atmel,at91sam9g46-tdes"; 1124 reg = <0xfc044000 0x100>; 1125 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1126 dmas = <&dma0 1127 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1128 AT91_XDMAC_DT_PERID(28))>, 1129 <&dma0 1130 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1131 AT91_XDMAC_DT_PERID(29))>; 1132 dma-names = "tx", "rx"; 1133 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1134 clock-names = "tdes_clk"; 1135 status = "okay"; 1136 }; 1137 1138 classd: classd@fc048000 { 1139 compatible = "atmel,sama5d2-classd"; 1140 reg = <0xfc048000 0x100>; 1141 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1142 dmas = <&dma0 1143 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1144 AT91_XDMAC_DT_PERID(47))>; 1145 dma-names = "tx"; 1146 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1147 clock-names = "pclk", "gclk"; 1148 status = "disabled"; 1149 }; 1150 1151 i2s1: i2s@fc04c000 { 1152 compatible = "atmel,sama5d2-i2s"; 1153 reg = <0xfc04c000 0x100>; 1154 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1155 dmas = <&dma0 1156 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1157 AT91_XDMAC_DT_PERID(33))>, 1158 <&dma0 1159 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1160 AT91_XDMAC_DT_PERID(34))>; 1161 dma-names = "tx", "rx"; 1162 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1163 clock-names = "pclk", "gclk"; 1164 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1165 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1166 status = "disabled"; 1167 }; 1168 1169 can1: can@fc050000 { 1170 compatible = "bosch,m_can"; 1171 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1172 reg-names = "m_can", "message_ram"; 1173 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1174 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1175 interrupt-names = "int0", "int1"; 1176 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1177 clock-names = "hclk", "cclk"; 1178 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1179 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1180 assigned-clock-rates = <40000000>; 1181 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1182 status = "disabled"; 1183 }; 1184 1185 sfrbu: sfr@fc05c000 { 1186 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1187 reg = <0xfc05c000 0x20>; 1188 }; 1189 1190 chipid@fc069000 { 1191 compatible = "atmel,sama5d2-chipid"; 1192 reg = <0xfc069000 0x8>; 1193 }; 1194 }; 1195 }; 1196}; 1197