1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SCP_RDN1E1_MMAP_H
9 #define SCP_RDN1E1_MMAP_H
10 
11 #include <stdint.h>
12 
13 /*
14  * Top-level base addresses
15  */
16 #define SCP_EXPANSION1_BASE           UINT32_C(0x01000000)
17 #define SCP_EXPANSION2_BASE           UINT32_C(0x21000000)
18 #define SCP_EXPANSION3_BASE           UINT32_C(0x40000000)
19 #define SCP_PERIPHERAL_BASE           UINT32_C(0x44000000)
20 #define SCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
21 #define SCP_POWER_PERIPHERAL_BASE     UINT32_C(0x50000000)
22 #define SCP_NOC_GPV_BASE              UINT32_C(0x51000000)
23 #define SCP_SYS0_BASE                 UINT32_C(0x60000000)
24 #define SCP_SYS1_BASE                 UINT32_C(0xA0000000)
25 #define SCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
26 #define SCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
27 
28 /*
29  * Peripherals
30  */
31 #define SCP_REFCLK_CNTCTL_BASE        (SCP_PERIPHERAL_BASE + 0x0000)
32 #define SCP_REFCLK_CNTBASE0_BASE      (SCP_PERIPHERAL_BASE + 0x1000)
33 #define SCP_UART_BASE                 (SCP_PERIPHERAL_BASE + 0x2000)
34 #define SCP_WDOG_BASE                 (SCP_PERIPHERAL_BASE + 0x6000)
35 #define SCP_CS_CNTCONTROL_BASE        (SCP_PERIPHERAL_BASE + 0xA000)
36 #define SCP_MHU_AP_BASE               (SCP_PERIPHERAL_BASE + 0x1000000)
37 #define SCP_MHU_MCP_BASE              (SCP_PERIPHERAL_BASE + 0x1800000)
38 
39 /*
40  * Power control peripherals
41  */
42 #define SCP_PIK_SCP_BASE              (SCP_POWER_PERIPHERAL_BASE + 0x00000)
43 #define SCP_PIK_DEBUG_BASE            (SCP_POWER_PERIPHERAL_BASE + 0x20000)
44 #define SCP_SCP_SENSOR_DEBUG_BASE     (SCP_POWER_PERIPHERAL_BASE + 0x30000)
45 #define SCP_PIK_SYSTEM_BASE           (SCP_POWER_PERIPHERAL_BASE + 0x40000)
46 #define SCP_SENSOR_SYSTEM_BASE        (SCP_POWER_PERIPHERAL_BASE + 0x50000)
47 #define SCP_SENSOR_CLUS0_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x70000)
48 #define SCP_SENSOR_CLUS1_BASE         (SCP_POWER_PERIPHERAL_BASE + 0x90000)
49 #define SCP_PIK_DEBUG_CHAIN_BASE      (SCP_POWER_PERIPHERAL_BASE + 0x500000)
50 #define SCP_PIK_CLUSTER_BASE(n)       ((SCP_POWER_PERIPHERAL_BASE + 0x60000) + \
51                                       ((n) * 0x20000))
52 
53 /*
54  * PPU base address
55  */
56 #define SCP_PPU_SCP_BASE              (SCP_PIK_SCP_BASE + 0x1000)
57 #define SCP_PPU_SYS0_BASE             (SCP_PIK_SYSTEM_BASE + 0x1000)
58 #define SCP_PPU_SYS1_BASE             (SCP_PIK_SYSTEM_BASE + 0x5000)
59 #define SCP_PPU_DEBUG_BASE            (SCP_PIK_DEBUG_BASE + 0x1000)
60 #define SCP_PPU_CLUSTER_BASE(n)       (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
61 #define SCP_PPU_CORE_BASE(n, m)       (SCP_PPU_CLUSTER_BASE((n)) + \
62                                        ((m) + 1) * 0x1000)
63 
64 /*
65  * System access port 0
66  */
67 #define SCP_CMN600_BASE               (SCP_SYS0_BASE + 0x10000000)
68 
69 /*
70  * System access port 1
71  */
72 #define SCP_TRUSTED_RAM_BASE          (SCP_SYS1_BASE + 0x04000000)
73 #define SCP_NONTRUSTED_RAM_BASE       (SCP_SYS1_BASE + 0x06000000)
74 #define SCP_REFCLK_CNTCONTROL_BASE    (SCP_SYS1_BASE + 0x2A430000)
75 #define SCP_SID_BASE                  (SCP_SYS1_BASE + 0x2A4A0000)
76 
77 /*
78  * Base addresses of MHU devices v2
79  */
80 #define SCP_MHU_SCP_AP_SND_NS_CLUS0  (SCP_MHU_AP_BASE + 0x00000)
81 #define SCP_MHU_SCP_AP_RCV_NS_CLUS0  (SCP_MHU_AP_BASE + 0x10000)
82 #define SCP_MHU_SCP_AP_SND_S_CLUS0   (SCP_MHU_AP_BASE + 0x400000)
83 #define SCP_MHU_SCP_AP_RCV_S_CLUS0   (SCP_MHU_AP_BASE + 0x410000)
84 #define SCP_MHU_SCP_MCP_SND          (SCP_MHU_MCP_BASE + 0x00000)
85 #define SCP_MHU_SCP_MCP_RCV          (SCP_MHU_MCP_BASE + 0x10000)
86 
87 #endif /* SCP_RDN1E1_MMAP_H */
88