1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM775_PIK_DPU_H 9 #define SGM775_PIK_DPU_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief DPU PIK register definitions 17 */ 18 struct pik_dpu_reg { 19 FWK_R uint8_t RESERVED0[0x810]; 20 FWK_RW uint32_t M0CLK_CTRL; 21 FWK_RW uint32_t M0CLK_DIV1; 22 FWK_RW uint32_t M0CLK_DIV2; 23 uint32_t RESERVED1; 24 FWK_RW uint32_t M1CLK_CTRL; 25 FWK_RW uint32_t M1CLK_DIV1; 26 FWK_RW uint32_t M1CLK_DIV2; 27 uint32_t RESERVED2; 28 FWK_RW uint32_t ACLKDP_CTRL; 29 FWK_RW uint32_t ACLKDP_DIV1; 30 FWK_RW uint32_t ACLKDP_DIV2; 31 uint8_t RESERVED3[0xA00 - 0x83C]; 32 FWK_R uint32_t CLKFORCE_STATUS; 33 FWK_W uint32_t CLKFORCE_SET; 34 FWK_W uint32_t CLKFORCE_CLR; 35 uint8_t RESERVED4[0xFC0 - 0xA0C]; 36 FWK_RW uint32_t PWR_CTRL_CONFIG; 37 uint8_t RESERVED5[0xFD0 - 0xFC4]; 38 FWK_R uint32_t PID4; 39 FWK_R uint32_t PID5; 40 FWK_R uint32_t PID6; 41 FWK_R uint32_t PID7; 42 FWK_R uint32_t PID0; 43 FWK_R uint32_t PID1; 44 FWK_R uint32_t PID2; 45 FWK_R uint32_t PID3; 46 FWK_R uint32_t ID0; 47 FWK_R uint32_t ID1; 48 FWK_R uint32_t ID2; 49 FWK_R uint32_t ID3; 50 }; 51 52 #endif /* SGM775_PIK_DPU_H */ 53