1 /*
2  * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice, this
9  *    list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  *    contributors may be used to endorse or promote products derived from this
17  *    software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef NRFX_IRQS_NRF52832_H__
33 #define NRFX_IRQS_NRF52832_H__
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 
40 // POWER_CLOCK_IRQn
41 #define nrfx_power_clock_irq_handler    POWER_CLOCK_IRQHandler
42 
43 // RADIO_IRQn
44 
45 // UARTE0_UART0_IRQn
46 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
47 #define nrfx_prs_box_4_irq_handler  UARTE0_UART0_IRQHandler
48 #else
49 #define nrfx_uarte_0_irq_handler    UARTE0_UART0_IRQHandler
50 #define nrfx_uart_0_irq_handler     UARTE0_UART0_IRQHandler
51 #endif
52 
53 // SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
54 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
55 #define nrfx_prs_box_0_irq_handler  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
56 #else
57 #define nrfx_spim_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
58 #define nrfx_spis_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
59 #define nrfx_twim_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
60 #define nrfx_twis_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
61 #define nrfx_spi_0_irq_handler      SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
62 #define nrfx_twi_0_irq_handler      SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
63 #endif
64 
65 // SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
66 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
67 #define nrfx_prs_box_1_irq_handler  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
68 #else
69 #define nrfx_spim_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
70 #define nrfx_spis_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
71 #define nrfx_twim_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
72 #define nrfx_twis_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
73 #define nrfx_spi_1_irq_handler      SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
74 #define nrfx_twi_1_irq_handler      SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
75 #endif
76 
77 // NFCT_IRQn
78 #define nrfx_nfct_irq_handler       NFCT_IRQHandler
79 
80 // GPIOTE_IRQn
81 #define nrfx_gpiote_irq_handler     GPIOTE_IRQHandler
82 
83 // SAADC_IRQn
84 #define nrfx_saadc_irq_handler      SAADC_IRQHandler
85 
86 // TIMER0_IRQn
87 #define nrfx_timer_0_irq_handler    TIMER0_IRQHandler
88 
89 // TIMER1_IRQn
90 #define nrfx_timer_1_irq_handler    TIMER1_IRQHandler
91 
92 // TIMER2_IRQn
93 #define nrfx_timer_2_irq_handler    TIMER2_IRQHandler
94 
95 // RTC0_IRQn
96 #define nrfx_rtc_0_irq_handler      RTC0_IRQHandler
97 
98 // TEMP_IRQn
99 #define nrfx_temp_irq_handler       TEMP_IRQHandler
100 
101 // RNG_IRQn
102 #define nrfx_rng_irq_handler        RNG_IRQHandler
103 
104 // ECB_IRQn
105 
106 // CCM_AAR_IRQn
107 
108 // WDT_IRQn
109 #define nrfx_wdt_0_irq_handler      WDT_IRQHandler
110 
111 // RTC1_IRQn
112 #define nrfx_rtc_1_irq_handler      RTC1_IRQHandler
113 
114 // QDEC_IRQn
115 #define nrfx_qdec_irq_handler       QDEC_IRQHandler
116 
117 // COMP_LPCOMP_IRQn
118 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
119 #define nrfx_prs_box_3_irq_handler  COMP_LPCOMP_IRQHandler
120 #else
121 #define nrfx_comp_irq_handler       COMP_LPCOMP_IRQHandler
122 #define nrfx_lpcomp_irq_handler     COMP_LPCOMP_IRQHandler
123 #endif
124 
125 // SWI0_EGU0_IRQn
126 #define nrfx_egu_0_irq_handler      SWI0_EGU0_IRQHandler
127 
128 // SWI1_EGU1_IRQn
129 #define nrfx_egu_1_irq_handler      SWI1_EGU1_IRQHandler
130 
131 // SWI2_EGU2_IRQn
132 #define nrfx_egu_2_irq_handler      SWI2_EGU2_IRQHandler
133 
134 // SWI3_EGU3_IRQn
135 #define nrfx_egu_3_irq_handler      SWI3_EGU3_IRQHandler
136 
137 // SWI4_EGU4_IRQn
138 #define nrfx_egu_4_irq_handler      SWI4_EGU4_IRQHandler
139 
140 // SWI5_EGU5_IRQn
141 #define nrfx_egu_5_irq_handler      SWI5_EGU5_IRQHandler
142 
143 // TIMER3_IRQn
144 #define nrfx_timer_3_irq_handler    TIMER3_IRQHandler
145 
146 // TIMER4_IRQn
147 #define nrfx_timer_4_irq_handler    TIMER4_IRQHandler
148 
149 // PWM0_IRQn
150 #define nrfx_pwm_0_irq_handler      PWM0_IRQHandler
151 
152 // PDM_IRQn
153 #define nrfx_pdm_irq_handler        PDM_IRQHandler
154 
155 // MWU_IRQn
156 
157 // PWM1_IRQn
158 #define nrfx_pwm_1_irq_handler      PWM1_IRQHandler
159 
160 // PWM2_IRQn
161 #define nrfx_pwm_2_irq_handler      PWM2_IRQHandler
162 
163 // SPIM2_SPIS2_SPI2_IRQn
164 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
165 #define nrfx_prs_box_2_irq_handler  SPIM2_SPIS2_SPI2_IRQHandler
166 #else
167 #define nrfx_spim_2_irq_handler     SPIM2_SPIS2_SPI2_IRQHandler
168 #define nrfx_spis_2_irq_handler     SPIM2_SPIS2_SPI2_IRQHandler
169 #define nrfx_spi_2_irq_handler      SPIM2_SPIS2_SPI2_IRQHandler
170 #endif
171 
172 // RTC2_IRQn
173 #define nrfx_rtc_2_irq_handler      RTC2_IRQHandler
174 
175 // I2S_IRQn
176 #define nrfx_i2s_irq_handler        I2S_IRQHandler
177 
178 // FPU_IRQn
179 
180 
181 #ifdef __cplusplus
182 }
183 #endif
184 
185 #endif // NRFX_IRQS_NRF52832_H__
186