1 /*
2  * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice, this
9  *    list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  *    contributors may be used to endorse or promote products derived from this
17  *    software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef NRFX_IRQS_NRF5340_APPLICATION_H__
33 #define NRFX_IRQS_NRF5340_APPLICATION_H__
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 // DCNF_IRQn
40 
41 // CACHE_IRQn
42 
43 // SPU_IRQn
44 
45 // CLOCK_POWER_IRQn
46 #define nrfx_power_clock_irq_handler    CLOCK_POWER_IRQHandler
47 
48 // SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn
49 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED)
50 #define nrfx_prs_box_0_irq_handler  SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
51 #else
52 #define nrfx_spim_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
53 #define nrfx_spis_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
54 #define nrfx_twim_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
55 #define nrfx_twis_0_irq_handler     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
56 #define nrfx_uarte_0_irq_handler    SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
57 #endif
58 
59 // SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn
60 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED)
61 #define nrfx_prs_box_1_irq_handler  SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
62 #else
63 #define nrfx_spim_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
64 #define nrfx_spis_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
65 #define nrfx_twim_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
66 #define nrfx_twis_1_irq_handler     SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
67 #define nrfx_uarte_1_irq_handler    SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
68 #endif
69 
70 // SPIM4_IRQn
71 #define nrfx_spim_4_irq_handler     SPIM4_IRQHandler
72 
73 // SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn
74 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED)
75 #define nrfx_prs_box_2_irq_handler  SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
76 #else
77 #define nrfx_spim_2_irq_handler     SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
78 #define nrfx_spis_2_irq_handler     SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
79 #define nrfx_twim_2_irq_handler     SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
80 #define nrfx_twis_2_irq_handler     SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
81 #define nrfx_uarte_2_irq_handler    SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
82 #endif
83 
84 // SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn
85 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED)
86 #define nrfx_prs_box_3_irq_handler  SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
87 #else
88 #define nrfx_spim_3_irq_handler     SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
89 #define nrfx_spis_3_irq_handler     SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
90 #define nrfx_twim_3_irq_handler     SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
91 #define nrfx_twis_3_irq_handler     SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
92 #define nrfx_uarte_3_irq_handler    SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
93 #endif
94 
95 // GPIOTE0_IRQn
96 #define nrfx_gpiote_irq_handler     GPIOTE_IRQHandler
97 
98 // SAADC_IRQn
99 #define nrfx_saadc_irq_handler      SAADC_IRQHandler
100 
101 // TIMER0_IRQn
102 #define nrfx_timer_0_irq_handler    TIMER0_IRQHandler
103 
104 // TIMER1_IRQn
105 #define nrfx_timer_1_irq_handler    TIMER1_IRQHandler
106 
107 // TIMER2_IRQn
108 #define nrfx_timer_2_irq_handler    TIMER2_IRQHandler
109 
110 // RTC0_IRQn
111 #define nrfx_rtc_0_irq_handler      RTC0_IRQHandler
112 
113 // RTC1_IRQn
114 #define nrfx_rtc_1_irq_handler      RTC1_IRQHandler
115 
116 // WDT0_IRQn
117 #define nrfx_wdt_0_irq_handler      WDT0_IRQHandler
118 
119 // WDT1_IRQn
120 #define nrfx_wdt_1_irq_handler      WDT1_IRQHandler
121 
122 // COMP_LPCOMP_IRQn
123 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
124 #define nrfx_prs_box_4_irq_handler  COMP_LPCOMP_IRQHandler
125 #else
126 #define nrfx_comp_irq_handler       COMP_LPCOMP_IRQHandler
127 #define nrfx_lpcomp_irq_handler     COMP_LPCOMP_IRQHandler
128 #endif
129 
130 // EGU0_IRQn
131 #define nrfx_egu_0_irq_handler      EGU0_IRQHandler
132 
133 // EGU1_IRQn
134 #define nrfx_egu_1_irq_handler      EGU1_IRQHandler
135 
136 // EGU2_IRQn
137 #define nrfx_egu_2_irq_handler      EGU2_IRQHandler
138 
139 // EGU3_IRQn
140 #define nrfx_egu_3_irq_handler      EGU3_IRQHandler
141 
142 // EGU4_IRQn
143 #define nrfx_egu_4_irq_handler      EGU4_IRQHandler
144 
145 // EGU5_IRQn
146 #define nrfx_egu_5_irq_handler      EGU5_IRQHandler
147 
148 // PWM0_IRQn
149 #define nrfx_pwm_0_irq_handler      PWM0_IRQHandler
150 
151 // PWM1_IRQn
152 #define nrfx_pwm_1_irq_handler      PWM1_IRQHandler
153 
154 // PWM2_IRQn
155 #define nrfx_pwm_2_irq_handler      PWM2_IRQHandler
156 
157 // PWM3_IRQn
158 #define nrfx_pwm_3_irq_handler      PWM3_IRQHandler
159 
160 // PDM0_IRQn
161 #define nrfx_pdm_irq_handler        PDM0_IRQHandler
162 
163 // I2S0_IRQn
164 #define nrfx_i2s_irq_handler        I2S0_IRQHandler
165 
166 // IPC_IRQn
167 #define nrfx_ipc_irq_handler        IPC_IRQHandler
168 
169 // QSPI_IRQn
170 #define nrfx_qspi_irq_handler       QSPI_IRQHandler
171 
172 // NFCT_IRQn
173 #define nrfx_nfct_irq_handler       NFCT_IRQHandler
174 
175 // GPIOTE1_IRQn
176 
177 // QDEC0_IRQn
178 #define nrfx_qdec_irq_handler       QDEC_IRQHandler
179 
180 // QDEC1_IRQn
181 
182 // USBD_IRQn
183 #define nrfx_usbd_irq_handler       USBD_IRQHandler
184 
185 // USBREGULATOR_IRQn
186 #define nrfx_usbreg_irq_handler     USBREGULATOR_IRQHandler
187 
188 // KMU_IRQn
189 
190 // CRYPTOCELL_IRQn
191 
192 #ifdef __cplusplus
193 }
194 #endif
195 
196 #endif // NRFX_IRQS_NRF5340_APPLICATION_H__
197