1 /* 2 * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRFX_IRQS_NRF5340_NETWORK_H__ 33 #define NRFX_IRQS_NRF5340_NETWORK_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 // CLOCK_POWER_IRQn 40 #define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler 41 42 // RADIO_IRQn 43 44 // RNG_IRQn 45 #define nrfx_rng_irq_handler RNG_IRQHandler 46 47 // GPIOTE_IRQn 48 #define nrfx_gpiote_irq_handler GPIOTE_IRQHandler 49 50 // WDT_IRQn 51 #define nrfx_wdt_0_irq_handler WDT_IRQHandler 52 53 // TIMER0_IRQn 54 #define nrfx_timer_0_irq_handler TIMER0_IRQHandler 55 56 // ECB_IRQn 57 58 // AAR_CCM_IRQn 59 60 // TEMP_IRQn 61 #define nrfx_temp_irq_handler TEMP_IRQHandler 62 63 // RTC0_IRQn 64 #define nrfx_rtc_0_irq_handler RTC0_IRQHandler 65 66 // IPC_IRQn 67 #define nrfx_ipc_irq_handler IPC_IRQHandler 68 69 // SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn 70 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) 71 #define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 72 #else 73 #define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 74 #define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 75 #define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 76 #define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 77 #define nrfx_uarte_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler 78 #endif 79 80 // EGU0_IRQn 81 #define nrfx_egu_0_irq_handler EGU0_IRQHandler 82 83 // RTC1_IRQn 84 #define nrfx_rtc_1_irq_handler RTC1_IRQHandler 85 86 // TIMER1_IRQn 87 #define nrfx_timer_1_irq_handler TIMER1_IRQHandler 88 89 // TIMER2_IRQn 90 #define nrfx_timer_2_irq_handler TIMER2_IRQHandler 91 92 // SWI0_IRQn 93 94 // SWI1_IRQn 95 96 // SWI2_IRQn 97 98 // SWI3_IRQn 99 100 #ifdef __cplusplus 101 } 102 #endif 103 104 #endif // NRFX_IRQS_NRF5340_NETWORK_H__ 105