1 /* 2 * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef NRFX_IRQS_NRF9160_H__ 33 #define NRFX_IRQS_NRF9160_H__ 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 40 // SPU_IRQn 41 42 // CLOCK_POWER_IRQn 43 #define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler 44 45 // UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn 46 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) 47 #define nrfx_prs_box_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 48 #else 49 #define nrfx_spim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 50 #define nrfx_spis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 51 #define nrfx_twim_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 52 #define nrfx_twis_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 53 #define nrfx_uarte_0_irq_handler UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler 54 #endif 55 56 // UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn 57 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) 58 #define nrfx_prs_box_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 59 #else 60 #define nrfx_spim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 61 #define nrfx_spis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 62 #define nrfx_twim_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 63 #define nrfx_twis_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 64 #define nrfx_uarte_1_irq_handler UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler 65 #endif 66 67 // UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn 68 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) 69 #define nrfx_prs_box_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 70 #else 71 #define nrfx_spim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 72 #define nrfx_spis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 73 #define nrfx_twim_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 74 #define nrfx_twis_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 75 #define nrfx_uarte_2_irq_handler UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler 76 #endif 77 78 // UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn 79 #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) 80 #define nrfx_prs_box_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 81 #else 82 #define nrfx_spim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 83 #define nrfx_spis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 84 #define nrfx_twim_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 85 #define nrfx_twis_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 86 #define nrfx_uarte_3_irq_handler UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler 87 #endif 88 89 // GPIOTE0_IRQn 90 #define nrfx_gpiote_irq_handler GPIOTE_IRQHandler 91 92 // SAADC_IRQn 93 #define nrfx_saadc_irq_handler SAADC_IRQHandler 94 95 // TIMER0_IRQn 96 #define nrfx_timer_0_irq_handler TIMER0_IRQHandler 97 98 // TIMER1_IRQn 99 #define nrfx_timer_1_irq_handler TIMER1_IRQHandler 100 101 // TIMER2_IRQn 102 #define nrfx_timer_2_irq_handler TIMER2_IRQHandler 103 104 // RTC0_IRQn 105 #define nrfx_rtc_0_irq_handler RTC0_IRQHandler 106 107 // RTC1_IRQn 108 #define nrfx_rtc_1_irq_handler RTC1_IRQHandler 109 110 // WDT_IRQn 111 #define nrfx_wdt_0_irq_handler WDT_IRQHandler 112 113 // EGU0_IRQn 114 #define nrfx_egu_0_irq_handler EGU0_IRQHandler 115 116 // EGU1_IRQn 117 #define nrfx_egu_1_irq_handler EGU1_IRQHandler 118 119 // EGU2_IRQn 120 #define nrfx_egu_2_irq_handler EGU2_IRQHandler 121 122 // EGU3_IRQn 123 #define nrfx_egu_3_irq_handler EGU3_IRQHandler 124 125 // EGU4_IRQn 126 #define nrfx_egu_4_irq_handler EGU4_IRQHandler 127 128 // EGU5_IRQn 129 #define nrfx_egu_5_irq_handler EGU5_IRQHandler 130 131 // PWM0_IRQn 132 #define nrfx_pwm_0_irq_handler PWM0_IRQHandler 133 134 // PWM1_IRQn 135 #define nrfx_pwm_1_irq_handler PWM1_IRQHandler 136 137 // PWM2_IRQn 138 #define nrfx_pwm_2_irq_handler PWM2_IRQHandler 139 140 // PWM3_IRQn 141 #define nrfx_pwm_3_irq_handler PWM3_IRQHandler 142 143 // PDM_IRQn 144 #define nrfx_pdm_irq_handler PDM_IRQHandler 145 146 // I2S_IRQn 147 #define nrfx_i2s_irq_handler I2S_IRQHandler 148 149 // FPU_IRQn 150 151 // GPIOTE1_IRQn 152 153 // KMU_IRQn 154 155 // CRYPTOCELL_IRQn 156 157 #ifdef __cplusplus 158 } 159 #endif 160 161 #endif // NRFX_IRQS_NRF9160_H__ 162