1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2012 Linaro Ltd 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/ste-db8500-clkout.h> 9#include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> 10#include <dt-bindings/mfd/dbx500-prcmu.h> 11#include <dt-bindings/arm/ux500_pm_domains.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 /* This stablilizes the device enumeration */ 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 spi0 = &spi0; 27 spi1 = &spi1; 28 spi2 = &spi2; 29 spi3 = &spi3; 30 serial0 = &serial0; 31 serial1 = &serial1; 32 serial2 = &serial2; 33 }; 34 35 chosen { 36 }; 37 38 cpus { 39 #address-cells = <1>; 40 #size-cells = <0>; 41 enable-method = "ste,dbx500-smp"; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&CPU0>; 47 }; 48 core1 { 49 cpu = <&CPU1>; 50 }; 51 }; 52 }; 53 CPU0: cpu@300 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 reg = <0x300>; 57 clocks = <&prcmu_clk PRCMU_ARMSS>; 58 clock-names = "cpu"; 59 clock-latency = <20000>; 60 #cooling-cells = <2>; 61 }; 62 CPU1: cpu@301 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a9"; 65 reg = <0x301>; 66 }; 67 }; 68 69 thermal-zones { 70 /* 71 * Thermal zone for the SoC, using the thermal sensor in the 72 * PRCMU for temperature and the cpufreq driver for passive 73 * cooling. 74 */ 75 cpu_thermal: cpu-thermal { 76 polling-delay-passive = <250>; 77 /* 78 * This sensor fires interrupts to update the thermal 79 * zone, so no polling is needed. 80 */ 81 polling-delay = <0>; 82 83 thermal-sensors = <&thermal>; 84 85 trips { 86 cpu_alert: cpu-alert { 87 temperature = <70000>; 88 hysteresis = <2000>; 89 type = "passive"; 90 }; 91 cpu-crit { 92 temperature = <85000>; 93 hysteresis = <0>; 94 type = "critical"; 95 }; 96 }; 97 98 cooling-maps { 99 trip = <&cpu_alert>; 100 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 101 contribution = <100>; 102 }; 103 }; 104 }; 105 106 soc { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 compatible = "stericsson,db8500", "simple-bus"; 110 interrupt-parent = <&intc>; 111 ranges; 112 113 ptm@801ae000 { 114 compatible = "arm,coresight-etm3x", "arm,primecell"; 115 reg = <0x801ae000 0x1000>; 116 117 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 118 clock-names = "apb_pclk", "atclk"; 119 cpu = <&CPU0>; 120 out-ports { 121 port { 122 ptm0_out_port: endpoint { 123 remote-endpoint = <&funnel_in_port0>; 124 }; 125 }; 126 }; 127 }; 128 129 ptm@801af000 { 130 compatible = "arm,coresight-etm3x", "arm,primecell"; 131 reg = <0x801af000 0x1000>; 132 133 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 134 clock-names = "apb_pclk", "atclk"; 135 cpu = <&CPU1>; 136 out-ports { 137 port { 138 ptm1_out_port: endpoint { 139 remote-endpoint = <&funnel_in_port1>; 140 }; 141 }; 142 }; 143 }; 144 145 funnel@801a6000 { 146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 147 reg = <0x801a6000 0x1000>; 148 149 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 150 clock-names = "apb_pclk", "atclk"; 151 out-ports { 152 port { 153 funnel_out_port: endpoint { 154 remote-endpoint = 155 <&replicator_in_port0>; 156 }; 157 }; 158 }; 159 160 in-ports { 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 port@0 { 165 reg = <0>; 166 funnel_in_port0: endpoint { 167 remote-endpoint = <&ptm0_out_port>; 168 }; 169 }; 170 171 port@1 { 172 reg = <1>; 173 funnel_in_port1: endpoint { 174 remote-endpoint = <&ptm1_out_port>; 175 }; 176 }; 177 }; 178 }; 179 180 replicator { 181 compatible = "arm,coresight-static-replicator"; 182 clocks = <&prcmu_clk PRCMU_APEATCLK>; 183 clock-names = "atclk"; 184 185 out-ports { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 189 port@0 { 190 reg = <0>; 191 replicator_out_port0: endpoint { 192 remote-endpoint = <&tpiu_in_port>; 193 }; 194 }; 195 port@1 { 196 reg = <1>; 197 replicator_out_port1: endpoint { 198 remote-endpoint = <&etb_in_port>; 199 }; 200 }; 201 }; 202 203 in-ports { 204 port { 205 replicator_in_port0: endpoint { 206 remote-endpoint = <&funnel_out_port>; 207 }; 208 }; 209 }; 210 }; 211 212 tpiu@80190000 { 213 compatible = "arm,coresight-tpiu", "arm,primecell"; 214 reg = <0x80190000 0x1000>; 215 216 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 217 clock-names = "apb_pclk", "atclk"; 218 in-ports { 219 port { 220 tpiu_in_port: endpoint { 221 remote-endpoint = <&replicator_out_port0>; 222 }; 223 }; 224 }; 225 }; 226 227 etb@801a4000 { 228 compatible = "arm,coresight-etb10", "arm,primecell"; 229 reg = <0x801a4000 0x1000>; 230 231 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>; 232 clock-names = "apb_pclk", "atclk"; 233 in-ports { 234 port { 235 etb_in_port: endpoint { 236 remote-endpoint = <&replicator_out_port1>; 237 }; 238 }; 239 }; 240 }; 241 242 intc: interrupt-controller@a0411000 { 243 compatible = "arm,cortex-a9-gic"; 244 #interrupt-cells = <3>; 245 #address-cells = <1>; 246 interrupt-controller; 247 reg = <0xa0411000 0x1000>, 248 <0xa0410100 0x100>; 249 }; 250 251 scu@a0410000 { 252 compatible = "arm,cortex-a9-scu"; 253 reg = <0xa0410000 0x100>; 254 }; 255 256 /* 257 * The backup RAM is used for retention during sleep 258 * and various things like spin tables 259 */ 260 backupram@80150000 { 261 compatible = "ste,dbx500-backupram"; 262 reg = <0x80150000 0x2000>; 263 }; 264 265 L2: cache-controller { 266 compatible = "arm,pl310-cache"; 267 reg = <0xa0412000 0x1000>; 268 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 269 cache-unified; 270 cache-level = <2>; 271 }; 272 273 pmu { 274 compatible = "arm,cortex-a9-pmu"; 275 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 276 }; 277 278 pm_domains: pm_domains0 { 279 compatible = "stericsson,ux500-pm-domains"; 280 #power-domain-cells = <1>; 281 }; 282 283 clocks { 284 compatible = "stericsson,u8500-clks"; 285 /* 286 * Registers for the CLKRST block on peripheral 287 * groups 1, 2, 3, 5, 6, 288 */ 289 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, 290 <0x8000f000 0x1000>, <0xa03ff000 0x1000>, 291 <0xa03cf000 0x1000>; 292 293 prcmu_clk: prcmu-clock { 294 #clock-cells = <1>; 295 }; 296 297 prcc_pclk: prcc-periph-clock { 298 #clock-cells = <2>; 299 }; 300 301 prcc_kclk: prcc-kernel-clock { 302 #clock-cells = <2>; 303 }; 304 305 prcc_reset: prcc-reset-controller { 306 #reset-cells = <2>; 307 }; 308 309 rtc_clk: rtc32k-clock { 310 #clock-cells = <0>; 311 }; 312 313 smp_twd_clk: smp-twd-clock { 314 #clock-cells = <0>; 315 }; 316 317 clkout_clk: clkout-clock { 318 /* Cell 1 id, cell 2 source, cell 3 div */ 319 #clock-cells = <3>; 320 }; 321 }; 322 323 mtu@a03c6000 { 324 /* Nomadik System Timer */ 325 compatible = "st,nomadik-mtu"; 326 reg = <0xa03c6000 0x1000>; 327 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 328 329 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; 330 clock-names = "timclk", "apb_pclk"; 331 }; 332 333 timer@a0410600 { 334 compatible = "arm,cortex-a9-twd-timer"; 335 reg = <0xa0410600 0x20>; 336 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 337 338 clocks = <&smp_twd_clk>; 339 }; 340 341 watchdog@a0410620 { 342 compatible = "arm,cortex-a9-twd-wdt"; 343 reg = <0xa0410620 0x20>; 344 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 345 clocks = <&smp_twd_clk>; 346 }; 347 348 rtc@80154000 { 349 compatible = "arm,pl031", "arm,primecell"; 350 reg = <0x80154000 0x1000>; 351 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 352 353 clocks = <&rtc_clk>; 354 clock-names = "apb_pclk"; 355 }; 356 357 gpio0: gpio@8012e000 { 358 compatible = "stericsson,db8500-gpio", 359 "st,nomadik-gpio"; 360 reg = <0x8012e000 0x80>; 361 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 st,supports-sleepmode; 365 gpio-controller; 366 #gpio-cells = <2>; 367 gpio-bank = <0>; 368 gpio-ranges = <&pinctrl 0 0 32>; 369 clocks = <&prcc_pclk 1 9>; 370 }; 371 372 gpio1: gpio@8012e080 { 373 compatible = "stericsson,db8500-gpio", 374 "st,nomadik-gpio"; 375 reg = <0x8012e080 0x80>; 376 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 st,supports-sleepmode; 380 gpio-controller; 381 #gpio-cells = <2>; 382 gpio-bank = <1>; 383 gpio-ranges = <&pinctrl 0 32 5>; 384 clocks = <&prcc_pclk 1 9>; 385 }; 386 387 gpio2: gpio@8000e000 { 388 compatible = "stericsson,db8500-gpio", 389 "st,nomadik-gpio"; 390 reg = <0x8000e000 0x80>; 391 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 392 interrupt-controller; 393 #interrupt-cells = <2>; 394 st,supports-sleepmode; 395 gpio-controller; 396 #gpio-cells = <2>; 397 gpio-bank = <2>; 398 gpio-ranges = <&pinctrl 0 64 32>; 399 clocks = <&prcc_pclk 3 8>; 400 }; 401 402 gpio3: gpio@8000e080 { 403 compatible = "stericsson,db8500-gpio", 404 "st,nomadik-gpio"; 405 reg = <0x8000e080 0x80>; 406 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 st,supports-sleepmode; 410 gpio-controller; 411 #gpio-cells = <2>; 412 gpio-bank = <3>; 413 gpio-ranges = <&pinctrl 0 96 2>; 414 clocks = <&prcc_pclk 3 8>; 415 }; 416 417 gpio4: gpio@8000e100 { 418 compatible = "stericsson,db8500-gpio", 419 "st,nomadik-gpio"; 420 reg = <0x8000e100 0x80>; 421 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 st,supports-sleepmode; 425 gpio-controller; 426 #gpio-cells = <2>; 427 gpio-bank = <4>; 428 gpio-ranges = <&pinctrl 0 128 32>; 429 clocks = <&prcc_pclk 3 8>; 430 }; 431 432 gpio5: gpio@8000e180 { 433 compatible = "stericsson,db8500-gpio", 434 "st,nomadik-gpio"; 435 reg = <0x8000e180 0x80>; 436 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 437 interrupt-controller; 438 #interrupt-cells = <2>; 439 st,supports-sleepmode; 440 gpio-controller; 441 #gpio-cells = <2>; 442 gpio-bank = <5>; 443 gpio-ranges = <&pinctrl 0 160 12>; 444 clocks = <&prcc_pclk 3 8>; 445 }; 446 447 gpio6: gpio@8011e000 { 448 compatible = "stericsson,db8500-gpio", 449 "st,nomadik-gpio"; 450 reg = <0x8011e000 0x80>; 451 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 st,supports-sleepmode; 455 gpio-controller; 456 #gpio-cells = <2>; 457 gpio-bank = <6>; 458 gpio-ranges = <&pinctrl 0 192 32>; 459 clocks = <&prcc_pclk 2 11>; 460 }; 461 462 gpio7: gpio@8011e080 { 463 compatible = "stericsson,db8500-gpio", 464 "st,nomadik-gpio"; 465 reg = <0x8011e080 0x80>; 466 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 st,supports-sleepmode; 470 gpio-controller; 471 #gpio-cells = <2>; 472 gpio-bank = <7>; 473 gpio-ranges = <&pinctrl 0 224 7>; 474 clocks = <&prcc_pclk 2 11>; 475 }; 476 477 gpio8: gpio@a03fe000 { 478 compatible = "stericsson,db8500-gpio", 479 "st,nomadik-gpio"; 480 reg = <0xa03fe000 0x80>; 481 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 st,supports-sleepmode; 485 gpio-controller; 486 #gpio-cells = <2>; 487 gpio-bank = <8>; 488 gpio-ranges = <&pinctrl 0 256 12>; 489 clocks = <&prcc_pclk 5 1>; 490 }; 491 492 pinctrl: pinctrl { 493 compatible = "stericsson,db8500-pinctrl"; 494 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>, 495 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>, 496 <&gpio8>; 497 prcm = <&prcmu>; 498 }; 499 500 usb_per5@a03e0000 { 501 compatible = "stericsson,db8500-musb"; 502 reg = <0xa03e0000 0x10000>; 503 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "mc"; 505 506 dr_mode = "otg"; 507 508 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */ 509 <&dma 38 0 0x0>, /* Logical - MemToDev */ 510 <&dma 37 0 0x2>, /* Logical - DevToMem */ 511 <&dma 37 0 0x0>, /* Logical - MemToDev */ 512 <&dma 36 0 0x2>, /* Logical - DevToMem */ 513 <&dma 36 0 0x0>, /* Logical - MemToDev */ 514 <&dma 19 0 0x2>, /* Logical - DevToMem */ 515 <&dma 19 0 0x0>, /* Logical - MemToDev */ 516 <&dma 18 0 0x2>, /* Logical - DevToMem */ 517 <&dma 18 0 0x0>, /* Logical - MemToDev */ 518 <&dma 17 0 0x2>, /* Logical - DevToMem */ 519 <&dma 17 0 0x0>, /* Logical - MemToDev */ 520 <&dma 16 0 0x2>, /* Logical - DevToMem */ 521 <&dma 16 0 0x0>, /* Logical - MemToDev */ 522 <&dma 39 0 0x2>, /* Logical - DevToMem */ 523 <&dma 39 0 0x0>; /* Logical - MemToDev */ 524 525 dma-names = "iep_1_9", "oep_1_9", 526 "iep_2_10", "oep_2_10", 527 "iep_3_11", "oep_3_11", 528 "iep_4_12", "oep_4_12", 529 "iep_5_13", "oep_5_13", 530 "iep_6_14", "oep_6_14", 531 "iep_7_15", "oep_7_15", 532 "iep_8", "oep_8"; 533 534 clocks = <&prcc_pclk 5 0>; 535 }; 536 537 dma: dma-controller@801C0000 { 538 compatible = "stericsson,db8500-dma40", "stericsson,dma40"; 539 reg = <0x801C0000 0x1000 0x40010000 0x800>; 540 reg-names = "base", "lcpa"; 541 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 542 543 #dma-cells = <3>; 544 memcpy-channels = <56 57 58 59 60>; 545 546 clocks = <&prcmu_clk PRCMU_DMACLK>; 547 }; 548 549 prcmu: prcmu@80157000 { 550 compatible = "stericsson,db8500-prcmu", "syscon"; 551 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; 552 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; 553 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 ranges; 559 560 prcmu-timer-4@80157450 { 561 compatible = "stericsson,db8500-prcmu-timer-4"; 562 reg = <0x80157450 0xC>; 563 }; 564 565 thermal: thermal@801573c0 { 566 compatible = "stericsson,db8500-thermal"; 567 reg = <0x801573c0 0x40>; 568 interrupt-parent = <&prcmu>; 569 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>, 570 <22 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; 572 #thermal-sensor-cells = <0>; 573 }; 574 575 db8500-prcmu-regulators { 576 compatible = "stericsson,db8500-prcmu-regulator"; 577 578 // DB8500_REGULATOR_VAPE 579 db8500_vape_reg: db8500_vape { 580 regulator-always-on; 581 }; 582 583 // DB8500_REGULATOR_VARM 584 db8500_varm_reg: db8500_varm { 585 }; 586 587 // DB8500_REGULATOR_VMODEM 588 db8500_vmodem_reg: db8500_vmodem { 589 }; 590 591 // DB8500_REGULATOR_VPLL 592 db8500_vpll_reg: db8500_vpll { 593 }; 594 595 // DB8500_REGULATOR_VSMPS1 596 db8500_vsmps1_reg: db8500_vsmps1 { 597 }; 598 599 // DB8500_REGULATOR_VSMPS2 600 db8500_vsmps2_reg: db8500_vsmps2 { 601 }; 602 603 // DB8500_REGULATOR_VSMPS3 604 db8500_vsmps3_reg: db8500_vsmps3 { 605 }; 606 607 // DB8500_REGULATOR_VRF1 608 db8500_vrf1_reg: db8500_vrf1 { 609 }; 610 611 // DB8500_REGULATOR_SWITCH_SVAMMDSP 612 db8500_sva_mmdsp_reg: db8500_sva_mmdsp { 613 }; 614 615 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET 616 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { 617 }; 618 619 // DB8500_REGULATOR_SWITCH_SVAPIPE 620 db8500_sva_pipe_reg: db8500_sva_pipe { 621 }; 622 623 // DB8500_REGULATOR_SWITCH_SIAMMDSP 624 db8500_sia_mmdsp_reg: db8500_sia_mmdsp { 625 }; 626 627 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET 628 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret { 629 }; 630 631 // DB8500_REGULATOR_SWITCH_SIAPIPE 632 db8500_sia_pipe_reg: db8500_sia_pipe { 633 }; 634 635 // DB8500_REGULATOR_SWITCH_SGA 636 db8500_sga_reg: db8500_sga { 637 vin-supply = <&db8500_vape_reg>; 638 }; 639 640 // DB8500_REGULATOR_SWITCH_B2R2_MCDE 641 db8500_b2r2_mcde_reg: db8500_b2r2_mcde { 642 vin-supply = <&db8500_vape_reg>; 643 }; 644 645 // DB8500_REGULATOR_SWITCH_ESRAM12 646 db8500_esram12_reg: db8500_esram12 { 647 }; 648 649 // DB8500_REGULATOR_SWITCH_ESRAM12RET 650 db8500_esram12_ret_reg: db8500_esram12_ret { 651 }; 652 653 // DB8500_REGULATOR_SWITCH_ESRAM34 654 db8500_esram34_reg: db8500_esram34 { 655 }; 656 657 // DB8500_REGULATOR_SWITCH_ESRAM34RET 658 db8500_esram34_ret_reg: db8500_esram34_ret { 659 }; 660 }; 661 }; 662 663 i2c0: i2c@80004000 { 664 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 665 reg = <0x80004000 0x1000>; 666 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 667 668 #address-cells = <1>; 669 #size-cells = <0>; 670 671 clock-frequency = <400000>; 672 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; 673 clock-names = "i2cclk", "apb_pclk"; 674 power-domains = <&pm_domains DOMAIN_VAPE>; 675 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; 676 677 status = "disabled"; 678 }; 679 680 i2c1: i2c@80122000 { 681 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 682 reg = <0x80122000 0x1000>; 683 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 684 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 clock-frequency = <400000>; 689 690 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; 691 clock-names = "i2cclk", "apb_pclk"; 692 power-domains = <&pm_domains DOMAIN_VAPE>; 693 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>; 694 695 status = "disabled"; 696 }; 697 698 i2c2: i2c@80128000 { 699 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 700 reg = <0x80128000 0x1000>; 701 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 702 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 clock-frequency = <400000>; 707 708 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; 709 clock-names = "i2cclk", "apb_pclk"; 710 power-domains = <&pm_domains DOMAIN_VAPE>; 711 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>; 712 713 status = "disabled"; 714 }; 715 716 i2c3: i2c@80110000 { 717 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 718 reg = <0x80110000 0x1000>; 719 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 720 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 clock-frequency = <400000>; 725 726 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; 727 clock-names = "i2cclk", "apb_pclk"; 728 power-domains = <&pm_domains DOMAIN_VAPE>; 729 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>; 730 731 status = "disabled"; 732 }; 733 734 i2c4: i2c@8012a000 { 735 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; 736 reg = <0x8012a000 0x1000>; 737 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 738 739 #address-cells = <1>; 740 #size-cells = <0>; 741 742 clock-frequency = <400000>; 743 744 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; 745 clock-names = "i2cclk", "apb_pclk"; 746 power-domains = <&pm_domains DOMAIN_VAPE>; 747 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>; 748 749 status = "disabled"; 750 }; 751 752 ssp0: spi@80002000 { 753 compatible = "arm,pl022", "arm,primecell"; 754 reg = <0x80002000 0x1000>; 755 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; 759 clock-names = "sspclk", "apb_pclk"; 760 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ 761 <&dma 8 0 0x0>; /* Logical - MemToDev */ 762 dma-names = "rx", "tx"; 763 power-domains = <&pm_domains DOMAIN_VAPE>; 764 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>; 765 766 status = "disabled"; 767 }; 768 769 ssp1: spi@80003000 { 770 compatible = "arm,pl022", "arm,primecell"; 771 reg = <0x80003000 0x1000>; 772 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; 776 clock-names = "sspclk", "apb_pclk"; 777 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ 778 <&dma 9 0 0x0>; /* Logical - MemToDev */ 779 dma-names = "rx", "tx"; 780 power-domains = <&pm_domains DOMAIN_VAPE>; 781 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>; 782 783 status = "disabled"; 784 }; 785 786 spi0: spi@8011a000 { 787 compatible = "arm,pl022", "arm,primecell"; 788 reg = <0x8011a000 0x1000>; 789 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 /* Same clock wired to kernel and pclk */ 793 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; 794 clock-names = "sspclk", "apb_pclk"; 795 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ 796 <&dma 0 0 0x0>; /* Logical - MemToDev */ 797 dma-names = "rx", "tx"; 798 power-domains = <&pm_domains DOMAIN_VAPE>; 799 800 status = "disabled"; 801 }; 802 803 spi1: spi@80112000 { 804 compatible = "arm,pl022", "arm,primecell"; 805 reg = <0x80112000 0x1000>; 806 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 /* Same clock wired to kernel and pclk */ 810 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; 811 clock-names = "sspclk", "apb_pclk"; 812 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ 813 <&dma 35 0 0x0>; /* Logical - MemToDev */ 814 dma-names = "rx", "tx"; 815 power-domains = <&pm_domains DOMAIN_VAPE>; 816 817 status = "disabled"; 818 }; 819 820 spi2: spi@80111000 { 821 compatible = "arm,pl022", "arm,primecell"; 822 reg = <0x80111000 0x1000>; 823 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 /* Same clock wired to kernel and pclk */ 827 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; 828 clock-names = "sspclk", "apb_pclk"; 829 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ 830 <&dma 33 0 0x0>; /* Logical - MemToDev */ 831 dma-names = "rx", "tx"; 832 power-domains = <&pm_domains DOMAIN_VAPE>; 833 834 status = "disabled"; 835 }; 836 837 spi3: spi@80129000 { 838 compatible = "arm,pl022", "arm,primecell"; 839 reg = <0x80129000 0x1000>; 840 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 /* Same clock wired to kernel and pclk */ 844 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; 845 clock-names = "sspclk", "apb_pclk"; 846 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ 847 <&dma 40 0 0x0>; /* Logical - MemToDev */ 848 dma-names = "rx", "tx"; 849 power-domains = <&pm_domains DOMAIN_VAPE>; 850 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>; 851 852 status = "disabled"; 853 }; 854 855 serial0: uart@80120000 { 856 compatible = "arm,pl011", "arm,primecell"; 857 reg = <0x80120000 0x1000>; 858 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 859 860 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ 861 <&dma 13 0 0x0>; /* Logical - MemToDev */ 862 dma-names = "rx", "tx"; 863 864 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>; 865 clock-names = "uart", "apb_pclk"; 866 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>; 867 868 status = "disabled"; 869 }; 870 871 serial1: uart@80121000 { 872 compatible = "arm,pl011", "arm,primecell"; 873 reg = <0x80121000 0x1000>; 874 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 875 876 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ 877 <&dma 12 0 0x0>; /* Logical - MemToDev */ 878 dma-names = "rx", "tx"; 879 880 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>; 881 clock-names = "uart", "apb_pclk"; 882 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>; 883 884 status = "disabled"; 885 }; 886 887 serial2: uart@80007000 { 888 compatible = "arm,pl011", "arm,primecell"; 889 reg = <0x80007000 0x1000>; 890 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 891 892 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ 893 <&dma 11 0 0x0>; /* Logical - MemToDev */ 894 dma-names = "rx", "tx"; 895 896 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>; 897 clock-names = "uart", "apb_pclk"; 898 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>; 899 900 status = "disabled"; 901 }; 902 903 mmc@80126000 { 904 compatible = "arm,pl18x", "arm,primecell"; 905 reg = <0x80126000 0x1000>; 906 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 907 908 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ 909 <&dma 29 0 0x0>; /* Logical - MemToDev */ 910 dma-names = "rx", "tx"; 911 912 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; 913 clock-names = "sdi", "apb_pclk"; 914 power-domains = <&pm_domains DOMAIN_VAPE>; 915 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>; 916 917 status = "disabled"; 918 }; 919 920 mmc@80118000 { 921 compatible = "arm,pl18x", "arm,primecell"; 922 reg = <0x80118000 0x1000>; 923 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 924 925 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ 926 <&dma 32 0 0x0>; /* Logical - MemToDev */ 927 dma-names = "rx", "tx"; 928 929 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; 930 clock-names = "sdi", "apb_pclk"; 931 power-domains = <&pm_domains DOMAIN_VAPE>; 932 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>; 933 934 status = "disabled"; 935 }; 936 937 mmc@80005000 { 938 compatible = "arm,pl18x", "arm,primecell"; 939 reg = <0x80005000 0x1000>; 940 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 941 942 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ 943 <&dma 28 0 0x0>; /* Logical - MemToDev */ 944 dma-names = "rx", "tx"; 945 946 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; 947 clock-names = "sdi", "apb_pclk"; 948 power-domains = <&pm_domains DOMAIN_VAPE>; 949 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>; 950 951 status = "disabled"; 952 }; 953 954 mmc@80119000 { 955 compatible = "arm,pl18x", "arm,primecell"; 956 reg = <0x80119000 0x1000>; 957 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 958 959 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ 960 <&dma 41 0 0x0>; /* Logical - MemToDev */ 961 dma-names = "rx", "tx"; 962 963 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; 964 clock-names = "sdi", "apb_pclk"; 965 power-domains = <&pm_domains DOMAIN_VAPE>; 966 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>; 967 968 status = "disabled"; 969 }; 970 971 mmc@80114000 { 972 compatible = "arm,pl18x", "arm,primecell"; 973 reg = <0x80114000 0x1000>; 974 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 975 976 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ 977 <&dma 42 0 0x0>; /* Logical - MemToDev */ 978 dma-names = "rx", "tx"; 979 980 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; 981 clock-names = "sdi", "apb_pclk"; 982 power-domains = <&pm_domains DOMAIN_VAPE>; 983 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>; 984 985 status = "disabled"; 986 }; 987 988 mmc@80008000 { 989 compatible = "arm,pl18x", "arm,primecell"; 990 reg = <0x80008000 0x1000>; 991 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 992 993 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ 994 <&dma 43 0 0x0>; /* Logical - MemToDev */ 995 dma-names = "rx", "tx"; 996 997 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; 998 clock-names = "sdi", "apb_pclk"; 999 power-domains = <&pm_domains DOMAIN_VAPE>; 1000 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>; 1001 1002 status = "disabled"; 1003 }; 1004 1005 sound { 1006 compatible = "stericsson,snd-soc-mop500"; 1007 stericsson,cpu-dai = <&msp1 &msp3>; 1008 }; 1009 1010 msp0: msp@80123000 { 1011 compatible = "stericsson,ux500-msp-i2s"; 1012 reg = <0x80123000 0x1000>; 1013 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1014 v-ape-supply = <&db8500_vape_reg>; 1015 1016 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ 1017 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */ 1018 dma-names = "rx", "tx"; 1019 1020 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>; 1021 clock-names = "msp", "apb_pclk"; 1022 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>; 1023 1024 status = "disabled"; 1025 }; 1026 1027 msp1: msp@80124000 { 1028 compatible = "stericsson,ux500-msp-i2s"; 1029 reg = <0x80124000 0x1000>; 1030 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1031 v-ape-supply = <&db8500_vape_reg>; 1032 1033 /* This DMA channel only exist on DB8500 v1 */ 1034 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ 1035 dma-names = "tx"; 1036 1037 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>; 1038 clock-names = "msp", "apb_pclk"; 1039 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>; 1040 1041 status = "disabled"; 1042 }; 1043 1044 // HDMI sound 1045 msp2: msp@80117000 { 1046 compatible = "stericsson,ux500-msp-i2s"; 1047 reg = <0x80117000 0x1000>; 1048 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1049 v-ape-supply = <&db8500_vape_reg>; 1050 1051 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ 1052 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev 1053 HighPrio - Fixed */ 1054 dma-names = "rx", "tx"; 1055 1056 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; 1057 clock-names = "msp", "apb_pclk"; 1058 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>; 1059 1060 status = "disabled"; 1061 }; 1062 1063 msp3: msp@80125000 { 1064 compatible = "stericsson,ux500-msp-i2s"; 1065 reg = <0x80125000 0x1000>; 1066 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1067 v-ape-supply = <&db8500_vape_reg>; 1068 1069 /* This DMA channel only exist on DB8500 v2 */ 1070 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ 1071 dma-names = "rx"; 1072 1073 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>; 1074 clock-names = "msp", "apb_pclk"; 1075 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>; 1076 1077 status = "disabled"; 1078 }; 1079 1080 external-bus@50000000 { 1081 compatible = "simple-bus"; 1082 reg = <0x50000000 0x4000000>; 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 ranges = <0 0x50000000 0x4000000>; 1086 status = "disabled"; 1087 }; 1088 1089 gpu@a0300000 { 1090 /* 1091 * This block is referred to as "Smart Graphics Adapter SGA500" 1092 * in documentation but is in practice a pretty straight-forward 1093 * MALI-400 GPU block. 1094 */ 1095 compatible = "stericsson,db8500-mali", "arm,mali-400"; 1096 reg = <0xa0300000 0x10000>; 1097 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1102 interrupt-names = "gp", 1103 "gpmmu", 1104 "pp0", 1105 "ppmmu0", 1106 "combined"; 1107 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>; 1108 clock-names = "bus", "core"; 1109 mali-supply = <&db8500_sga_reg>; 1110 power-domains = <&pm_domains DOMAIN_VAPE>; 1111 }; 1112 1113 mcde@a0350000 { 1114 compatible = "ste,mcde"; 1115 reg = <0xa0350000 0x1000>; 1116 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1117 epod-supply = <&db8500_b2r2_mcde_reg>; 1118 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ 1119 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ 1120 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */ 1121 clock-names = "mcde", "lcd", "hdmi"; 1122 #address-cells = <1>; 1123 #size-cells = <1>; 1124 ranges; 1125 status = "disabled"; 1126 1127 dsi0: dsi@a0351000 { 1128 compatible = "ste,mcde-dsi"; 1129 reg = <0xa0351000 0x1000>; 1130 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; 1131 clock-names = "hs", "lp"; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 }; 1135 dsi1: dsi@a0352000 { 1136 compatible = "ste,mcde-dsi"; 1137 reg = <0xa0352000 0x1000>; 1138 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; 1139 clock-names = "hs", "lp"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 }; 1143 dsi2: dsi@a0353000 { 1144 compatible = "ste,mcde-dsi"; 1145 reg = <0xa0353000 0x1000>; 1146 /* This DSI port only has the Low Power / Energy Save clock */ 1147 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>; 1148 clock-names = "lp"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 }; 1152 }; 1153 1154 cryp@a03cb000 { 1155 compatible = "stericsson,ux500-cryp"; 1156 reg = <0xa03cb000 0x1000>; 1157 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&prcc_pclk 6 1>; 1159 power-domains = <&pm_domains DOMAIN_VAPE>; 1160 }; 1161 1162 hash@a03c2000 { 1163 compatible = "stericsson,ux500-hash"; 1164 reg = <0xa03c2000 0x1000>; 1165 clocks = <&prcc_pclk 6 2>; 1166 power-domains = <&pm_domains DOMAIN_VAPE>; 1167 }; 1168 }; 1169}; 1170