1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_adc.h 4 * @author MCD Application Team 5 * @version V1.5.1 6 * @date 22-May-2015 7 * @brief This file contains all the functions prototypes for the ADC firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F4xx_ADC_H 31 #define __STM32F4xx_ADC_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f4xx.h" 39 40 /** @addtogroup STM32F4xx_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup ADC 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 /** 51 * @brief ADC Init structure definition 52 */ 53 typedef struct 54 { 55 uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. 56 This parameter can be a value of @ref ADC_resolution */ 57 FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion 58 is performed in Scan (multichannels) 59 or Single (one channel) mode. 60 This parameter can be set to ENABLE or DISABLE */ 61 FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 62 is performed in Continuous or Single mode. 63 This parameter can be set to ENABLE or DISABLE. */ 64 uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and 65 enable the trigger of a regular group. 66 This parameter can be a value of 67 @ref ADC_external_trigger_edge_for_regular_channels_conversion */ 68 uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger 69 the start of conversion of a regular group. 70 This parameter can be a value of 71 @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ 72 uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment 73 is left or right. This parameter can be 74 a value of @ref ADC_data_align */ 75 uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions 76 that will be done using the sequencer for 77 regular channel group. 78 This parameter must range from 1 to 16. */ 79 }ADC_InitTypeDef; 80 81 /** 82 * @brief ADC Common Init structure definition 83 */ 84 typedef struct 85 { 86 uint32_t ADC_Mode; /*!< Configures the ADC to operate in 87 independent or multi mode. 88 This parameter can be a value of @ref ADC_Common_mode */ 89 uint32_t ADC_Prescaler; /*!< Select the frequency of the clock 90 to the ADC. The clock is common for all the ADCs. 91 This parameter can be a value of @ref ADC_Prescaler */ 92 uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access 93 mode for multi ADC mode. 94 This parameter can be a value of 95 @ref ADC_Direct_memory_access_mode_for_multi_mode */ 96 uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 97 This parameter can be a value of 98 @ref ADC_delay_between_2_sampling_phases */ 99 100 }ADC_CommonInitTypeDef; 101 102 103 /* Exported constants --------------------------------------------------------*/ 104 105 /** @defgroup ADC_Exported_Constants 106 * @{ 107 */ 108 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ 109 ((PERIPH) == ADC2) || \ 110 ((PERIPH) == ADC3)) 111 112 /** @defgroup ADC_Common_mode 113 * @{ 114 */ 115 #define ADC_Mode_Independent ((uint32_t)0x00000000) 116 #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) 117 #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) 118 #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) 119 #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) 120 #define ADC_DualMode_Interl ((uint32_t)0x00000007) 121 #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) 122 #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) 123 #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) 124 #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) 125 #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) 126 #define ADC_TripleMode_Interl ((uint32_t)0x00000017) 127 #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) 128 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ 129 ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ 130 ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ 131 ((MODE) == ADC_DualMode_InjecSimult) || \ 132 ((MODE) == ADC_DualMode_RegSimult) || \ 133 ((MODE) == ADC_DualMode_Interl) || \ 134 ((MODE) == ADC_DualMode_AlterTrig) || \ 135 ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ 136 ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ 137 ((MODE) == ADC_TripleMode_InjecSimult) || \ 138 ((MODE) == ADC_TripleMode_RegSimult) || \ 139 ((MODE) == ADC_TripleMode_Interl) || \ 140 ((MODE) == ADC_TripleMode_AlterTrig)) 141 /** 142 * @} 143 */ 144 145 146 /** @defgroup ADC_Prescaler 147 * @{ 148 */ 149 #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) 150 #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) 151 #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) 152 #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) 153 #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ 154 ((PRESCALER) == ADC_Prescaler_Div4) || \ 155 ((PRESCALER) == ADC_Prescaler_Div6) || \ 156 ((PRESCALER) == ADC_Prescaler_Div8)) 157 /** 158 * @} 159 */ 160 161 162 /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 163 * @{ 164 */ 165 #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ 166 #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ 167 #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ 168 #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ 169 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ 170 ((MODE) == ADC_DMAAccessMode_1) || \ 171 ((MODE) == ADC_DMAAccessMode_2) || \ 172 ((MODE) == ADC_DMAAccessMode_3)) 173 174 /** 175 * @} 176 */ 177 178 179 /** @defgroup ADC_delay_between_2_sampling_phases 180 * @{ 181 */ 182 #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) 183 #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) 184 #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) 185 #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) 186 #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) 187 #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) 188 #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) 189 #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) 190 #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) 191 #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) 192 #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) 193 #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) 194 #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) 195 #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) 196 #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) 197 #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) 198 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ 199 ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ 200 ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ 201 ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ 202 ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ 203 ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ 204 ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ 205 ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ 206 ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ 207 ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ 208 ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ 209 ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ 210 ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ 211 ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ 212 ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ 213 ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) 214 215 /** 216 * @} 217 */ 218 219 220 /** @defgroup ADC_resolution 221 * @{ 222 */ 223 #define ADC_Resolution_12b ((uint32_t)0x00000000) 224 #define ADC_Resolution_10b ((uint32_t)0x01000000) 225 #define ADC_Resolution_8b ((uint32_t)0x02000000) 226 #define ADC_Resolution_6b ((uint32_t)0x03000000) 227 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ 228 ((RESOLUTION) == ADC_Resolution_10b) || \ 229 ((RESOLUTION) == ADC_Resolution_8b) || \ 230 ((RESOLUTION) == ADC_Resolution_6b)) 231 232 /** 233 * @} 234 */ 235 236 237 /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 238 * @{ 239 */ 240 #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) 241 #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) 242 #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) 243 #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) 244 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ 245 ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ 246 ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ 247 ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) 248 /** 249 * @} 250 */ 251 252 253 /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 254 * @{ 255 */ 256 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) 257 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) 258 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) 259 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) 260 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) 261 #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) 262 #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) 263 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) 264 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) 265 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) 266 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) 267 #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) 268 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) 269 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) 270 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) 271 #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) 272 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ 273 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ 274 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ 275 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ 276 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ 277 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ 278 ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ 279 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ 280 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ 281 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ 282 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ 283 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ 284 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ 285 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ 286 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ 287 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) 288 /** 289 * @} 290 */ 291 292 293 /** @defgroup ADC_data_align 294 * @{ 295 */ 296 #define ADC_DataAlign_Right ((uint32_t)0x00000000) 297 #define ADC_DataAlign_Left ((uint32_t)0x00000800) 298 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ 299 ((ALIGN) == ADC_DataAlign_Left)) 300 /** 301 * @} 302 */ 303 304 305 /** @defgroup ADC_channels 306 * @{ 307 */ 308 #define ADC_Channel_0 ((uint8_t)0x00) 309 #define ADC_Channel_1 ((uint8_t)0x01) 310 #define ADC_Channel_2 ((uint8_t)0x02) 311 #define ADC_Channel_3 ((uint8_t)0x03) 312 #define ADC_Channel_4 ((uint8_t)0x04) 313 #define ADC_Channel_5 ((uint8_t)0x05) 314 #define ADC_Channel_6 ((uint8_t)0x06) 315 #define ADC_Channel_7 ((uint8_t)0x07) 316 #define ADC_Channel_8 ((uint8_t)0x08) 317 #define ADC_Channel_9 ((uint8_t)0x09) 318 #define ADC_Channel_10 ((uint8_t)0x0A) 319 #define ADC_Channel_11 ((uint8_t)0x0B) 320 #define ADC_Channel_12 ((uint8_t)0x0C) 321 #define ADC_Channel_13 ((uint8_t)0x0D) 322 #define ADC_Channel_14 ((uint8_t)0x0E) 323 #define ADC_Channel_15 ((uint8_t)0x0F) 324 #define ADC_Channel_16 ((uint8_t)0x10) 325 #define ADC_Channel_17 ((uint8_t)0x11) 326 #define ADC_Channel_18 ((uint8_t)0x12) 327 328 #if defined (STM32F40_41xxx) 329 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) 330 #endif /* STM32F40_41xxx */ 331 332 #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) 333 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) 334 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 335 336 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) 337 #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) 338 339 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ 340 ((CHANNEL) == ADC_Channel_1) || \ 341 ((CHANNEL) == ADC_Channel_2) || \ 342 ((CHANNEL) == ADC_Channel_3) || \ 343 ((CHANNEL) == ADC_Channel_4) || \ 344 ((CHANNEL) == ADC_Channel_5) || \ 345 ((CHANNEL) == ADC_Channel_6) || \ 346 ((CHANNEL) == ADC_Channel_7) || \ 347 ((CHANNEL) == ADC_Channel_8) || \ 348 ((CHANNEL) == ADC_Channel_9) || \ 349 ((CHANNEL) == ADC_Channel_10) || \ 350 ((CHANNEL) == ADC_Channel_11) || \ 351 ((CHANNEL) == ADC_Channel_12) || \ 352 ((CHANNEL) == ADC_Channel_13) || \ 353 ((CHANNEL) == ADC_Channel_14) || \ 354 ((CHANNEL) == ADC_Channel_15) || \ 355 ((CHANNEL) == ADC_Channel_16) || \ 356 ((CHANNEL) == ADC_Channel_17) || \ 357 ((CHANNEL) == ADC_Channel_18)) 358 /** 359 * @} 360 */ 361 362 363 /** @defgroup ADC_sampling_times 364 * @{ 365 */ 366 #define ADC_SampleTime_3Cycles ((uint8_t)0x00) 367 #define ADC_SampleTime_15Cycles ((uint8_t)0x01) 368 #define ADC_SampleTime_28Cycles ((uint8_t)0x02) 369 #define ADC_SampleTime_56Cycles ((uint8_t)0x03) 370 #define ADC_SampleTime_84Cycles ((uint8_t)0x04) 371 #define ADC_SampleTime_112Cycles ((uint8_t)0x05) 372 #define ADC_SampleTime_144Cycles ((uint8_t)0x06) 373 #define ADC_SampleTime_480Cycles ((uint8_t)0x07) 374 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ 375 ((TIME) == ADC_SampleTime_15Cycles) || \ 376 ((TIME) == ADC_SampleTime_28Cycles) || \ 377 ((TIME) == ADC_SampleTime_56Cycles) || \ 378 ((TIME) == ADC_SampleTime_84Cycles) || \ 379 ((TIME) == ADC_SampleTime_112Cycles) || \ 380 ((TIME) == ADC_SampleTime_144Cycles) || \ 381 ((TIME) == ADC_SampleTime_480Cycles)) 382 /** 383 * @} 384 */ 385 386 387 /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 388 * @{ 389 */ 390 #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) 391 #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) 392 #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) 393 #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) 394 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ 395 ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ 396 ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ 397 ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) 398 399 /** 400 * @} 401 */ 402 403 404 /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 405 * @{ 406 */ 407 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) 408 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) 409 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) 410 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) 411 #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) 412 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) 413 #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) 414 #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) 415 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) 416 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) 417 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) 418 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) 419 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) 420 #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) 421 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) 422 #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) 423 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ 424 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ 425 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ 426 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ 427 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ 428 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ 429 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ 430 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ 431 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ 432 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ 433 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ 434 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ 435 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ 436 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ 437 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ 438 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) 439 /** 440 * @} 441 */ 442 443 444 /** @defgroup ADC_injected_channel_selection 445 * @{ 446 */ 447 #define ADC_InjectedChannel_1 ((uint8_t)0x14) 448 #define ADC_InjectedChannel_2 ((uint8_t)0x18) 449 #define ADC_InjectedChannel_3 ((uint8_t)0x1C) 450 #define ADC_InjectedChannel_4 ((uint8_t)0x20) 451 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ 452 ((CHANNEL) == ADC_InjectedChannel_2) || \ 453 ((CHANNEL) == ADC_InjectedChannel_3) || \ 454 ((CHANNEL) == ADC_InjectedChannel_4)) 455 /** 456 * @} 457 */ 458 459 460 /** @defgroup ADC_analog_watchdog_selection 461 * @{ 462 */ 463 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) 464 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) 465 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) 466 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) 467 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) 468 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) 469 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) 470 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ 471 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ 472 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ 473 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ 474 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ 475 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ 476 ((WATCHDOG) == ADC_AnalogWatchdog_None)) 477 /** 478 * @} 479 */ 480 481 482 /** @defgroup ADC_interrupts_definition 483 * @{ 484 */ 485 #define ADC_IT_EOC ((uint16_t)0x0205) 486 #define ADC_IT_AWD ((uint16_t)0x0106) 487 #define ADC_IT_JEOC ((uint16_t)0x0407) 488 #define ADC_IT_OVR ((uint16_t)0x201A) 489 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ 490 ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 491 /** 492 * @} 493 */ 494 495 496 /** @defgroup ADC_flags_definition 497 * @{ 498 */ 499 #define ADC_FLAG_AWD ((uint8_t)0x01) 500 #define ADC_FLAG_EOC ((uint8_t)0x02) 501 #define ADC_FLAG_JEOC ((uint8_t)0x04) 502 #define ADC_FLAG_JSTRT ((uint8_t)0x08) 503 #define ADC_FLAG_STRT ((uint8_t)0x10) 504 #define ADC_FLAG_OVR ((uint8_t)0x20) 505 506 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) 507 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ 508 ((FLAG) == ADC_FLAG_EOC) || \ 509 ((FLAG) == ADC_FLAG_JEOC) || \ 510 ((FLAG)== ADC_FLAG_JSTRT) || \ 511 ((FLAG) == ADC_FLAG_STRT) || \ 512 ((FLAG)== ADC_FLAG_OVR)) 513 /** 514 * @} 515 */ 516 517 518 /** @defgroup ADC_thresholds 519 * @{ 520 */ 521 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) 522 /** 523 * @} 524 */ 525 526 527 /** @defgroup ADC_injected_offset 528 * @{ 529 */ 530 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) 531 /** 532 * @} 533 */ 534 535 536 /** @defgroup ADC_injected_length 537 * @{ 538 */ 539 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) 540 /** 541 * @} 542 */ 543 544 545 /** @defgroup ADC_injected_rank 546 * @{ 547 */ 548 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) 549 /** 550 * @} 551 */ 552 553 554 /** @defgroup ADC_regular_length 555 * @{ 556 */ 557 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) 558 /** 559 * @} 560 */ 561 562 563 /** @defgroup ADC_regular_rank 564 * @{ 565 */ 566 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) 567 /** 568 * @} 569 */ 570 571 572 /** @defgroup ADC_regular_discontinuous_mode_number 573 * @{ 574 */ 575 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) 576 /** 577 * @} 578 */ 579 580 581 /** 582 * @} 583 */ 584 585 /* Exported macro ------------------------------------------------------------*/ 586 /* Exported functions --------------------------------------------------------*/ 587 588 /* Function used to set the ADC configuration to the default reset state *****/ 589 void ADC_DeInit(void); 590 591 /* Initialization and Configuration functions *********************************/ 592 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); 593 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); 594 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); 595 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); 596 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); 597 598 /* Analog Watchdog configuration functions ************************************/ 599 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); 600 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); 601 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); 602 603 /* Temperature Sensor, Vrefint and VBAT management functions ******************/ 604 void ADC_TempSensorVrefintCmd(FunctionalState NewState); 605 void ADC_VBATCmd(FunctionalState NewState); 606 607 /* Regular Channels Configuration functions ***********************************/ 608 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 609 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); 610 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); 611 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 612 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 613 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); 614 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 615 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); 616 uint32_t ADC_GetMultiModeConversionValue(void); 617 618 /* Regular Channels DMA Configuration functions *******************************/ 619 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); 620 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 621 void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); 622 623 /* Injected channels Configuration functions **********************************/ 624 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 625 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); 626 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); 627 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); 628 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); 629 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); 630 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); 631 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 632 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); 633 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); 634 635 /* Interrupts and flags management functions **********************************/ 636 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); 637 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); 638 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); 639 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); 640 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); 641 642 #ifdef __cplusplus 643 } 644 #endif 645 646 #endif /*__STM32F4xx_ADC_H */ 647 648 /** 649 * @} 650 */ 651 652 /** 653 * @} 654 */ 655 656 /************************ (C) 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