1 /**
2 ******************************************************************************
3 * @file stm32f4xx_flash.c
4 * @author MCD Application Team
5 * @version V1.5.1
6 * @date 22-May-2015
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the FLASH peripheral:
9 * + FLASH Interface configuration
10 * + FLASH Memory Programming
11 * + Option Bytes Programming
12 * + Interrupts and flags management
13 *
14 @verbatim
15 ===============================================================================
16 ##### How to use this driver #####
17 ===============================================================================
18 [..]
19 This driver provides functions to configure and program the FLASH memory
20 of all STM32F4xx devices. These functions are split in 4 groups:
21
22 (#) FLASH Interface configuration functions: this group includes the
23 management of the following features:
24 (++) Set the latency
25 (++) Enable/Disable the prefetch buffer
26 (++) Enable/Disable the Instruction cache and the Data cache
27 (++) Reset the Instruction cache and the Data cache
28
29 (#) FLASH Memory Programming functions: this group includes all needed
30 functions to erase and program the main memory:
31 (++) Lock and Unlock the FLASH interface
32 (++) Erase function: Erase sector, erase all sectors
33 (++) Program functions: byte, half word, word and double word
34
35 (#) Option Bytes Programming functions: this group includes all needed
36 functions to manage the Option Bytes:
37 (++) Set/Reset the write protection
38 (++) Set the Read protection Level
39 (++) Set the BOR level
40 (++) Program the user Option Bytes
41 (++) Launch the Option Bytes loader
42
43 (#) Interrupts and flags management functions: this group
44 includes all needed functions to:
45 (++) Enable/Disable the FLASH interrupt sources
46 (++) Get flags status
47 (++) Clear flags
48 (++) Get FLASH operation status
49 (++) Wait for last FLASH operation
50 @endverbatim
51 ******************************************************************************
52 * @attention
53 *
54 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
55 *
56 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
57 * You may not use this file except in compliance with the License.
58 * You may obtain a copy of the License at:
59 *
60 * http://www.st.com/software_license_agreement_liberty_v2
61 *
62 * Unless required by applicable law or agreed to in writing, software
63 * distributed under the License is distributed on an "AS IS" BASIS,
64 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
65 * See the License for the specific language governing permissions and
66 * limitations under the License.
67 *
68 ******************************************************************************
69 */
70
71 /* Includes ------------------------------------------------------------------*/
72 #include "stm32f4xx_flash.h"
73
74 /** @addtogroup STM32F4xx_StdPeriph_Driver
75 * @{
76 */
77
78 /** @defgroup FLASH
79 * @brief FLASH driver modules
80 * @{
81 */
82
83 /* Private typedef -----------------------------------------------------------*/
84 /* Private define ------------------------------------------------------------*/
85 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
86
87 /* Private macro -------------------------------------------------------------*/
88 /* Private variables ---------------------------------------------------------*/
89 /* Private function prototypes -----------------------------------------------*/
90 /* Private functions ---------------------------------------------------------*/
91
92 /** @defgroup FLASH_Private_Functions
93 * @{
94 */
95
96 /** @defgroup FLASH_Group1 FLASH Interface configuration functions
97 * @brief FLASH Interface configuration functions
98 *
99
100 @verbatim
101 ===============================================================================
102 ##### FLASH Interface configuration functions #####
103 ===============================================================================
104 [..]
105 This group includes the following functions:
106 (+) void FLASH_SetLatency(uint32_t FLASH_Latency)
107 To correctly read data from FLASH memory, the number of wait states (LATENCY)
108 must be correctly programmed according to the frequency of the CPU clock
109 (HCLK) and the supply voltage of the device.
110 [..]
111 For STM32F405xx/07xx and STM32F415xx/17xx devices
112 +-------------------------------------------------------------------------------------+
113 | Latency | HCLK clock frequency (MHz) |
114 | |---------------------------------------------------------------------|
115 | | voltage range | voltage range | voltage range | voltage range |
116 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
117 |---------------|----------------|----------------|-----------------|-----------------|
118 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
119 |---------------|----------------|----------------|-----------------|-----------------|
120 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
121 |---------------|----------------|----------------|-----------------|-----------------|
122 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
123 |---------------|----------------|----------------|-----------------|-----------------|
124 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
125 |---------------|----------------|----------------|-----------------|-----------------|
126 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
127 |---------------|----------------|----------------|-----------------|-----------------|
128 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
129 |---------------|----------------|----------------|-----------------|-----------------|
130 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
131 |---------------|----------------|----------------|-----------------|-----------------|
132 |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
133 +---------------|----------------|----------------|-----------------|-----------------+
134
135 [..]
136 For STM32F42xxx/43xxx devices
137 +-------------------------------------------------------------------------------------+
138 | Latency | HCLK clock frequency (MHz) |
139 | |---------------------------------------------------------------------|
140 | | voltage range | voltage range | voltage range | voltage range |
141 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
142 |---------------|----------------|----------------|-----------------|-----------------|
143 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
144 |---------------|----------------|----------------|-----------------|-----------------|
145 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
146 |---------------|----------------|----------------|-----------------|-----------------|
147 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
148 |---------------|----------------|----------------|-----------------|-----------------|
149 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
150 |---------------|----------------|----------------|-----------------|-----------------|
151 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
152 |---------------|----------------|----------------|-----------------|-----------------|
153 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
154 |---------------|----------------|----------------|-----------------|-----------------|
155 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
156 |---------------|----------------|----------------|-----------------|-----------------|
157 |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
158 |---------------|----------------|----------------|-----------------|-----------------|
159 |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
160 +-------------------------------------------------------------------------------------+
161
162 [..]
163 For STM32F401x devices
164 +-------------------------------------------------------------------------------------+
165 | Latency | HCLK clock frequency (MHz) |
166 | |---------------------------------------------------------------------|
167 | | voltage range | voltage range | voltage range | voltage range |
168 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
169 |---------------|----------------|----------------|-----------------|-----------------|
170 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
171 |---------------|----------------|----------------|-----------------|-----------------|
172 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
173 |---------------|----------------|----------------|-----------------|-----------------|
174 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
175 |---------------|----------------|----------------|-----------------|-----------------|
176 |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
177 |---------------|----------------|----------------|-----------------|-----------------|
178 |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
179 +-------------------------------------------------------------------------------------+
180
181 [..]
182 For STM32F411xE devices
183 +-------------------------------------------------------------------------------------+
184 | Latency | HCLK clock frequency (MHz) |
185 | |---------------------------------------------------------------------|
186 | | voltage range | voltage range | voltage range | voltage range |
187 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
188 |---------------|----------------|----------------|-----------------|-----------------|
189 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
190 |---------------|----------------|----------------|-----------------|-----------------|
191 |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
192 |---------------|----------------|----------------|-----------------|-----------------|
193 |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
194 |---------------|----------------|----------------|-----------------|-----------------|
195 |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
196 |---------------|----------------|----------------|-----------------|-----------------|
197 |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
198 |---------------|----------------|----------------|-----------------|-----------------|
199 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
200 |---------------|----------------|----------------|-----------------|-----------------|
201 |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
202 +-------------------------------------------------------------------------------------+
203
204 [..]
205 +-------------------------------------------------------------------------------------------------------------------+
206 | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
207 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
208 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
209 |Max Parallelism| x32 | x16 | x8 | x64 |
210 |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
211 |PSIZE[1:0] | 10 | 01 | 00 | 11 |
212 +-------------------------------------------------------------------------------------------------------------------+
213
214 -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
215 (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz.
216 (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz.
217 [..]
218 On STM32F42xxx/43xxx devices:
219 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz.
220 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON.
221 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON.
222 [..]
223 On STM32F401x devices:
224 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
225 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
226 [..]
227 On STM32F411xE devices:
228 (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
229 (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
230 (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
231
232 For more details please refer product DataSheet
233 You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
234
235 (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState)
236 (+) void FLASH_InstructionCacheCmd(FunctionalState NewState)
237 (+) void FLASH_DataCacheCmd(FunctionalState NewState)
238 (+) void FLASH_InstructionCacheReset(void)
239 (+) void FLASH_DataCacheReset(void)
240
241 [..]
242 The unlock sequence is not needed for these functions.
243
244 @endverbatim
245 * @{
246 */
247
248 /**
249 * @brief Sets the code latency value.
250 * @param FLASH_Latency: specifies the FLASH Latency value.
251 * This parameter can be one of the following values:
252 * @arg FLASH_Latency_0: FLASH Zero Latency cycle
253 * @arg FLASH_Latency_1: FLASH One Latency cycle
254 * @arg FLASH_Latency_2: FLASH Two Latency cycles
255 * @arg FLASH_Latency_3: FLASH Three Latency cycles
256 * @arg FLASH_Latency_4: FLASH Four Latency cycles
257 * @arg FLASH_Latency_5: FLASH Five Latency cycles
258 * @arg FLASH_Latency_6: FLASH Six Latency cycles
259 * @arg FLASH_Latency_7: FLASH Seven Latency cycles
260 * @arg FLASH_Latency_8: FLASH Eight Latency cycles
261 * @arg FLASH_Latency_9: FLASH Nine Latency cycles
262 * @arg FLASH_Latency_10: FLASH Teen Latency cycles
263 * @arg FLASH_Latency_11: FLASH Eleven Latency cycles
264 * @arg FLASH_Latency_12: FLASH Twelve Latency cycles
265 * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles
266 * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
267 * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
268 *
269 * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter
270 * can be a value between FLASH_Latency_0 and FLASH_Latency_7.
271 *
272 * @note For STM32F42xxx/43xxx devices this parameter can be a value between
273 * FLASH_Latency_0 and FLASH_Latency_15.
274 *
275 * @retval None
276 */
FLASH_SetLatency(uint32_t FLASH_Latency)277 void FLASH_SetLatency(uint32_t FLASH_Latency)
278 {
279 /* Check the parameters */
280 assert_param(IS_FLASH_LATENCY(FLASH_Latency));
281
282 /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
283 *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
284 }
285
286 /**
287 * @brief Enables or disables the Prefetch Buffer.
288 * @param NewState: new state of the Prefetch Buffer.
289 * This parameter can be: ENABLE or DISABLE.
290 * @retval None
291 */
FLASH_PrefetchBufferCmd(FunctionalState NewState)292 void FLASH_PrefetchBufferCmd(FunctionalState NewState)
293 {
294 /* Check the parameters */
295 assert_param(IS_FUNCTIONAL_STATE(NewState));
296
297 /* Enable or disable the Prefetch Buffer */
298 if(NewState != DISABLE)
299 {
300 FLASH->ACR |= FLASH_ACR_PRFTEN;
301 }
302 else
303 {
304 FLASH->ACR &= (~FLASH_ACR_PRFTEN);
305 }
306 }
307
308 /**
309 * @brief Enables or disables the Instruction Cache feature.
310 * @param NewState: new state of the Instruction Cache.
311 * This parameter can be: ENABLE or DISABLE.
312 * @retval None
313 */
FLASH_InstructionCacheCmd(FunctionalState NewState)314 void FLASH_InstructionCacheCmd(FunctionalState NewState)
315 {
316 /* Check the parameters */
317 assert_param(IS_FUNCTIONAL_STATE(NewState));
318
319 if(NewState != DISABLE)
320 {
321 FLASH->ACR |= FLASH_ACR_ICEN;
322 }
323 else
324 {
325 FLASH->ACR &= (~FLASH_ACR_ICEN);
326 }
327 }
328
329 /**
330 * @brief Enables or disables the Data Cache feature.
331 * @param NewState: new state of the Data Cache.
332 * This parameter can be: ENABLE or DISABLE.
333 * @retval None
334 */
FLASH_DataCacheCmd(FunctionalState NewState)335 void FLASH_DataCacheCmd(FunctionalState NewState)
336 {
337 /* Check the parameters */
338 assert_param(IS_FUNCTIONAL_STATE(NewState));
339
340 if(NewState != DISABLE)
341 {
342 FLASH->ACR |= FLASH_ACR_DCEN;
343 }
344 else
345 {
346 FLASH->ACR &= (~FLASH_ACR_DCEN);
347 }
348 }
349
350 /**
351 * @brief Resets the Instruction Cache.
352 * @note This function must be used only when the Instruction Cache is disabled.
353 * @param None
354 * @retval None
355 */
FLASH_InstructionCacheReset(void)356 void FLASH_InstructionCacheReset(void)
357 {
358 FLASH->ACR |= FLASH_ACR_ICRST;
359 }
360
361 /**
362 * @brief Resets the Data Cache.
363 * @note This function must be used only when the Data Cache is disabled.
364 * @param None
365 * @retval None
366 */
FLASH_DataCacheReset(void)367 void FLASH_DataCacheReset(void)
368 {
369 FLASH->ACR |= FLASH_ACR_DCRST;
370 }
371
372 /**
373 * @}
374 */
375
376 /** @defgroup FLASH_Group2 FLASH Memory Programming functions
377 * @brief FLASH Memory Programming functions
378 *
379 @verbatim
380 ===============================================================================
381 ##### FLASH Memory Programming functions #####
382 ===============================================================================
383 [..]
384 This group includes the following functions:
385 (+) void FLASH_Unlock(void)
386 (+) void FLASH_Lock(void)
387 (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
388 (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
389 (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
390 (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
391 (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
392 (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
393 The following functions can be used only for STM32F42xxx/43xxx devices.
394 (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
395 (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
396 [..]
397 Any operation of erase or program should follow these steps:
398 (#) Call the FLASH_Unlock() function to enable the FLASH control register access
399
400 (#) Call the desired function to erase sector(s) or program data
401
402 (#) Call the FLASH_Lock() function to disable the FLASH control register access
403 (recommended to protect the FLASH memory against possible unwanted operation)
404
405 @endverbatim
406 * @{
407 */
408
409 /**
410 * @brief Unlocks the FLASH control register access
411 * @param None
412 * @retval None
413 */
FLASH_Unlock(void)414 void FLASH_Unlock(void)
415 {
416 if((FLASH->CR & FLASH_CR_LOCK) != RESET)
417 {
418 /* Authorize the FLASH Registers access */
419 FLASH->KEYR = FLASH_KEY1;
420 FLASH->KEYR = FLASH_KEY2;
421 }
422 }
423
424 /**
425 * @brief Locks the FLASH control register access
426 * @param None
427 * @retval None
428 */
FLASH_Lock(void)429 void FLASH_Lock(void)
430 {
431 /* Set the LOCK Bit to lock the FLASH Registers access */
432 FLASH->CR |= FLASH_CR_LOCK;
433 }
434
435 /**
436 * @brief Erases a specified FLASH Sector.
437 *
438 * @note If an erase and a program operations are requested simultaneously,
439 * the erase operation is performed before the program one.
440 *
441 * @param FLASH_Sector: The Sector number to be erased.
442 *
443 * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can
444 * be a value between FLASH_Sector_0 and FLASH_Sector_11.
445 *
446 * For STM32F42xxx/43xxx devices this parameter can be a value between
447 * FLASH_Sector_0 and FLASH_Sector_23.
448 *
449 * For STM32F401xx devices this parameter can be a value between
450 * FLASH_Sector_0 and FLASH_Sector_5.
451 *
452 * For STM32F411xE devices this parameter can be a value between
453 * FLASH_Sector_0 and FLASH_Sector_7.
454 *
455 * @param VoltageRange: The device voltage range which defines the erase parallelism.
456 * This parameter can be one of the following values:
457 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
458 * the operation will be done by byte (8-bit)
459 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
460 * the operation will be done by half word (16-bit)
461 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
462 * the operation will be done by word (32-bit)
463 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
464 * the operation will be done by double word (64-bit)
465 *
466 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
467 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
468 */
FLASH_EraseSector(uint32_t FLASH_Sector,uint8_t VoltageRange)469 FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
470 {
471 uint32_t tmp_psize = 0x0;
472 FLASH_Status status = FLASH_COMPLETE;
473
474 /* Check the parameters */
475 assert_param(IS_FLASH_SECTOR(FLASH_Sector));
476 assert_param(IS_VOLTAGERANGE(VoltageRange));
477
478 if(VoltageRange == VoltageRange_1)
479 {
480 tmp_psize = FLASH_PSIZE_BYTE;
481 }
482 else if(VoltageRange == VoltageRange_2)
483 {
484 tmp_psize = FLASH_PSIZE_HALF_WORD;
485 }
486 else if(VoltageRange == VoltageRange_3)
487 {
488 tmp_psize = FLASH_PSIZE_WORD;
489 }
490 else
491 {
492 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
493 }
494 /* Wait for last operation to be completed */
495 status = FLASH_WaitForLastOperation();
496
497 if(status == FLASH_COMPLETE)
498 {
499 /* if the previous operation is completed, proceed to erase the sector */
500 FLASH->CR &= CR_PSIZE_MASK;
501 FLASH->CR |= tmp_psize;
502 FLASH->CR &= SECTOR_MASK;
503 FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
504 FLASH->CR |= FLASH_CR_STRT;
505
506 /* Wait for last operation to be completed */
507 status = FLASH_WaitForLastOperation();
508
509 /* if the erase operation is completed, disable the SER Bit */
510 FLASH->CR &= (~FLASH_CR_SER);
511 FLASH->CR &= SECTOR_MASK;
512 }
513 /* Return the Erase Status */
514 return status;
515 }
516
517 /**
518 * @brief Erases all FLASH Sectors.
519 *
520 * @note If an erase and a program operations are requested simultaneously,
521 * the erase operation is performed before the program one.
522 *
523 * @param VoltageRange: The device voltage range which defines the erase parallelism.
524 * This parameter can be one of the following values:
525 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
526 * the operation will be done by byte (8-bit)
527 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
528 * the operation will be done by half word (16-bit)
529 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
530 * the operation will be done by word (32-bit)
531 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
532 * the operation will be done by double word (64-bit)
533 *
534 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
535 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
536 */
FLASH_EraseAllSectors(uint8_t VoltageRange)537 FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
538 {
539 uint32_t tmp_psize = 0x0;
540 FLASH_Status status = FLASH_COMPLETE;
541
542 /* Wait for last operation to be completed */
543 status = FLASH_WaitForLastOperation();
544 assert_param(IS_VOLTAGERANGE(VoltageRange));
545
546 if(VoltageRange == VoltageRange_1)
547 {
548 tmp_psize = FLASH_PSIZE_BYTE;
549 }
550 else if(VoltageRange == VoltageRange_2)
551 {
552 tmp_psize = FLASH_PSIZE_HALF_WORD;
553 }
554 else if(VoltageRange == VoltageRange_3)
555 {
556 tmp_psize = FLASH_PSIZE_WORD;
557 }
558 else
559 {
560 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
561 }
562 if(status == FLASH_COMPLETE)
563 {
564 /* if the previous operation is completed, proceed to erase all sectors */
565 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
566 FLASH->CR &= CR_PSIZE_MASK;
567 FLASH->CR |= tmp_psize;
568 FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
569 FLASH->CR |= FLASH_CR_STRT;
570
571 /* Wait for last operation to be completed */
572 status = FLASH_WaitForLastOperation();
573
574 /* if the erase operation is completed, disable the MER Bit */
575 FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
576 #endif /* STM32F427_437xx || STM32F429_439xx */
577
578 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx)
579 FLASH->CR &= CR_PSIZE_MASK;
580 FLASH->CR |= tmp_psize;
581 FLASH->CR |= FLASH_CR_MER;
582 FLASH->CR |= FLASH_CR_STRT;
583
584 /* Wait for last operation to be completed */
585 status = FLASH_WaitForLastOperation();
586
587 /* if the erase operation is completed, disable the MER Bit */
588 FLASH->CR &= (~FLASH_CR_MER);
589 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
590
591 }
592 /* Return the Erase Status */
593 return status;
594 }
595
596 /**
597 * @brief Erases all FLASH Sectors in Bank 1.
598 *
599 * @note This function can be used only for STM32F42xxx/43xxx devices.
600 *
601 * @note If an erase and a program operations are requested simultaneously,
602 * the erase operation is performed before the program one.
603 *
604 * @param VoltageRange: The device voltage range which defines the erase parallelism.
605 * This parameter can be one of the following values:
606 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
607 * the operation will be done by byte (8-bit)
608 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
609 * the operation will be done by half word (16-bit)
610 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
611 * the operation will be done by word (32-bit)
612 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
613 * the operation will be done by double word (64-bit)
614 *
615 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
616 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
617 */
FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)618 FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange)
619 {
620 uint32_t tmp_psize = 0x0;
621 FLASH_Status status = FLASH_COMPLETE;
622
623 /* Wait for last operation to be completed */
624 status = FLASH_WaitForLastOperation();
625 assert_param(IS_VOLTAGERANGE(VoltageRange));
626
627 if(VoltageRange == VoltageRange_1)
628 {
629 tmp_psize = FLASH_PSIZE_BYTE;
630 }
631 else if(VoltageRange == VoltageRange_2)
632 {
633 tmp_psize = FLASH_PSIZE_HALF_WORD;
634 }
635 else if(VoltageRange == VoltageRange_3)
636 {
637 tmp_psize = FLASH_PSIZE_WORD;
638 }
639 else
640 {
641 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
642 }
643 if(status == FLASH_COMPLETE)
644 {
645 /* if the previous operation is completed, proceed to erase all sectors */
646 FLASH->CR &= CR_PSIZE_MASK;
647 FLASH->CR |= tmp_psize;
648 FLASH->CR |= FLASH_CR_MER1;
649 FLASH->CR |= FLASH_CR_STRT;
650
651 /* Wait for last operation to be completed */
652 status = FLASH_WaitForLastOperation();
653
654 /* if the erase operation is completed, disable the MER Bit */
655 FLASH->CR &= (~FLASH_CR_MER1);
656
657 }
658 /* Return the Erase Status */
659 return status;
660 }
661
662
663 /**
664 * @brief Erases all FLASH Sectors in Bank 2.
665 *
666 * @note This function can be used only for STM32F42xxx/43xxx devices.
667 *
668 * @note If an erase and a program operations are requested simultaneously,
669 * the erase operation is performed before the program one.
670 *
671 * @param VoltageRange: The device voltage range which defines the erase parallelism.
672 * This parameter can be one of the following values:
673 * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
674 * the operation will be done by byte (8-bit)
675 * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
676 * the operation will be done by half word (16-bit)
677 * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
678 * the operation will be done by word (32-bit)
679 * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
680 * the operation will be done by double word (64-bit)
681 *
682 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
683 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
684 */
FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)685 FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
686 {
687 uint32_t tmp_psize = 0x0;
688 FLASH_Status status = FLASH_COMPLETE;
689
690 /* Wait for last operation to be completed */
691 status = FLASH_WaitForLastOperation();
692 assert_param(IS_VOLTAGERANGE(VoltageRange));
693
694 if(VoltageRange == VoltageRange_1)
695 {
696 tmp_psize = FLASH_PSIZE_BYTE;
697 }
698 else if(VoltageRange == VoltageRange_2)
699 {
700 tmp_psize = FLASH_PSIZE_HALF_WORD;
701 }
702 else if(VoltageRange == VoltageRange_3)
703 {
704 tmp_psize = FLASH_PSIZE_WORD;
705 }
706 else
707 {
708 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
709 }
710 if(status == FLASH_COMPLETE)
711 {
712 /* if the previous operation is completed, proceed to erase all sectors */
713 FLASH->CR &= CR_PSIZE_MASK;
714 FLASH->CR |= tmp_psize;
715 FLASH->CR |= FLASH_CR_MER2;
716 FLASH->CR |= FLASH_CR_STRT;
717
718 /* Wait for last operation to be completed */
719 status = FLASH_WaitForLastOperation();
720
721 /* if the erase operation is completed, disable the MER Bit */
722 FLASH->CR &= (~FLASH_CR_MER2);
723
724 }
725 /* Return the Erase Status */
726 return status;
727 }
728
729 /**
730 * @brief Programs a double word (64-bit) at a specified address.
731 * @note This function must be used when the device voltage range is from
732 * 2.7V to 3.6V and an External Vpp is present.
733 *
734 * @note If an erase and a program operations are requested simultaneously,
735 * the erase operation is performed before the program one.
736 *
737 * @param Address: specifies the address to be programmed.
738 * @param Data: specifies the data to be programmed.
739 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
740 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
741 */
FLASH_ProgramDoubleWord(uint32_t Address,uint64_t Data)742 FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
743 {
744 FLASH_Status status = FLASH_COMPLETE;
745
746 /* Check the parameters */
747 assert_param(IS_FLASH_ADDRESS(Address));
748
749 /* Wait for last operation to be completed */
750 status = FLASH_WaitForLastOperation();
751
752 if(status == FLASH_COMPLETE)
753 {
754 /* if the previous operation is completed, proceed to program the new data */
755 FLASH->CR &= CR_PSIZE_MASK;
756 FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
757 FLASH->CR |= FLASH_CR_PG;
758
759 *(__IO uint64_t*)Address = Data;
760
761 /* Wait for last operation to be completed */
762 status = FLASH_WaitForLastOperation();
763
764 /* if the program operation is completed, disable the PG Bit */
765 FLASH->CR &= (~FLASH_CR_PG);
766 }
767 /* Return the Program Status */
768 return status;
769 }
770
771 /**
772 * @brief Programs a word (32-bit) at a specified address.
773 *
774 * @note This function must be used when the device voltage range is from 2.7V to 3.6V.
775 *
776 * @note If an erase and a program operations are requested simultaneously,
777 * the erase operation is performed before the program one.
778 *
779 * @param Address: specifies the address to be programmed.
780 * This parameter can be any address in Program memory zone or in OTP zone.
781 * @param Data: specifies the data to be programmed.
782 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
783 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
784 */
FLASH_ProgramWord(uint32_t Address,uint32_t Data)785 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
786 {
787 FLASH_Status status = FLASH_COMPLETE;
788
789 /* Check the parameters */
790 assert_param(IS_FLASH_ADDRESS(Address));
791
792 /* Wait for last operation to be completed */
793 status = FLASH_WaitForLastOperation();
794
795 if(status == FLASH_COMPLETE)
796 {
797 /* if the previous operation is completed, proceed to program the new data */
798 FLASH->CR &= CR_PSIZE_MASK;
799 FLASH->CR |= FLASH_PSIZE_WORD;
800 FLASH->CR |= FLASH_CR_PG;
801
802 *(__IO uint32_t*)Address = Data;
803
804 /* Wait for last operation to be completed */
805 status = FLASH_WaitForLastOperation();
806
807 /* if the program operation is completed, disable the PG Bit */
808 FLASH->CR &= (~FLASH_CR_PG);
809 }
810 /* Return the Program Status */
811 return status;
812 }
813
814 /**
815 * @brief Programs a half word (16-bit) at a specified address.
816 * @note This function must be used when the device voltage range is from 2.1V to 3.6V.
817 *
818 * @note If an erase and a program operations are requested simultaneously,
819 * the erase operation is performed before the program one.
820 *
821 * @param Address: specifies the address to be programmed.
822 * This parameter can be any address in Program memory zone or in OTP zone.
823 * @param Data: specifies the data to be programmed.
824 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
825 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
826 */
FLASH_ProgramHalfWord(uint32_t Address,uint16_t Data)827 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
828 {
829 FLASH_Status status = FLASH_COMPLETE;
830
831 /* Check the parameters */
832 assert_param(IS_FLASH_ADDRESS(Address));
833
834 /* Wait for last operation to be completed */
835 status = FLASH_WaitForLastOperation();
836
837 if(status == FLASH_COMPLETE)
838 {
839 /* if the previous operation is completed, proceed to program the new data */
840 FLASH->CR &= CR_PSIZE_MASK;
841 FLASH->CR |= FLASH_PSIZE_HALF_WORD;
842 FLASH->CR |= FLASH_CR_PG;
843
844 *(__IO uint16_t*)Address = Data;
845
846 /* Wait for last operation to be completed */
847 status = FLASH_WaitForLastOperation();
848
849 /* if the program operation is completed, disable the PG Bit */
850 FLASH->CR &= (~FLASH_CR_PG);
851 }
852 /* Return the Program Status */
853 return status;
854 }
855
856 /**
857 * @brief Programs a byte (8-bit) at a specified address.
858 * @note This function can be used within all the device supply voltage ranges.
859 *
860 * @note If an erase and a program operations are requested simultaneously,
861 * the erase operation is performed before the program one.
862 *
863 * @param Address: specifies the address to be programmed.
864 * This parameter can be any address in Program memory zone or in OTP zone.
865 * @param Data: specifies the data to be programmed.
866 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
867 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
868 */
FLASH_ProgramByte(uint32_t Address,uint8_t Data)869 FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
870 {
871 FLASH_Status status = FLASH_COMPLETE;
872
873 /* Check the parameters */
874 assert_param(IS_FLASH_ADDRESS(Address));
875
876 /* Wait for last operation to be completed */
877 status = FLASH_WaitForLastOperation();
878
879 if(status == FLASH_COMPLETE)
880 {
881 /* if the previous operation is completed, proceed to program the new data */
882 FLASH->CR &= CR_PSIZE_MASK;
883 FLASH->CR |= FLASH_PSIZE_BYTE;
884 FLASH->CR |= FLASH_CR_PG;
885
886 *(__IO uint8_t*)Address = Data;
887
888 /* Wait for last operation to be completed */
889 status = FLASH_WaitForLastOperation();
890
891 /* if the program operation is completed, disable the PG Bit */
892 FLASH->CR &= (~FLASH_CR_PG);
893 }
894
895 /* Return the Program Status */
896 return status;
897 }
898
899 /**
900 * @}
901 */
902
903 /** @defgroup FLASH_Group3 Option Bytes Programming functions
904 * @brief Option Bytes Programming functions
905 *
906 @verbatim
907 ===============================================================================
908 ##### Option Bytes Programming functions #####
909 ===============================================================================
910 [..]
911 This group includes the following functions:
912 (+) void FLASH_OB_Unlock(void)
913 (+) void FLASH_OB_Lock(void)
914 (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
915 (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
916 (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect)
917 (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
918 (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
919 (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP)
920 (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
921 (+) void FLASH_OB_BORConfig(uint8_t OB_BOR)
922 (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)
923 (+) FLASH_Status FLASH_OB_Launch(void)
924 (+) uint32_t FLASH_OB_GetUser(void)
925 (+) uint8_t FLASH_OB_GetWRP(void)
926 (+) uint8_t FLASH_OB_GetWRP1(void)
927 (+) uint8_t FLASH_OB_GetPCROP(void)
928 (+) uint8_t FLASH_OB_GetPCROP1(void)
929 (+) uint8_t FLASH_OB_GetRDP(void)
930 (+) uint8_t FLASH_OB_GetBOR(void)
931 [..]
932 The following function can be used only for STM32F42xxx/43xxx devices.
933 (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT)
934 [..]
935 Any operation of erase or program should follow these steps:
936 (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
937 register access
938
939 (#) Call one or several functions to program the desired Option Bytes:
940 (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
941 => to Enable/Disable the desired sector write protection
942 (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read
943 Protection Level
944 (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
945 => to configure the user Option Bytes.
946 (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level
947
948 (#) Once all needed Option Bytes to be programmed are correctly written,
949 call the FLASH_OB_Launch() function to launch the Option Bytes
950 programming process.
951
952 -@- When changing the IWDG mode from HW to SW or from SW to HW, a system
953 reset is needed to make the change effective.
954
955 (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
956 register access (recommended to protect the Option Bytes against
957 possible unwanted operations)
958
959 @endverbatim
960 * @{
961 */
962
963 /**
964 * @brief Unlocks the FLASH Option Control Registers access.
965 * @param None
966 * @retval None
967 */
FLASH_OB_Unlock(void)968 void FLASH_OB_Unlock(void)
969 {
970 if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
971 {
972 /* Authorizes the Option Byte register programming */
973 FLASH->OPTKEYR = FLASH_OPT_KEY1;
974 FLASH->OPTKEYR = FLASH_OPT_KEY2;
975 }
976 }
977
978 /**
979 * @brief Locks the FLASH Option Control Registers access.
980 * @param None
981 * @retval None
982 */
FLASH_OB_Lock(void)983 void FLASH_OB_Lock(void)
984 {
985 /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
986 FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
987 }
988
989 /**
990 * @brief Enables or disables the write protection of the desired sectors, for the first
991 * 1 Mb of the Flash
992 *
993 * @note When the memory read protection level is selected (RDP level = 1),
994 * it is not possible to program or erase the flash sector i if CortexM4
995 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
996 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
997 *
998 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
999 * This parameter can be one of the following values:
1000 * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11
1001 * @arg OB_WRP_Sector_All
1002 * @param Newstate: new state of the Write Protection.
1003 * This parameter can be: ENABLE or DISABLE.
1004 * @retval None
1005 */
FLASH_OB_WRPConfig(uint32_t OB_WRP,FunctionalState NewState)1006 void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
1007 {
1008 FLASH_Status status = FLASH_COMPLETE;
1009
1010 /* Check the parameters */
1011 assert_param(IS_OB_WRP(OB_WRP));
1012 assert_param(IS_FUNCTIONAL_STATE(NewState));
1013
1014 status = FLASH_WaitForLastOperation();
1015
1016 if(status == FLASH_COMPLETE)
1017 {
1018 if(NewState != DISABLE)
1019 {
1020 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
1021 }
1022 else
1023 {
1024 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
1025 }
1026 }
1027 }
1028
1029 /**
1030 * @brief Enables or disables the write protection of the desired sectors, for the second
1031 * 1 Mb of the Flash
1032 *
1033 * @note This function can be used only for STM32F42xxx/43xxx devices.
1034 *
1035 * @note When the memory read out protection is selected (RDP level = 1),
1036 * it is not possible to program or erase the flash sector i if CortexM4
1037 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
1038 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
1039 *
1040 * @param OB_WRP: specifies the sector(s) to be write protected or unprotected.
1041 * This parameter can be one of the following values:
1042 * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23
1043 * @arg OB_WRP_Sector_All
1044 * @param Newstate: new state of the Write Protection.
1045 * This parameter can be: ENABLE or DISABLE.
1046 * @retval None
1047 */
FLASH_OB_WRP1Config(uint32_t OB_WRP,FunctionalState NewState)1048 void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState)
1049 {
1050 FLASH_Status status = FLASH_COMPLETE;
1051
1052 /* Check the parameters */
1053 assert_param(IS_OB_WRP(OB_WRP));
1054 assert_param(IS_FUNCTIONAL_STATE(NewState));
1055
1056 status = FLASH_WaitForLastOperation();
1057
1058 if(status == FLASH_COMPLETE)
1059 {
1060 if(NewState != DISABLE)
1061 {
1062 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP);
1063 }
1064 else
1065 {
1066 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
1067 }
1068 }
1069 }
1070
1071 /**
1072 * @brief Select the Protection Mode (SPRMOD).
1073 *
1074 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
1075 *
1076 * @note After PCROP activation, Option Byte modification is not possible.
1077 * Exception made for the global Read Out Protection modification level (level1 to level0)
1078 * @note Once SPRMOD bit is active unprotection of a protected sector is not possible
1079 *
1080 * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
1081 *
1082 * @note Some Precautions should be taken when activating the PCROP feature :
1083 * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1
1084 * and WRPi = 1 (default value), then the user sector i is read/write protected.
1085 * In order to avoid activation of PCROP Mode for undesired sectors, please follow the
1086 * below safety sequence :
1087 * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function
1088 * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2
1089 * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function
1090 * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function.
1091 *
1092 * @param OB_PCROP: Select the Protection Mode of nWPRi bits
1093 * This parameter can be one of the following values:
1094 * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors.
1095 * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors.
1096 * @retval None
1097 */
FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)1098 void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
1099 {
1100 uint8_t optiontmp = 0xFF;
1101
1102 /* Check the parameters */
1103 assert_param(IS_OB_PCROP_SELECT(OB_PcROP));
1104
1105 /* Mask SPRMOD bit */
1106 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
1107 /* Update Option Byte */
1108 *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp);
1109
1110 }
1111
1112 /**
1113 * @brief Enables or disables the read/write protection (PCROP) of the desired
1114 * sectors, for the first 1 MB of the Flash.
1115 *
1116 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
1117 *
1118 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
1119 * This parameter can be one of the following values:
1120 * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for
1121 * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and
1122 * OB_PCROP_Sector5 for STM32F401xx/411xE devices.
1123 * @arg OB_PCROP_Sector_All
1124 * @param Newstate: new state of the Write Protection.
1125 * This parameter can be: ENABLE or DISABLE.
1126 * @retval None
1127 */
FLASH_OB_PCROPConfig(uint32_t OB_PCROP,FunctionalState NewState)1128 void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState)
1129 {
1130 FLASH_Status status = FLASH_COMPLETE;
1131
1132 /* Check the parameters */
1133 assert_param(IS_OB_PCROP(OB_PCROP));
1134 assert_param(IS_FUNCTIONAL_STATE(NewState));
1135
1136 status = FLASH_WaitForLastOperation();
1137
1138 if(status == FLASH_COMPLETE)
1139 {
1140 if(NewState != DISABLE)
1141 {
1142 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
1143 }
1144 else
1145 {
1146 *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP);
1147 }
1148 }
1149 }
1150
1151 /**
1152 * @brief Enables or disables the read/write protection (PCROP) of the desired
1153 * sectors
1154 *
1155 * @note This function can be used only for STM32F42xxx/43xxx devices.
1156 *
1157 * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
1158 * This parameter can be one of the following values:
1159 * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23
1160 * @arg OB_PCROP_Sector_All
1161 * @param Newstate: new state of the Write Protection.
1162 * This parameter can be: ENABLE or DISABLE.
1163 * @retval None
1164 */
FLASH_OB_PCROP1Config(uint32_t OB_PCROP,FunctionalState NewState)1165 void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState)
1166 {
1167 FLASH_Status status = FLASH_COMPLETE;
1168
1169 /* Check the parameters */
1170 assert_param(IS_OB_PCROP(OB_PCROP));
1171 assert_param(IS_FUNCTIONAL_STATE(NewState));
1172
1173 status = FLASH_WaitForLastOperation();
1174
1175 if(status == FLASH_COMPLETE)
1176 {
1177 if(NewState != DISABLE)
1178 {
1179 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP;
1180 }
1181 else
1182 {
1183 *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP);
1184 }
1185 }
1186 }
1187
1188
1189 /**
1190 * @brief Sets the read protection level.
1191 * @param OB_RDP: specifies the read protection level.
1192 * This parameter can be one of the following values:
1193 * @arg OB_RDP_Level_0: No protection
1194 * @arg OB_RDP_Level_1: Read protection of the memory
1195 * @arg OB_RDP_Level_2: Full chip protection
1196 *
1197 * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
1198 *
1199 * @retval None
1200 */
FLASH_OB_RDPConfig(uint8_t OB_RDP)1201 void FLASH_OB_RDPConfig(uint8_t OB_RDP)
1202 {
1203 FLASH_Status status = FLASH_COMPLETE;
1204
1205 /* Check the parameters */
1206 assert_param(IS_OB_RDP(OB_RDP));
1207
1208 status = FLASH_WaitForLastOperation();
1209
1210 if(status == FLASH_COMPLETE)
1211 {
1212 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
1213
1214 }
1215 }
1216
1217 /**
1218 * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
1219 * @param OB_IWDG: Selects the IWDG mode
1220 * This parameter can be one of the following values:
1221 * @arg OB_IWDG_SW: Software IWDG selected
1222 * @arg OB_IWDG_HW: Hardware IWDG selected
1223 * @param OB_STOP: Reset event when entering STOP mode.
1224 * This parameter can be one of the following values:
1225 * @arg OB_STOP_NoRST: No reset generated when entering in STOP
1226 * @arg OB_STOP_RST: Reset generated when entering in STOP
1227 * @param OB_STDBY: Reset event when entering Standby mode.
1228 * This parameter can be one of the following values:
1229 * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
1230 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
1231 * @retval None
1232 */
FLASH_OB_UserConfig(uint8_t OB_IWDG,uint8_t OB_STOP,uint8_t OB_STDBY)1233 void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
1234 {
1235 uint8_t optiontmp = 0xFF;
1236 FLASH_Status status = FLASH_COMPLETE;
1237
1238 /* Check the parameters */
1239 assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
1240 assert_param(IS_OB_STOP_SOURCE(OB_STOP));
1241 assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
1242
1243 /* Wait for last operation to be completed */
1244 status = FLASH_WaitForLastOperation();
1245
1246 if(status == FLASH_COMPLETE)
1247 {
1248 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
1249 /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
1250 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
1251 #endif /* STM32F427_437xx || STM32F429_439xx */
1252
1253 #if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx)
1254 /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
1255 optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
1256 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE || STM32F446xx */
1257
1258 /* Update User Option Byte */
1259 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
1260 }
1261 }
1262
1263 /**
1264 * @brief Configure the Dual Bank Boot.
1265 *
1266 * @note This function can be used only for STM32F42xxx/43xxx devices.
1267 *
1268 * @param OB_BOOT: specifies the Dual Bank Boot Option byte.
1269 * This parameter can be one of the following values:
1270 * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
1271 * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
1272 * @retval None
1273 */
FLASH_OB_BootConfig(uint8_t OB_BOOT)1274 void FLASH_OB_BootConfig(uint8_t OB_BOOT)
1275 {
1276 /* Check the parameters */
1277 assert_param(IS_OB_BOOT(OB_BOOT));
1278
1279 /* Set Dual Bank Boot */
1280 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
1281 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT;
1282
1283 }
1284
1285 /**
1286 * @brief Sets the BOR Level.
1287 * @param OB_BOR: specifies the Option Bytes BOR Reset Level.
1288 * This parameter can be one of the following values:
1289 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
1290 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
1291 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
1292 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
1293 * @retval None
1294 */
FLASH_OB_BORConfig(uint8_t OB_BOR)1295 void FLASH_OB_BORConfig(uint8_t OB_BOR)
1296 {
1297 /* Check the parameters */
1298 assert_param(IS_OB_BOR(OB_BOR));
1299
1300 /* Set the BOR Level */
1301 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
1302 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
1303
1304 }
1305
1306 /**
1307 * @brief Launch the option byte loading.
1308 * @param None
1309 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
1310 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
1311 */
FLASH_OB_Launch(void)1312 FLASH_Status FLASH_OB_Launch(void)
1313 {
1314 FLASH_Status status = FLASH_COMPLETE;
1315
1316 /* Set the OPTSTRT bit in OPTCR register */
1317 *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
1318
1319 /* Wait for last operation to be completed */
1320 status = FLASH_WaitForLastOperation();
1321
1322 return status;
1323 }
1324
1325 /**
1326 * @brief Returns the FLASH User Option Bytes values.
1327 * @param None
1328 * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
1329 * and RST_STDBY(Bit2).
1330 */
FLASH_OB_GetUser(void)1331 uint8_t FLASH_OB_GetUser(void)
1332 {
1333 /* Return the User Option Byte */
1334 return (uint8_t)(FLASH->OPTCR >> 5);
1335 }
1336
1337 /**
1338 * @brief Returns the FLASH Write Protection Option Bytes value.
1339 * @param None
1340 * @retval The FLASH Write Protection Option Bytes value
1341 */
FLASH_OB_GetWRP(void)1342 uint16_t FLASH_OB_GetWRP(void)
1343 {
1344 /* Return the FLASH write protection Register value */
1345 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
1346 }
1347
1348 /**
1349 * @brief Returns the FLASH Write Protection Option Bytes value.
1350 *
1351 * @note This function can be used only for STM32F42xxx/43xxx devices.
1352 *
1353 * @param None
1354 * @retval The FLASH Write Protection Option Bytes value
1355 */
FLASH_OB_GetWRP1(void)1356 uint16_t FLASH_OB_GetWRP1(void)
1357 {
1358 /* Return the FLASH write protection Register value */
1359 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
1360 }
1361
1362 /**
1363 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
1364 *
1365 * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices.
1366 *
1367 * @param None
1368 * @retval The FLASH PC Read/Write Protection Option Bytes value
1369 */
FLASH_OB_GetPCROP(void)1370 uint16_t FLASH_OB_GetPCROP(void)
1371 {
1372 /* Return the FLASH PC Read/write protection Register value */
1373 return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
1374 }
1375
1376 /**
1377 * @brief Returns the FLASH PC Read/Write Protection Option Bytes value.
1378 *
1379 * @note This function can be used only for STM32F42xxx/43xxx devices.
1380 *
1381 * @param None
1382 * @retval The FLASH PC Read/Write Protection Option Bytes value
1383 */
FLASH_OB_GetPCROP1(void)1384 uint16_t FLASH_OB_GetPCROP1(void)
1385 {
1386 /* Return the FLASH write protection Register value */
1387 return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
1388 }
1389
1390 /**
1391 * @brief Returns the FLASH Read Protection level.
1392 * @param None
1393 * @retval FLASH ReadOut Protection Status:
1394 * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
1395 * - RESET, when OB_RDP_Level_0 is set
1396 */
FLASH_OB_GetRDP(void)1397 FlagStatus FLASH_OB_GetRDP(void)
1398 {
1399 FlagStatus readstatus = RESET;
1400
1401 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
1402 {
1403 readstatus = SET;
1404 }
1405 else
1406 {
1407 readstatus = RESET;
1408 }
1409 return readstatus;
1410 }
1411
1412 /**
1413 * @brief Returns the FLASH BOR level.
1414 * @param None
1415 * @retval The FLASH BOR level:
1416 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
1417 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
1418 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
1419 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
1420 */
FLASH_OB_GetBOR(void)1421 uint8_t FLASH_OB_GetBOR(void)
1422 {
1423 /* Return the FLASH BOR level */
1424 return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
1425 }
1426
1427 /**
1428 * @}
1429 */
1430
1431 /** @defgroup FLASH_Group4 Interrupts and flags management functions
1432 * @brief Interrupts and flags management functions
1433 *
1434 @verbatim
1435 ===============================================================================
1436 ##### Interrupts and flags management functions #####
1437 ===============================================================================
1438 @endverbatim
1439 * @{
1440 */
1441
1442 /**
1443 * @brief Enables or disables the specified FLASH interrupts.
1444 * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
1445 * This parameter can be any combination of the following values:
1446 * @arg FLASH_IT_ERR: FLASH Error Interrupt
1447 * @arg FLASH_IT_EOP: FLASH end of operation Interrupt
1448 * @retval None
1449 */
FLASH_ITConfig(uint32_t FLASH_IT,FunctionalState NewState)1450 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
1451 {
1452 /* Check the parameters */
1453 assert_param(IS_FLASH_IT(FLASH_IT));
1454 assert_param(IS_FUNCTIONAL_STATE(NewState));
1455
1456 if(NewState != DISABLE)
1457 {
1458 /* Enable the interrupt sources */
1459 FLASH->CR |= FLASH_IT;
1460 }
1461 else
1462 {
1463 /* Disable the interrupt sources */
1464 FLASH->CR &= ~(uint32_t)FLASH_IT;
1465 }
1466 }
1467
1468 /**
1469 * @brief Checks whether the specified FLASH flag is set or not.
1470 * @param FLASH_FLAG: specifies the FLASH flag to check.
1471 * This parameter can be one of the following values:
1472 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
1473 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
1474 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
1475 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
1476 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
1477 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
1478 * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
1479 * @arg FLASH_FLAG_BSY: FLASH Busy flag
1480 * @retval The new state of FLASH_FLAG (SET or RESET).
1481 */
FLASH_GetFlagStatus(uint32_t FLASH_FLAG)1482 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
1483 {
1484 FlagStatus bitstatus = RESET;
1485 /* Check the parameters */
1486 assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
1487
1488 if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
1489 {
1490 bitstatus = SET;
1491 }
1492 else
1493 {
1494 bitstatus = RESET;
1495 }
1496 /* Return the new state of FLASH_FLAG (SET or RESET) */
1497 return bitstatus;
1498 }
1499
1500 /**
1501 * @brief Clears the FLASH's pending flags.
1502 * @param FLASH_FLAG: specifies the FLASH flags to clear.
1503 * This parameter can be any combination of the following values:
1504 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
1505 * @arg FLASH_FLAG_OPERR: FLASH operation Error flag
1506 * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
1507 * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
1508 * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
1509 * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
1510 * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices)
1511 * @retval None
1512 */
FLASH_ClearFlag(uint32_t FLASH_FLAG)1513 void FLASH_ClearFlag(uint32_t FLASH_FLAG)
1514 {
1515 /* Check the parameters */
1516 assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
1517
1518 /* Clear the flags */
1519 FLASH->SR = FLASH_FLAG;
1520 }
1521
1522 /**
1523 * @brief Returns the FLASH Status.
1524 * @param None
1525 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
1526 * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
1527 */
FLASH_GetStatus(void)1528 FLASH_Status FLASH_GetStatus(void)
1529 {
1530 FLASH_Status flashstatus = FLASH_COMPLETE;
1531
1532 if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
1533 {
1534 flashstatus = FLASH_BUSY;
1535 }
1536 else
1537 {
1538 if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
1539 {
1540 flashstatus = FLASH_ERROR_WRP;
1541 }
1542 else
1543 {
1544 if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00)
1545 {
1546 flashstatus = FLASH_ERROR_RD;
1547 }
1548 else
1549 {
1550 if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
1551 {
1552 flashstatus = FLASH_ERROR_PROGRAM;
1553 }
1554 else
1555 {
1556 if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
1557 {
1558 flashstatus = FLASH_ERROR_OPERATION;
1559 }
1560 else
1561 {
1562 flashstatus = FLASH_COMPLETE;
1563 }
1564 }
1565 }
1566 }
1567 }
1568 /* Return the FLASH Status */
1569 return flashstatus;
1570 }
1571
1572 /**
1573 * @brief Waits for a FLASH operation to complete.
1574 * @param None
1575 * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
1576 * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
1577 */
FLASH_WaitForLastOperation(void)1578 FLASH_Status FLASH_WaitForLastOperation(void)
1579 {
1580 __IO FLASH_Status status = FLASH_COMPLETE;
1581
1582 /* Check for the FLASH Status */
1583 status = FLASH_GetStatus();
1584
1585 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
1586 Even if the FLASH operation fails, the BUSY flag will be reset and an error
1587 flag will be set */
1588 while(status == FLASH_BUSY)
1589 {
1590 status = FLASH_GetStatus();
1591 }
1592 /* Return the operation status */
1593 return status;
1594 }
1595
1596 /**
1597 * @}
1598 */
1599
1600 /**
1601 * @}
1602 */
1603
1604 /**
1605 * @}
1606 */
1607
1608 /**
1609 * @}
1610 */
1611
1612 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1613