1 /**
2 ******************************************************************************
3 * @file stm32f4xx_pwr.c
4 * @author MCD Application Team
5 * @version V1.5.1
6 * @date 22-May-2015
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Power Controller (PWR) peripheral:
9 * + Backup Domain Access
10 * + PVD configuration
11 * + WakeUp pin configuration
12 * + Main and Backup Regulators configuration
13 * + FLASH Power Down configuration
14 * + Low Power modes configuration
15 * + Flags management
16 *
17 ******************************************************************************
18 * @attention
19 *
20 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
21 *
22 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
23 * You may not use this file except in compliance with the License.
24 * You may obtain a copy of the License at:
25 *
26 * http://www.st.com/software_license_agreement_liberty_v2
27 *
28 * Unless required by applicable law or agreed to in writing, software
29 * distributed under the License is distributed on an "AS IS" BASIS,
30 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31 * See the License for the specific language governing permissions and
32 * limitations under the License.
33 *
34 ******************************************************************************
35 */
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_pwr.h"
39 #include "stm32f4xx_rcc.h"
40
41 /** @addtogroup STM32F4xx_StdPeriph_Driver
42 * @{
43 */
44
45 /** @defgroup PWR
46 * @brief PWR driver modules
47 * @{
48 */
49
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private define ------------------------------------------------------------*/
52 /* --------- PWR registers bit address in the alias region ---------- */
53 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
54
55 /* --- CR Register ---*/
56
57 /* Alias word address of DBP bit */
58 #define CR_OFFSET (PWR_OFFSET + 0x00)
59 #define DBP_BitNumber 0x08
60 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
61
62 /* Alias word address of PVDE bit */
63 #define PVDE_BitNumber 0x04
64 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
65
66 /* Alias word address of FPDS bit */
67 #define FPDS_BitNumber 0x09
68 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
69
70 /* Alias word address of PMODE bit */
71 #define PMODE_BitNumber 0x0E
72 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
73
74 /* Alias word address of ODEN bit */
75 #define ODEN_BitNumber 0x10
76 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
77
78 /* Alias word address of ODSWEN bit */
79 #define ODSWEN_BitNumber 0x11
80 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
81
82 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
83 /* Alias word address of MRUDS bit */
84 #define MRUDS_BitNumber 0x0B
85 #define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4))
86
87 /* Alias word address of LPUDS bit */
88 #define LPUDS_BitNumber 0x0A
89 #define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4))
90 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
91
92 #if defined(STM32F401xx) || defined(STM32F411xE)
93 /* Alias word address of MRLVDS bit */
94 #define MRLVDS_BitNumber 0x0B
95 #define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
96
97 /* Alias word address of LPLVDS bit */
98 #define LPLVDS_BitNumber 0x0A
99 #define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
100 #endif /* STM32F401xx || STM32F411xE */
101
102 /* --- CSR Register ---*/
103 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
104 /* Alias word address of EWUP bit */
105 #define CSR_OFFSET (PWR_OFFSET + 0x04)
106 #define EWUP_BitNumber 0x08
107 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
108 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
109
110 #if defined(STM32F446xx)
111 /* Alias word address of EWUP2 bit */
112 #define CSR_OFFSET (PWR_OFFSET + 0x04)
113 #define EWUP1_BitNumber 0x08
114 #define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
115 #define EWUP2_BitNumber 0x07
116 #define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
117 #endif /* STM32F446xx */
118
119 /* Alias word address of BRE bit */
120 #define BRE_BitNumber 0x09
121 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
122
123 /* ------------------ PWR registers bit mask ------------------------ */
124
125 /* CR register bit mask */
126 #define CR_DS_MASK ((uint32_t)0xFFFFF3FC)
127 #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
128 #define CR_VOS_MASK ((uint32_t)0xFFFF3FFF)
129
130 /* Private macro -------------------------------------------------------------*/
131 /* Private variables ---------------------------------------------------------*/
132 /* Private function prototypes -----------------------------------------------*/
133 /* Private functions ---------------------------------------------------------*/
134
135 /** @defgroup PWR_Private_Functions
136 * @{
137 */
138
139 /** @defgroup PWR_Group1 Backup Domain Access function
140 * @brief Backup Domain Access function
141 *
142 @verbatim
143 ===============================================================================
144 ##### Backup Domain Access function #####
145 ===============================================================================
146 [..]
147 After reset, the backup domain (RTC registers, RTC backup data
148 registers and backup SRAM) is protected against possible unwanted
149 write accesses.
150 To enable access to the RTC Domain and RTC registers, proceed as follows:
151 (+) Enable the Power Controller (PWR) APB1 interface clock using the
152 RCC_APB1PeriphClockCmd() function.
153 (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function.
154
155 @endverbatim
156 * @{
157 */
158
159 /**
160 * @brief Deinitializes the PWR peripheral registers to their default reset values.
161 * @param None
162 * @retval None
163 */
PWR_DeInit(void)164 void PWR_DeInit(void)
165 {
166 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
167 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
168 }
169
170 /**
171 * @brief Enables or disables access to the backup domain (RTC registers, RTC
172 * backup data registers and backup SRAM).
173 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
174 * Backup Domain Access should be kept enabled.
175 * @param NewState: new state of the access to the backup domain.
176 * This parameter can be: ENABLE or DISABLE.
177 * @retval None
178 */
PWR_BackupAccessCmd(FunctionalState NewState)179 void PWR_BackupAccessCmd(FunctionalState NewState)
180 {
181 /* Check the parameters */
182 assert_param(IS_FUNCTIONAL_STATE(NewState));
183
184 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
185 }
186
187 /**
188 * @}
189 */
190
191 /** @defgroup PWR_Group2 PVD configuration functions
192 * @brief PVD configuration functions
193 *
194 @verbatim
195 ===============================================================================
196 ##### PVD configuration functions #####
197 ===============================================================================
198 [..]
199 (+) The PVD is used to monitor the VDD power supply by comparing it to a
200 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
201 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
202 than the PVD threshold. This event is internally connected to the EXTI
203 line16 and can generate an interrupt if enabled through the EXTI registers.
204 (+) The PVD is stopped in Standby mode.
205
206 @endverbatim
207 * @{
208 */
209
210 /**
211 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
212 * @param PWR_PVDLevel: specifies the PVD detection level
213 * This parameter can be one of the following values:
214 * @arg PWR_PVDLevel_0
215 * @arg PWR_PVDLevel_1
216 * @arg PWR_PVDLevel_2
217 * @arg PWR_PVDLevel_3
218 * @arg PWR_PVDLevel_4
219 * @arg PWR_PVDLevel_5
220 * @arg PWR_PVDLevel_6
221 * @arg PWR_PVDLevel_7
222 * @note Refer to the electrical characteristics of your device datasheet for
223 * more details about the voltage threshold corresponding to each
224 * detection level.
225 * @retval None
226 */
PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)227 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
228 {
229 uint32_t tmpreg = 0;
230
231 /* Check the parameters */
232 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
233
234 tmpreg = PWR->CR;
235
236 /* Clear PLS[7:5] bits */
237 tmpreg &= CR_PLS_MASK;
238
239 /* Set PLS[7:5] bits according to PWR_PVDLevel value */
240 tmpreg |= PWR_PVDLevel;
241
242 /* Store the new value */
243 PWR->CR = tmpreg;
244 }
245
246 /**
247 * @brief Enables or disables the Power Voltage Detector(PVD).
248 * @param NewState: new state of the PVD.
249 * This parameter can be: ENABLE or DISABLE.
250 * @retval None
251 */
PWR_PVDCmd(FunctionalState NewState)252 void PWR_PVDCmd(FunctionalState NewState)
253 {
254 /* Check the parameters */
255 assert_param(IS_FUNCTIONAL_STATE(NewState));
256
257 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
258 }
259
260 /**
261 * @}
262 */
263
264 /** @defgroup PWR_Group3 WakeUp pin configuration functions
265 * @brief WakeUp pin configuration functions
266 *
267 @verbatim
268 ===============================================================================
269 ##### WakeUp pin configuration functions #####
270 ===============================================================================
271 [..]
272 (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
273 forced in input pull down configuration and is active on rising edges.
274 (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
275
276 @endverbatim
277 * @{
278 */
279 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
280 /**
281 * @brief Enables or disables the WakeUp Pin functionality.
282 * @param NewState: new state of the WakeUp Pin functionality.
283 * This parameter can be: ENABLE or DISABLE.
284 * @retval None
285 */
PWR_WakeUpPinCmd(FunctionalState NewState)286 void PWR_WakeUpPinCmd(FunctionalState NewState)
287 {
288 /* Check the parameters */
289 assert_param(IS_FUNCTIONAL_STATE(NewState));
290
291 *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
292 }
293 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
294
295 #if defined(STM32F446xx)
296 /**
297 * @brief Enables or disables the WakeUp Pin functionality.
298 * @param PWR_WakeUpPinx: specifies the WakeUp Pin.
299 * This parameter can be one of the following values:
300 * @arg PWR_WakeUp_Pin1: WKUP1 pin is used for wakeup from Standby mode.
301 * @arg PWR_WakeUp_Pin2: WKUP2 pin is used for wakeup from Standby mode.
302 * @param NewState: new state of the WakeUp Pin functionality.
303 * This parameter can be: ENABLE or DISABLE.
304 * @retval None
305 */
PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx,FunctionalState NewState)306 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState)
307 {
308 /* Check the parameters */
309 assert_param(IS_FUNCTIONAL_STATE(NewState));
310 assert_param(IS_PWR_WAKEUP_PIN(NewState));
311 if(PWR_WakeUpPinx == PWR_WakeUp_Pin1)
312 {
313 *(__IO uint32_t *) CSR_EWUP1_BB = (uint32_t)NewState;
314 }
315 else /* PWR_WakeUp_Pin1 */
316 {
317 *(__IO uint32_t *) CSR_EWUP2_BB = (uint32_t)NewState;
318 }
319 }
320 #endif /* STM32F446xx */
321
322 /**
323 * @}
324 */
325
326 /** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
327 * @brief Main and Backup Regulators configuration functions
328 *
329 @verbatim
330 ===============================================================================
331 ##### Main and Backup Regulators configuration functions #####
332 ===============================================================================
333 [..]
334 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
335 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
336 retained even in Standby or VBAT mode when the low power backup regulator
337 is enabled. It can be considered as an internal EEPROM when VBAT is
338 always present. You can use the PWR_BackupRegulatorCmd() function to
339 enable the low power backup regulator and use the PWR_GetFlagStatus
340 (PWR_FLAG_BRR) to check if it is ready or not.
341
342 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
343 the backup SRAM is powered from VDD which replaces the VBAT power supply to
344 save battery life.
345
346 (+) The backup SRAM is not mass erased by an tamper event. It is read
347 protected to prevent confidential data, such as cryptographic private
348 key, from being accessed. The backup SRAM can be erased only through
349 the Flash interface when a protection level change from level 1 to
350 level 0 is requested.
351 -@- Refer to the description of Read protection (RDP) in the reference manual.
352
353 (+) The main internal regulator can be configured to have a tradeoff between
354 performance and power consumption when the device does not operate at
355 the maximum frequency.
356 (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be
357 configured on the fly through PWR_MainRegulatorModeConfig() function which
358 configure VOS bit in PWR_CR register:
359 (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
360 the System frequency can go up to 168 MHz.
361 (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
362 the System frequency can go up to 144 MHz.
363
364 (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through
365 PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in
366 PWR_CR register:
367 which configure VOS[1:0] bits in PWR_CR register:
368 (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected)
369 the System frequency can go up to 168 MHz.
370 (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected)
371 the System frequency can go up to 144 MHz.
372 (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected)
373 the System frequency can go up to 120 MHz.
374
375 (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
376 is OFF and the HSI or HSE clock source is selected as system clock.
377 The new value programmed is active only when the PLL is ON.
378 When the PLL is OFF, the voltage scale 3 is automatically selected.
379 Refer to the datasheets for more details.
380
381 (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
382 2 operating modes available:
383 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
384 voltage scaling (scale 1, scale 2 or scale 3)
385 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
386 higher frequency than the normal mode for a given voltage scaling (scale 1,
387 scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and
388 PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow
389 the sequence described in Reference manual.
390
391 (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
392 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
393 and internal SRAM. 2 operating modes are available:
394 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
395 available when the main regulator or the low power regulator is used in Scale 3 or
396 low voltage mode.
397 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
398 available when the main regulator or the low power regulator is in low voltage mode.
399 This mode is enabled through PWR_UnderDriveCmd() function.
400
401 @endverbatim
402 * @{
403 */
404
405 /**
406 * @brief Enables or disables the Backup Regulator.
407 * @param NewState: new state of the Backup Regulator.
408 * This parameter can be: ENABLE or DISABLE.
409 * @retval None
410 */
PWR_BackupRegulatorCmd(FunctionalState NewState)411 void PWR_BackupRegulatorCmd(FunctionalState NewState)
412 {
413 /* Check the parameters */
414 assert_param(IS_FUNCTIONAL_STATE(NewState));
415
416 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
417 }
418
419 /**
420 * @brief Configures the main internal regulator output voltage.
421 * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
422 * a tradeoff between performance and power consumption when the device does
423 * not operate at the maximum frequency (refer to the datasheets for more details).
424 * This parameter can be one of the following values:
425 * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
426 * System frequency up to 168 MHz.
427 * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
428 * System frequency up to 144 MHz.
429 * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode,
430 * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices)
431 * @retval None
432 */
PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)433 void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
434 {
435 uint32_t tmpreg = 0;
436
437 /* Check the parameters */
438 assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
439
440 tmpreg = PWR->CR;
441
442 /* Clear VOS[15:14] bits */
443 tmpreg &= CR_VOS_MASK;
444
445 /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */
446 tmpreg |= PWR_Regulator_Voltage;
447
448 /* Store the new value */
449 PWR->CR = tmpreg;
450 }
451
452 /**
453 * @brief Enables or disables the Over-Drive.
454 *
455 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
456 * This mode allows the CPU and the core logic to operate at a higher frequency
457 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
458 *
459 * @note It is recommended to enter or exit Over-drive mode when the application is not running
460 * critical tasks and when the system clock source is either HSI or HSE.
461 * During the Over-drive switch activation, no peripheral clocks should be enabled.
462 * The peripheral clocks must be enabled once the Over-drive mode is activated.
463 *
464 * @param NewState: new state of the Over Drive mode.
465 * This parameter can be: ENABLE or DISABLE.
466 * @retval None
467 */
PWR_OverDriveCmd(FunctionalState NewState)468 void PWR_OverDriveCmd(FunctionalState NewState)
469 {
470 /* Check the parameters */
471 assert_param(IS_FUNCTIONAL_STATE(NewState));
472
473 /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */
474 *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState;
475 }
476
477 /**
478 * @brief Enables or disables the Over-Drive switching.
479 *
480 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
481 *
482 * @param NewState: new state of the Over Drive switching mode.
483 * This parameter can be: ENABLE or DISABLE.
484 * @retval None
485 */
PWR_OverDriveSWCmd(FunctionalState NewState)486 void PWR_OverDriveSWCmd(FunctionalState NewState)
487 {
488 /* Check the parameters */
489 assert_param(IS_FUNCTIONAL_STATE(NewState));
490
491 /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */
492 *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState;
493 }
494
495 /**
496 * @brief Enables or disables the Under-Drive mode.
497 *
498 * @note This function can be used only for STM32F42xxx/STM3243xxx devices.
499 * @note This mode is enabled only with STOP low power mode.
500 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
501 * mode is only available when the main regulator or the low power regulator
502 * is in low voltage mode
503 *
504 * @note If the Under-drive mode was enabled, it is automatically disabled after
505 * exiting Stop mode.
506 * When the voltage regulator operates in Under-drive mode, an additional
507 * startup delay is induced when waking up from Stop mode.
508 *
509 * @param NewState: new state of the Under Drive mode.
510 * This parameter can be: ENABLE or DISABLE.
511 * @retval None
512 */
PWR_UnderDriveCmd(FunctionalState NewState)513 void PWR_UnderDriveCmd(FunctionalState NewState)
514 {
515 /* Check the parameters */
516 assert_param(IS_FUNCTIONAL_STATE(NewState));
517
518 if (NewState != DISABLE)
519 {
520 /* Set the UDEN[1:0] bits to enable the Under Drive mode */
521 PWR->CR |= (uint32_t)PWR_CR_UDEN;
522 }
523 else
524 {
525 /* Reset the UDEN[1:0] bits to disable the Under Drive mode */
526 PWR->CR &= (uint32_t)(~PWR_CR_UDEN);
527 }
528 }
529
530 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
531 /**
532 * @brief Enables or disables the Main Regulator under drive mode.
533 *
534 * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
535 *
536 * @param NewState: new state of the Main Regulator Under Drive mode.
537 * This parameter can be: ENABLE or DISABLE.
538 * @retval None
539 */
PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState)540 void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState)
541 {
542 /* Check the parameters */
543 assert_param(IS_FUNCTIONAL_STATE(NewState));
544
545 if (NewState != DISABLE)
546 {
547 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE;
548 }
549 else
550 {
551 *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)DISABLE;
552 }
553 }
554
555 /**
556 * @brief Enables or disables the Low Power Regulator under drive mode.
557 *
558 * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
559 *
560 * @param NewState: new state of the Low Power Regulator Under Drive mode.
561 * This parameter can be: ENABLE or DISABLE.
562 * @retval None
563 */
PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState)564 void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState)
565 {
566 /* Check the parameters */
567 assert_param(IS_FUNCTIONAL_STATE(NewState));
568
569 if (NewState != DISABLE)
570 {
571 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE;
572 }
573 else
574 {
575 *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)DISABLE;
576 }
577 }
578 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
579
580 #if defined(STM32F401xx) || defined(STM32F411xE)
581 /**
582 * @brief Enables or disables the Main Regulator low voltage mode.
583 *
584 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
585 *
586 * @param NewState: new state of the Main Regulator Low Voltage mode.
587 * This parameter can be: ENABLE or DISABLE.
588 * @retval None
589 */
PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)590 void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
591 {
592 /* Check the parameters */
593 assert_param(IS_FUNCTIONAL_STATE(NewState));
594
595 if (NewState != DISABLE)
596 {
597 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
598 }
599 else
600 {
601 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
602 }
603 }
604
605 /**
606 * @brief Enables or disables the Low Power Regulator low voltage mode.
607 *
608 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
609 *
610 * @param NewState: new state of the Low Power Regulator Low Voltage mode.
611 * This parameter can be: ENABLE or DISABLE.
612 * @retval None
613 */
PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)614 void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
615 {
616 /* Check the parameters */
617 assert_param(IS_FUNCTIONAL_STATE(NewState));
618
619 if (NewState != DISABLE)
620 {
621 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
622 }
623 else
624 {
625 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
626 }
627 }
628 #endif /* STM32F401xx || STM32F411xE */
629
630 /**
631 * @}
632 */
633
634 /** @defgroup PWR_Group5 FLASH Power Down configuration functions
635 * @brief FLASH Power Down configuration functions
636 *
637 @verbatim
638 ===============================================================================
639 ##### FLASH Power Down configuration functions #####
640 ===============================================================================
641 [..]
642 (+) By setting the FPDS bit in the PWR_CR register by using the
643 PWR_FlashPowerDownCmd() function, the Flash memory also enters power
644 down mode when the device enters Stop mode. When the Flash memory
645 is in power down mode, an additional startup delay is incurred when
646 waking up from Stop mode.
647 @endverbatim
648 * @{
649 */
650
651 /**
652 * @brief Enables or disables the Flash Power Down in STOP mode.
653 * @param NewState: new state of the Flash power mode.
654 * This parameter can be: ENABLE or DISABLE.
655 * @retval None
656 */
PWR_FlashPowerDownCmd(FunctionalState NewState)657 void PWR_FlashPowerDownCmd(FunctionalState NewState)
658 {
659 /* Check the parameters */
660 assert_param(IS_FUNCTIONAL_STATE(NewState));
661
662 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
663 }
664
665 /**
666 * @}
667 */
668
669 /** @defgroup PWR_Group6 Low Power modes configuration functions
670 * @brief Low Power modes configuration functions
671 *
672 @verbatim
673 ===============================================================================
674 ##### Low Power modes configuration functions #####
675 ===============================================================================
676 [..]
677 The devices feature 3 low-power modes:
678 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
679 (+) Stop mode: all clocks are stopped, regulator running, regulator
680 in low power mode
681 (+) Standby mode: 1.2V domain powered off.
682
683 *** Sleep mode ***
684 ==================
685 [..]
686 (+) Entry:
687 (++) The Sleep mode is entered by using the __WFI() or __WFE() functions.
688 (+) Exit:
689 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
690 controller (NVIC) can wake up the device from Sleep mode.
691
692 *** Stop mode ***
693 =================
694 [..]
695 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
696 and the HSE RC oscillators are disabled. Internal SRAM and register contents
697 are preserved.
698 The voltage regulator can be configured either in normal or low-power mode.
699 To minimize the consumption In Stop mode, FLASH can be powered off before
700 entering the Stop mode. It can be switched on again by software after exiting
701 the Stop mode using the PWR_FlashPowerDownCmd() function.
702
703 (+) Entry:
704 (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON)
705 function with:
706 (+++) Main regulator ON.
707 (+++) Low Power regulator ON.
708 (+) Exit:
709 (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
710
711 *** Standby mode ***
712 ====================
713 [..]
714 The Standby mode allows to achieve the lowest power consumption. It is based
715 on the Cortex-M4 deepsleep mode, with the voltage regulator disabled.
716 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
717 the HSE oscillator are also switched off. SRAM and register contents are lost
718 except for the RTC registers, RTC backup registers, backup SRAM and Standby
719 circuitry.
720
721 The voltage regulator is OFF.
722
723 (+) Entry:
724 (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
725 (+) Exit:
726 (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
727 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
728
729 *** Auto-wakeup (AWU) from low-power mode ***
730 =============================================
731 [..]
732 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
733 Wakeup event, a tamper event, a time-stamp event, or a comparator event,
734 without depending on an external interrupt (Auto-wakeup mode).
735
736 (#) RTC auto-wakeup (AWU) from the Stop mode
737
738 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
739 (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
740 or Event modes) using the EXTI_Init() function.
741 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
742 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
743 and RTC_AlarmCmd() functions.
744 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
745 is necessary to:
746 (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt
747 or Event modes) using the EXTI_Init() function.
748 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
749 function
750 (+++) Configure the RTC to detect the tamper or time stamp event using the
751 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
752 functions.
753 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
754 (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt
755 or Event modes) using the EXTI_Init() function.
756 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
757 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
758 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
759
760 (#) RTC auto-wakeup (AWU) from the Standby mode
761
762 (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
763 (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
764 (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
765 and RTC_AlarmCmd() functions.
766 (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
767 is necessary to:
768 (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
769 function
770 (+++) Configure the RTC to detect the tamper or time stamp event using the
771 RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
772 functions.
773 (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
774 (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
775 (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
776 RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
777
778 @endverbatim
779 * @{
780 */
781
782 /**
783 * @brief Enters STOP mode.
784 *
785 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
786 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
787 * the HSI RC oscillator is selected as system clock.
788 * @note When the voltage regulator operates in low power mode, an additional
789 * startup delay is incurred when waking up from Stop mode.
790 * By keeping the internal regulator ON during Stop mode, the consumption
791 * is higher although the startup time is reduced.
792 *
793 * @param PWR_Regulator: specifies the regulator state in STOP mode.
794 * This parameter can be one of the following values:
795 * @arg PWR_MainRegulator_ON: STOP mode with regulator ON
796 * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON
797 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
798 * This parameter can be one of the following values:
799 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
800 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
801 * @retval None
802 */
PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)803 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
804 {
805 uint32_t tmpreg = 0;
806
807 /* Check the parameters */
808 assert_param(IS_PWR_REGULATOR(PWR_Regulator));
809 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
810
811 /* Select the regulator state in STOP mode ---------------------------------*/
812 tmpreg = PWR->CR;
813 /* Clear PDDS and LPDS bits */
814 tmpreg &= CR_DS_MASK;
815
816 /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */
817 tmpreg |= PWR_Regulator;
818
819 /* Store the new value */
820 PWR->CR = tmpreg;
821
822 /* Set SLEEPDEEP bit of Cortex System Control Register */
823 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
824
825 /* Select STOP mode entry --------------------------------------------------*/
826 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
827 {
828 /* Request Wait For Interrupt */
829 __WFI();
830 }
831 else
832 {
833 /* Request Wait For Event */
834 __WFE();
835 }
836 /* Reset SLEEPDEEP bit of Cortex System Control Register */
837 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
838 }
839
840 /**
841 * @brief Enters in Under-Drive STOP mode.
842 *
843 * @note This mode is only available for STM32F42xxx/STM3243xxx devices.
844 *
845 * @note This mode can be selected only when the Under-Drive is already active
846 *
847 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
848 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
849 * the HSI RC oscillator is selected as system clock.
850 * @note When the voltage regulator operates in low power mode, an additional
851 * startup delay is incurred when waking up from Stop mode.
852 * By keeping the internal regulator ON during Stop mode, the consumption
853 * is higher although the startup time is reduced.
854 *
855 * @param PWR_Regulator: specifies the regulator state in STOP mode.
856 * This parameter can be one of the following values:
857 * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode
858 * and Flash memory in power-down when the device is in Stop under-drive mode
859 * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode
860 * and Flash memory in power-down when the device is in Stop under-drive mode
861 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
862 * This parameter can be one of the following values:
863 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
864 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
865 * @retval None
866 */
PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)867 void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
868 {
869 uint32_t tmpreg = 0;
870
871 /* Check the parameters */
872 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator));
873 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
874
875 /* Select the regulator state in STOP mode ---------------------------------*/
876 tmpreg = PWR->CR;
877 /* Clear PDDS and LPDS bits */
878 tmpreg &= CR_DS_MASK;
879
880 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
881 tmpreg |= PWR_Regulator;
882
883 /* Store the new value */
884 PWR->CR = tmpreg;
885
886 /* Set SLEEPDEEP bit of Cortex System Control Register */
887 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
888
889 /* Select STOP mode entry --------------------------------------------------*/
890 if(PWR_STOPEntry == PWR_STOPEntry_WFI)
891 {
892 /* Request Wait For Interrupt */
893 __WFI();
894 }
895 else
896 {
897 /* Request Wait For Event */
898 __WFE();
899 }
900 /* Reset SLEEPDEEP bit of Cortex System Control Register */
901 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
902 }
903
904 /**
905 * @brief Enters STANDBY mode.
906 * @note In Standby mode, all I/O pins are high impedance except for:
907 * - Reset pad (still available)
908 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
909 * Alarm out, or RTC clock calibration out.
910 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
911 * - WKUP pin 1 (PA0) if enabled.
912 * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function
913 * @param None
914 * @retval None
915 */
PWR_EnterSTANDBYMode(void)916 void PWR_EnterSTANDBYMode(void)
917 {
918 /* Select STANDBY mode */
919 PWR->CR |= PWR_CR_PDDS;
920
921 /* Set SLEEPDEEP bit of Cortex System Control Register */
922 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
923
924 /* This option is used to ensure that store operations are completed */
925 #if defined ( __CC_ARM )
926 __force_stores();
927 #endif
928 /* Request Wait For Interrupt */
929 __WFI();
930 }
931
932 /**
933 * @}
934 */
935
936 /** @defgroup PWR_Group7 Flags management functions
937 * @brief Flags management functions
938 *
939 @verbatim
940 ===============================================================================
941 ##### Flags management functions #####
942 ===============================================================================
943
944 @endverbatim
945 * @{
946 */
947
948 /**
949 * @brief Checks whether the specified PWR flag is set or not.
950 * @param PWR_FLAG: specifies the flag to check.
951 * This parameter can be one of the following values:
952 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
953 * was received from the WKUP pin or from the RTC alarm (Alarm A
954 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
955 * An additional wakeup event is detected if the WKUP pin is enabled
956 * (by setting the EWUP bit) when the WKUP pin level is already high.
957 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
958 * resumed from StandBy mode.
959 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
960 * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode
961 * For this reason, this bit is equal to 0 after Standby or reset
962 * until the PVDE bit is set.
963 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
964 * when the device wakes up from Standby mode or by a system reset
965 * or power reset.
966 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
967 * scaling output selection is ready.
968 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
969 * is ready (STM32F42xxx/43xxx devices)
970 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
971 * switching is ready (STM32F42xxx/43xxx devices)
972 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
973 * is enabled in Stop mode (STM32F42xxx/43xxx devices)
974 * @retval The new state of PWR_FLAG (SET or RESET).
975 */
PWR_GetFlagStatus(uint32_t PWR_FLAG)976 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
977 {
978 FlagStatus bitstatus = RESET;
979
980 /* Check the parameters */
981 assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
982
983 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
984 {
985 bitstatus = SET;
986 }
987 else
988 {
989 bitstatus = RESET;
990 }
991 /* Return the flag status */
992 return bitstatus;
993 }
994
995 /**
996 * @brief Clears the PWR's pending flags.
997 * @param PWR_FLAG: specifies the flag to clear.
998 * This parameter can be one of the following values:
999 * @arg PWR_FLAG_WU: Wake Up flag
1000 * @arg PWR_FLAG_SB: StandBy flag
1001 * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices)
1002 * @retval None
1003 */
PWR_ClearFlag(uint32_t PWR_FLAG)1004 void PWR_ClearFlag(uint32_t PWR_FLAG)
1005 {
1006 /* Check the parameters */
1007 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
1008
1009 #if defined (STM32F427_437xx) || defined (STM32F429_439xx)
1010 if (PWR_FLAG != PWR_FLAG_UDRDY)
1011 {
1012 PWR->CR |= PWR_FLAG << 2;
1013 }
1014 else
1015 {
1016 PWR->CSR |= PWR_FLAG_UDRDY;
1017 }
1018 #endif /* STM32F427_437xx || STM32F429_439xx */
1019
1020 #if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
1021 PWR->CR |= PWR_FLAG << 2;
1022 #endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
1023 }
1024
1025 /**
1026 * @}
1027 */
1028
1029 /**
1030 * @}
1031 */
1032
1033 /**
1034 * @}
1035 */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1042