1 /**
2 ******************************************************************************
3 * @file stm32f4xx_rcc.c
4 * @author MCD Application Team
5 * @version V1.5.1
6 * @date 22-May-2015
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Reset and clock control (RCC) peripheral:
9 * + Internal/external clocks, PLL, CSS and MCO configuration
10 * + System, AHB and APB busses clocks configuration
11 * + Peripheral clocks configuration
12 * + Interrupts and flags management
13 *
14 @verbatim
15 ===============================================================================
16 ##### RCC specific features #####
17 ===============================================================================
18 [..]
19 After reset the device is running from Internal High Speed oscillator
20 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
21 and I-Cache are disabled, and all peripherals are off except internal
22 SRAM, Flash and JTAG.
23 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
24 all peripherals mapped on these busses are running at HSI speed.
25 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
26 (+) All GPIOs are in input floating state, except the JTAG pins which
27 are assigned to be used for debug purpose.
28 [..]
29 Once the device started from reset, the user application has to:
30 (+) Configure the clock source to be used to drive the System clock
31 (if the application needs higher frequency/performance)
32 (+) Configure the System clock frequency and Flash settings
33 (+) Configure the AHB and APB busses prescalers
34 (+) Enable the clock for the peripheral(s) to be used
35 (+) Configure the clock source(s) for peripherals which clocks are not
36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
37 @endverbatim
38 ******************************************************************************
39 * @attention
40 *
41 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
42 *
43 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
44 * You may not use this file except in compliance with the License.
45 * You may obtain a copy of the License at:
46 *
47 * http://www.st.com/software_license_agreement_liberty_v2
48 *
49 * Unless required by applicable law or agreed to in writing, software
50 * distributed under the License is distributed on an "AS IS" BASIS,
51 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
52 * See the License for the specific language governing permissions and
53 * limitations under the License.
54 *
55 ******************************************************************************
56 */
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f4xx_rcc.h"
60
61 /** @addtogroup STM32F4xx_StdPeriph_Driver
62 * @{
63 */
64
65 /** @defgroup RCC
66 * @brief RCC driver modules
67 * @{
68 */
69
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72 /* ------------ RCC registers bit address in the alias region ----------- */
73 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
74 /* --- CR Register ---*/
75 /* Alias word address of HSION bit */
76 #define CR_OFFSET (RCC_OFFSET + 0x00)
77 #define HSION_BitNumber 0x00
78 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
79 /* Alias word address of CSSON bit */
80 #define CSSON_BitNumber 0x13
81 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
82 /* Alias word address of PLLON bit */
83 #define PLLON_BitNumber 0x18
84 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
85 /* Alias word address of PLLI2SON bit */
86 #define PLLI2SON_BitNumber 0x1A
87 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
88
89 /* Alias word address of PLLSAION bit */
90 #define PLLSAION_BitNumber 0x1C
91 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
92
93 /* --- CFGR Register ---*/
94 /* Alias word address of I2SSRC bit */
95 #define CFGR_OFFSET (RCC_OFFSET + 0x08)
96 #define I2SSRC_BitNumber 0x17
97 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
98
99 /* --- BDCR Register ---*/
100 /* Alias word address of RTCEN bit */
101 #define BDCR_OFFSET (RCC_OFFSET + 0x70)
102 #define RTCEN_BitNumber 0x0F
103 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
104 /* Alias word address of BDRST bit */
105 #define BDRST_BitNumber 0x10
106 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
107
108 /* --- CSR Register ---*/
109 /* Alias word address of LSION bit */
110 #define CSR_OFFSET (RCC_OFFSET + 0x74)
111 #define LSION_BitNumber 0x00
112 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
113
114 /* --- DCKCFGR Register ---*/
115 /* Alias word address of TIMPRE bit */
116 #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
117 #define TIMPRE_BitNumber 0x18
118 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
119 /* ---------------------- RCC registers bit mask ------------------------ */
120 /* CFGR register bit mask */
121 #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
122 #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
123
124 /* RCC Flag Mask */
125 #define FLAG_MASK ((uint8_t)0x1F)
126
127 /* CR register byte 3 (Bits[23:16]) base address */
128 #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
129
130 /* CIR register byte 2 (Bits[15:8]) base address */
131 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
132
133 /* CIR register byte 3 (Bits[23:16]) base address */
134 #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
135
136 /* BDCR register base address */
137 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
138
139 /* Private macro -------------------------------------------------------------*/
140 /* Private variables ---------------------------------------------------------*/
141 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
142
143 /* Private function prototypes -----------------------------------------------*/
144 /* Private functions ---------------------------------------------------------*/
145
146 /** @defgroup RCC_Private_Functions
147 * @{
148 */
149
150 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
151 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
152 *
153 @verbatim
154 ===================================================================================
155 ##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
156 ===================================================================================
157 [..]
158 This section provide functions allowing to configure the internal/external clocks,
159 PLLs, CSS and MCO pins.
160
161 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
162 the PLL as System clock source.
163
164 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
165 clock source.
166
167 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
168 through the PLL as System clock source. Can be used also as RTC clock source.
169
170 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
171
172 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
173 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
174 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
175 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
176
177 (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve
178 high-quality audio performance on the I2S interface or SAI interface in case
179 of STM32F429x/439x devices.
180
181 (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
182 interface and LCD TFT controller available only for STM32F42xxx/43xxx devices.
183
184 (#) CSS (Clock security system), once enable and if a HSE clock failure occurs
185 (HSE used directly or through PLL as System clock source), the System clock
186 is automatically switched to HSI and an interrupt is generated if enabled.
187 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
188 exception vector.
189
190 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
191 clock (through a configurable prescaler) on PA8 pin.
192
193 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
194 clock (through a configurable prescaler) on PC9 pin.
195 @endverbatim
196 * @{
197 */
198
199 /**
200 * @brief Resets the RCC clock configuration to the default reset state.
201 * @note The default reset state of the clock configuration is given below:
202 * - HSI ON and used as system clock source
203 * - HSE, PLL and PLLI2S OFF
204 * - AHB, APB1 and APB2 prescaler set to 1.
205 * - CSS, MCO1 and MCO2 OFF
206 * - All interrupts disabled
207 * @note This function doesn't modify the configuration of the
208 * - Peripheral clocks
209 * - LSI, LSE and RTC clocks
210 * @param None
211 * @retval None
212 */
RCC_DeInit(void)213 void RCC_DeInit(void)
214 {
215 /* Set HSION bit */
216 RCC->CR |= (uint32_t)0x00000001;
217
218 /* Reset CFGR register */
219 RCC->CFGR = 0x00000000;
220
221 /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */
222 RCC->CR &= (uint32_t)0xEAF6FFFF;
223
224 /* Reset PLLCFGR register */
225 RCC->PLLCFGR = 0x24003010;
226
227 /* Reset PLLI2SCFGR register */
228 RCC->PLLI2SCFGR = 0x20003000;
229
230 /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */
231 RCC->PLLSAICFGR = 0x24003000;
232
233 /* Reset HSEBYP bit */
234 RCC->CR &= (uint32_t)0xFFFBFFFF;
235
236 /* Disable all interrupts */
237 RCC->CIR = 0x00000000;
238
239 /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */
240 RCC->DCKCFGR = 0x00000000;
241 }
242
243 /**
244 * @brief Configures the External High Speed oscillator (HSE).
245 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
246 * software should wait on HSERDY flag to be set indicating that HSE clock
247 * is stable and can be used to clock the PLL and/or system clock.
248 * @note HSE state can not be changed if it is used directly or through the
249 * PLL as system clock. In this case, you have to select another source
250 * of the system clock then change the HSE state (ex. disable it).
251 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
252 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
253 * was previously enabled you have to enable it again after calling this
254 * function.
255 * @param RCC_HSE: specifies the new state of the HSE.
256 * This parameter can be one of the following values:
257 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
258 * 6 HSE oscillator clock cycles.
259 * @arg RCC_HSE_ON: turn ON the HSE oscillator
260 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
261 * @retval None
262 */
RCC_HSEConfig(uint8_t RCC_HSE)263 void RCC_HSEConfig(uint8_t RCC_HSE)
264 {
265 /* Check the parameters */
266 assert_param(IS_RCC_HSE(RCC_HSE));
267
268 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
269 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
270
271 /* Set the new HSE configuration -------------------------------------------*/
272 *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
273 }
274
275 /**
276 * @brief Waits for HSE start-up.
277 * @note This functions waits on HSERDY flag to be set and return SUCCESS if
278 * this flag is set, otherwise returns ERROR if the timeout is reached
279 * and this flag is not set. The timeout value is defined by the constant
280 * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
281 * on the HSE crystal used in your application.
282 * @param None
283 * @retval An ErrorStatus enumeration value:
284 * - SUCCESS: HSE oscillator is stable and ready to use
285 * - ERROR: HSE oscillator not yet ready
286 */
RCC_WaitForHSEStartUp(void)287 ErrorStatus RCC_WaitForHSEStartUp(void)
288 {
289 __IO uint32_t startupcounter = 0;
290 ErrorStatus status = ERROR;
291 FlagStatus hsestatus = RESET;
292 /* Wait till HSE is ready and if Time out is reached exit */
293 do
294 {
295 hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
296 startupcounter++;
297 } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
298
299 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
300 {
301 status = SUCCESS;
302 }
303 else
304 {
305 status = ERROR;
306 }
307 return (status);
308 }
309
310 /**
311 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
312 * @note The calibration is used to compensate for the variations in voltage
313 * and temperature that influence the frequency of the internal HSI RC.
314 * @param HSICalibrationValue: specifies the calibration trimming value.
315 * This parameter must be a number between 0 and 0x1F.
316 * @retval None
317 */
RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)318 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
319 {
320 uint32_t tmpreg = 0;
321 /* Check the parameters */
322 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
323
324 tmpreg = RCC->CR;
325
326 /* Clear HSITRIM[4:0] bits */
327 tmpreg &= ~RCC_CR_HSITRIM;
328
329 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
330 tmpreg |= (uint32_t)HSICalibrationValue << 3;
331
332 /* Store the new value */
333 RCC->CR = tmpreg;
334 }
335
336 /**
337 * @brief Enables or disables the Internal High Speed oscillator (HSI).
338 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
339 * It is used (enabled by hardware) as system clock source after startup
340 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
341 * of the HSE used directly or indirectly as system clock (if the Clock
342 * Security System CSS is enabled).
343 * @note HSI can not be stopped if it is used as system clock source. In this case,
344 * you have to select another source of the system clock then stop the HSI.
345 * @note After enabling the HSI, the application software should wait on HSIRDY
346 * flag to be set indicating that HSI clock is stable and can be used as
347 * system clock source.
348 * @param NewState: new state of the HSI.
349 * This parameter can be: ENABLE or DISABLE.
350 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
351 * clock cycles.
352 * @retval None
353 */
RCC_HSICmd(FunctionalState NewState)354 void RCC_HSICmd(FunctionalState NewState)
355 {
356 /* Check the parameters */
357 assert_param(IS_FUNCTIONAL_STATE(NewState));
358
359 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
360 }
361
362 /**
363 * @brief Configures the External Low Speed oscillator (LSE).
364 * @note As the LSE is in the Backup domain and write access is denied to
365 * this domain after reset, you have to enable write access using
366 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
367 * (to be done once after reset).
368 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
369 * software should wait on LSERDY flag to be set indicating that LSE clock
370 * is stable and can be used to clock the RTC.
371 * @param RCC_LSE: specifies the new state of the LSE.
372 * This parameter can be one of the following values:
373 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
374 * 6 LSE oscillator clock cycles.
375 * @arg RCC_LSE_ON: turn ON the LSE oscillator
376 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
377 * @retval None
378 */
RCC_LSEConfig(uint8_t RCC_LSE)379 void RCC_LSEConfig(uint8_t RCC_LSE)
380 {
381 /* Check the parameters */
382 assert_param(IS_RCC_LSE(RCC_LSE));
383
384 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
385 /* Reset LSEON bit */
386 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
387
388 /* Reset LSEBYP bit */
389 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
390
391 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
392 switch (RCC_LSE)
393 {
394 case RCC_LSE_ON:
395 /* Set LSEON bit */
396 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
397 break;
398 case RCC_LSE_Bypass:
399 /* Set LSEBYP and LSEON bits */
400 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
401 break;
402 default:
403 break;
404 }
405 }
406
407 /**
408 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
409 * @note After enabling the LSI, the application software should wait on
410 * LSIRDY flag to be set indicating that LSI clock is stable and can
411 * be used to clock the IWDG and/or the RTC.
412 * @note LSI can not be disabled if the IWDG is running.
413 * @param NewState: new state of the LSI.
414 * This parameter can be: ENABLE or DISABLE.
415 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
416 * clock cycles.
417 * @retval None
418 */
RCC_LSICmd(FunctionalState NewState)419 void RCC_LSICmd(FunctionalState NewState)
420 {
421 /* Check the parameters */
422 assert_param(IS_FUNCTIONAL_STATE(NewState));
423
424 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
425 }
426
427 #if defined(STM32F446xx)
428 /**
429 * @brief Configures the main PLL clock source, multiplication and division factors.
430 * @note This function must be used only when the main PLL is disabled.
431 *
432 * @param RCC_PLLSource: specifies the PLL entry clock source.
433 * This parameter can be one of the following values:
434 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
435 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
436 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
437 *
438 * @param PLLM: specifies the division factor for PLL VCO input clock
439 * This parameter must be a number between 0 and 63.
440 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
441 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
442 * of 2 MHz to limit PLL jitter.
443 *
444 * @param PLLN: specifies the multiplication factor for PLL VCO output clock
445 * This parameter must be a number between 192 and 432.
446 * @note You have to set the PLLN parameter correctly to ensure that the VCO
447 * output frequency is between 192 and 432 MHz.
448 *
449 * @param PLLP: specifies the division factor for main system clock (SYSCLK)
450 * This parameter must be a number in the range {2, 4, 6, or 8}.
451 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
452 * the System clock frequency.
453 *
454 * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
455 * This parameter must be a number between 4 and 15.
456 *
457 * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
458 * This parameter must be a number between 2 and 7.
459 *
460 * @note If the USB OTG FS is used in your application, you have to set the
461 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
462 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
463 * correctly.
464 *
465 * @retval None
466 */
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP,uint32_t PLLQ,uint32_t PLLR)467 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
468 {
469 /* Check the parameters */
470 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
471 assert_param(IS_RCC_PLLM_VALUE(PLLM));
472 assert_param(IS_RCC_PLLN_VALUE(PLLN));
473 assert_param(IS_RCC_PLLP_VALUE(PLLP));
474 assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
475 assert_param(IS_RCC_PLLR_VALUE(PLLR));
476
477 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
478 (PLLQ << 24) | (PLLR << 28);
479 }
480 #endif /* STM32F446xx */
481
482 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
483 /**
484 * @brief Configures the main PLL clock source, multiplication and division factors.
485 * @note This function must be used only when the main PLL is disabled.
486 *
487 * @param RCC_PLLSource: specifies the PLL entry clock source.
488 * This parameter can be one of the following values:
489 * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
490 * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
491 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
492 *
493 * @param PLLM: specifies the division factor for PLL VCO input clock
494 * This parameter must be a number between 0 and 63.
495 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
496 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
497 * of 2 MHz to limit PLL jitter.
498 *
499 * @param PLLN: specifies the multiplication factor for PLL VCO output clock
500 * This parameter must be a number between 192 and 432.
501 * @note You have to set the PLLN parameter correctly to ensure that the VCO
502 * output frequency is between 192 and 432 MHz.
503 *
504 * @param PLLP: specifies the division factor for main system clock (SYSCLK)
505 * This parameter must be a number in the range {2, 4, 6, or 8}.
506 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
507 * the System clock frequency.
508 *
509 * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
510 * This parameter must be a number between 4 and 15.
511 * @note If the USB OTG FS is used in your application, you have to set the
512 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
513 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
514 * correctly.
515 *
516 * @retval None
517 */
RCC_PLLConfig(uint32_t RCC_PLLSource,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP,uint32_t PLLQ)518 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
519 {
520 /* Check the parameters */
521 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
522 assert_param(IS_RCC_PLLM_VALUE(PLLM));
523 assert_param(IS_RCC_PLLN_VALUE(PLLN));
524 assert_param(IS_RCC_PLLP_VALUE(PLLP));
525 assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
526
527 RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
528 (PLLQ << 24);
529 }
530 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
531
532 /**
533 * @brief Enables or disables the main PLL.
534 * @note After enabling the main PLL, the application software should wait on
535 * PLLRDY flag to be set indicating that PLL clock is stable and can
536 * be used as system clock source.
537 * @note The main PLL can not be disabled if it is used as system clock source
538 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
539 * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
540 * @retval None
541 */
RCC_PLLCmd(FunctionalState NewState)542 void RCC_PLLCmd(FunctionalState NewState)
543 {
544 /* Check the parameters */
545 assert_param(IS_FUNCTIONAL_STATE(NewState));
546 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
547 }
548
549 #if defined(STM32F40_41xxx) || defined(STM32F401xx)
550 /**
551 * @brief Configures the PLLI2S clock multiplication and division factors.
552 *
553 * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx
554 * or STM32F401xx devices.
555 *
556 * @note This function must be used only when the PLLI2S is disabled.
557 * @note PLLI2S clock source is common with the main PLL (configured in
558 * RCC_PLLConfig function )
559 *
560 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
561 * This parameter must be a number between 192 and 432.
562 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
563 * output frequency is between 192 and 432 MHz.
564 *
565 * @param PLLI2SR: specifies the division factor for I2S clock
566 * This parameter must be a number between 2 and 7.
567 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
568 * on the I2S clock frequency.
569 *
570 * @retval None
571 */
RCC_PLLI2SConfig(uint32_t PLLI2SN,uint32_t PLLI2SR)572 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
573 {
574 /* Check the parameters */
575 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
576 assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
577
578 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
579 }
580 #endif /* STM32F40_41xxx || STM32F401xx */
581
582 #if defined(STM32F411xE)
583 /**
584 * @brief Configures the PLLI2S clock multiplication and division factors.
585 *
586 * @note This function can be used only for STM32F411xE devices.
587 *
588 * @note This function must be used only when the PLLI2S is disabled.
589 * @note PLLI2S clock source is common with the main PLL (configured in
590 * RCC_PLLConfig function )
591 *
592 * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
593 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
594 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
595 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
596 * of 2 MHz to limit PLLI2S jitter.
597 *
598 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
599 * This parameter must be a number between 192 and 432.
600 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
601 * output frequency is between 192 and 432 MHz.
602 *
603 * @param PLLI2SR: specifies the division factor for I2S clock
604 * This parameter must be a number between 2 and 7.
605 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
606 * on the I2S clock frequency.
607 *
608 * @retval None
609 */
RCC_PLLI2SConfig(uint32_t PLLI2SN,uint32_t PLLI2SR,uint32_t PLLI2SM)610 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
611 {
612 /* Check the parameters */
613 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
614 assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM));
615 assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
616
617 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
618 }
619 #endif /* STM32F411xE */
620
621 #if defined(STM32F427_437xx) || defined(STM32F429_439xx)
622 /**
623 * @brief Configures the PLLI2S clock multiplication and division factors.
624 *
625 * @note This function can be used only for STM32F42xxx/43xxx devices
626 *
627 * @note This function must be used only when the PLLI2S is disabled.
628 * @note PLLI2S clock source is common with the main PLL (configured in
629 * RCC_PLLConfig function )
630 *
631 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
632 * This parameter must be a number between 192 and 432.
633 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
634 * output frequency is between 192 and 432 MHz.
635 *
636 * @param PLLI2SQ: specifies the division factor for SAI1 clock
637 * This parameter must be a number between 2 and 15.
638 *
639 * @param PLLI2SR: specifies the division factor for I2S clock
640 * This parameter must be a number between 2 and 7.
641 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
642 * on the I2S clock frequency.
643 *
644 * @retval None
645 */
RCC_PLLI2SConfig(uint32_t PLLI2SN,uint32_t PLLI2SQ,uint32_t PLLI2SR)646 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
647 {
648 /* Check the parameters */
649 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
650 assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
651 assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
652
653 RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
654 }
655 #endif /* STM32F427_437xx || STM32F429_439xx */
656
657 #if defined(STM32F446xx)
658 /**
659 * @brief Configures the PLLI2S clock multiplication and division factors.
660 *
661 * @note This function can be used only for STM32F446xx devices
662 *
663 * @note This function must be used only when the PLLI2S is disabled.
664 * @note PLLI2S clock source is common with the main PLL (configured in
665 * RCC_PLLConfig function )
666 *
667 * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
668 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
669 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
670 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
671 * of 2 MHz to limit PLLI2S jitter.
672 *
673 * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
674 * This parameter must be a number between 192 and 432.
675 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
676 * output frequency is between 192 and 432 MHz.
677 *
678 * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output
679 * This parameter must be a number in the range {2, 4, 6, or 8}.
680 *
681 * @param PLLI2SQ: specifies the division factor for SAI1 clock
682 * This parameter must be a number between 2 and 15.
683 *
684 * @param PLLI2SR: specifies the division factor for I2S clock
685 * This parameter must be a number between 2 and 7.
686 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
687 * on the I2S clock frequency.
688 * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
689 *
690 * @retval None
691 */
RCC_PLLI2SConfig(uint32_t PLLI2SM,uint32_t PLLI2SN,uint32_t PLLI2SP,uint32_t PLLI2SQ,uint32_t PLLI2SR)692 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
693 {
694 /* Check the parameters */
695 assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM));
696 assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
697 assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP));
698 assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
699 assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
700
701 RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
702 }
703 #endif /* STM32F446xx */
704
705 /**
706 * @brief Enables or disables the PLLI2S.
707 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
708 * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
709 * @retval None
710 */
RCC_PLLI2SCmd(FunctionalState NewState)711 void RCC_PLLI2SCmd(FunctionalState NewState)
712 {
713 /* Check the parameters */
714 assert_param(IS_FUNCTIONAL_STATE(NewState));
715 *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
716 }
717
718 #if defined(STM32F446xx)
719 /**
720 * @brief Configures the PLLSAI clock multiplication and division factors.
721 *
722 * @note This function can be used only for STM32F446xx devices
723 *
724 * @note This function must be used only when the PLLSAI is disabled.
725 * @note PLLSAI clock source is common with the main PLL (configured in
726 * RCC_PLLConfig function )
727 *
728 * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock
729 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
730 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
731 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
732 * of 2 MHz to limit PLLSAI jitter.
733 *
734 * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
735 * This parameter must be a number between 192 and 432.
736 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
737 * output frequency is between 192 and 432 MHz.
738 *
739 * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
740 * This parameter must be a number in the range {2, 4, 6, or 8}.
741 *
742 * @param PLLSAIQ: specifies the division factor for SAI1 clock
743 * This parameter must be a number between 2 and 15.
744 *
745 * @retval None
746 */
RCC_PLLSAIConfig(uint32_t PLLSAIM,uint32_t PLLSAIN,uint32_t PLLSAIP,uint32_t PLLSAIQ)747 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
748 {
749 /* Check the parameters */
750 assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM));
751 assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
752 assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
753 assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
754
755 RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
756 }
757 #endif /* STM32F446xx */
758
759 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
760 /**
761 * @brief Configures the PLLSAI clock multiplication and division factors.
762 *
763 * @note This function can be used only for STM32F42xxx/43xxx devices
764 *
765 * @note This function must be used only when the PLLSAI is disabled.
766 * @note PLLSAI clock source is common with the main PLL (configured in
767 * RCC_PLLConfig function )
768 *
769 * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
770 * This parameter must be a number between 192 and 432.
771 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
772 * output frequency is between 192 and 432 MHz.
773 *
774 * @param PLLSAIQ: specifies the division factor for SAI1 clock
775 * This parameter must be a number between 2 and 15.
776 *
777 * @param PLLSAIR: specifies the division factor for LTDC clock
778 * This parameter must be a number between 2 and 7.
779 *
780 * @retval None
781 */
RCC_PLLSAIConfig(uint32_t PLLSAIN,uint32_t PLLSAIQ,uint32_t PLLSAIR)782 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
783 {
784 /* Check the parameters */
785 assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
786 assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
787 assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
788
789 RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
790 }
791 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
792
793 /**
794 * @brief Enables or disables the PLLSAI.
795 *
796 * @note This function can be used only for STM32F42xxx/43xxx devices
797 *
798 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
799 * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
800 * @retval None
801 */
RCC_PLLSAICmd(FunctionalState NewState)802 void RCC_PLLSAICmd(FunctionalState NewState)
803 {
804 /* Check the parameters */
805 assert_param(IS_FUNCTIONAL_STATE(NewState));
806 *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState;
807 }
808
809 /**
810 * @brief Enables or disables the Clock Security System.
811 * @note If a failure is detected on the HSE oscillator clock, this oscillator
812 * is automatically disabled and an interrupt is generated to inform the
813 * software about the failure (Clock Security System Interrupt, CSSI),
814 * allowing the MCU to perform rescue operations. The CSSI is linked to
815 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
816 * @param NewState: new state of the Clock Security System.
817 * This parameter can be: ENABLE or DISABLE.
818 * @retval None
819 */
RCC_ClockSecuritySystemCmd(FunctionalState NewState)820 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
821 {
822 /* Check the parameters */
823 assert_param(IS_FUNCTIONAL_STATE(NewState));
824 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
825 }
826
827 /**
828 * @brief Selects the clock source to output on MCO1 pin(PA8).
829 * @note PA8 should be configured in alternate function mode.
830 * @param RCC_MCO1Source: specifies the clock source to output.
831 * This parameter can be one of the following values:
832 * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
833 * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
834 * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
835 * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
836 * @param RCC_MCO1Div: specifies the MCO1 prescaler.
837 * This parameter can be one of the following values:
838 * @arg RCC_MCO1Div_1: no division applied to MCO1 clock
839 * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
840 * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
841 * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
842 * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
843 * @retval None
844 */
RCC_MCO1Config(uint32_t RCC_MCO1Source,uint32_t RCC_MCO1Div)845 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
846 {
847 uint32_t tmpreg = 0;
848
849 /* Check the parameters */
850 assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
851 assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));
852
853 tmpreg = RCC->CFGR;
854
855 /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
856 tmpreg &= CFGR_MCO1_RESET_MASK;
857
858 /* Select MCO1 clock source and prescaler */
859 tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
860
861 /* Store the new value */
862 RCC->CFGR = tmpreg;
863 }
864
865 /**
866 * @brief Selects the clock source to output on MCO2 pin(PC9).
867 * @note PC9 should be configured in alternate function mode.
868 * @param RCC_MCO2Source: specifies the clock source to output.
869 * This parameter can be one of the following values:
870 * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
871 * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
872 * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
873 * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
874 * @param RCC_MCO2Div: specifies the MCO2 prescaler.
875 * This parameter can be one of the following values:
876 * @arg RCC_MCO2Div_1: no division applied to MCO2 clock
877 * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
878 * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
879 * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
880 * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
881 * @retval None
882 */
RCC_MCO2Config(uint32_t RCC_MCO2Source,uint32_t RCC_MCO2Div)883 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
884 {
885 uint32_t tmpreg = 0;
886
887 /* Check the parameters */
888 assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
889 assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
890
891 tmpreg = RCC->CFGR;
892
893 /* Clear MCO2 and MCO2PRE[2:0] bits */
894 tmpreg &= CFGR_MCO2_RESET_MASK;
895
896 /* Select MCO2 clock source and prescaler */
897 tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
898
899 /* Store the new value */
900 RCC->CFGR = tmpreg;
901 }
902
903 /**
904 * @}
905 */
906
907 /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
908 * @brief System, AHB and APB busses clocks configuration functions
909 *
910 @verbatim
911 ===============================================================================
912 ##### System, AHB and APB busses clocks configuration functions #####
913 ===============================================================================
914 [..]
915 This section provide functions allowing to configure the System, AHB, APB1 and
916 APB2 busses clocks.
917
918 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
919 HSE and PLL.
920 The AHB clock (HCLK) is derived from System clock through configurable
921 prescaler and used to clock the CPU, memory and peripherals mapped
922 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
923 from AHB clock through configurable prescalers and used to clock
924 the peripherals mapped on these busses. You can use
925 "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
926
927 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
928 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
929 from an external clock mapped on the I2S_CKIN pin.
930 You have to use RCC_I2SCLKConfig() function to configure this clock.
931 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
932 divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
933 functions to configure this clock.
934 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
935 to work correctly, while the SDIO require a frequency equal or lower than
936 to 48. This clock is derived of the main PLL through PLLQ divider.
937 (+@) IWDG clock which is always the LSI clock.
938
939 (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
940 of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
941 on the device voltage range, the maximum frequency should be adapted accordingly:
942 +-------------------------------------------------------------------------------------+
943 | Latency | HCLK clock frequency (MHz) |
944 | |---------------------------------------------------------------------|
945 | | voltage range | voltage range | voltage range | voltage range |
946 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
947 |---------------|----------------|----------------|-----------------|-----------------|
948 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
949 |---------------|----------------|----------------|-----------------|-----------------|
950 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
951 |---------------|----------------|----------------|-----------------|-----------------|
952 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
953 |---------------|----------------|----------------|-----------------|-----------------|
954 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
955 |---------------|----------------|----------------|-----------------|-----------------|
956 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
957 |---------------|----------------|----------------|-----------------|-----------------|
958 |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
959 |---------------|----------------|----------------|-----------------|-----------------|
960 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
961 |---------------|----------------|----------------|-----------------|-----------------|
962 |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
963 +---------------|----------------|----------------|-----------------|-----------------+
964 (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
965 PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
966 frequency should be adapted accordingly:
967 +-------------------------------------------------------------------------------------+
968 | Latency | HCLK clock frequency (MHz) |
969 | |---------------------------------------------------------------------|
970 | | voltage range | voltage range | voltage range | voltage range |
971 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
972 |---------------|----------------|----------------|-----------------|-----------------|
973 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
974 |---------------|----------------|----------------|-----------------|-----------------|
975 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
976 |---------------|----------------|----------------|-----------------|-----------------|
977 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
978 |---------------|----------------|----------------|-----------------|-----------------|
979 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
980 |---------------|----------------|----------------|-----------------|-----------------|
981 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
982 |---------------|----------------|----------------|-----------------|-----------------|
983 |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
984 |---------------|----------------|----------------|-----------------|-----------------|
985 |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
986 |---------------|----------------|----------------|-----------------|-----------------|
987 |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
988 |---------------|----------------|----------------|-----------------|-----------------|
989 |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
990 +-------------------------------------------------------------------------------------+
991
992 (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
993 PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
994 frequency should be adapted accordingly:
995 +-------------------------------------------------------------------------------------+
996 | Latency | HCLK clock frequency (MHz) |
997 | |---------------------------------------------------------------------|
998 | | voltage range | voltage range | voltage range | voltage range |
999 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
1000 |---------------|----------------|----------------|-----------------|-----------------|
1001 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
1002 |---------------|----------------|----------------|-----------------|-----------------|
1003 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
1004 |---------------|----------------|----------------|-----------------|-----------------|
1005 |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
1006 |---------------|----------------|----------------|-----------------|-----------------|
1007 |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
1008 |---------------|----------------|----------------|-----------------|-----------------|
1009 |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
1010 +-------------------------------------------------------------------------------------+
1011
1012 (#) For STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
1013 PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
1014 frequency should be adapted accordingly:
1015 +-------------------------------------------------------------------------------------+
1016 | Latency | HCLK clock frequency (MHz) |
1017 | |---------------------------------------------------------------------|
1018 | | voltage range | voltage range | voltage range | voltage range |
1019 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
1020 |---------------|----------------|----------------|-----------------|-----------------|
1021 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
1022 |---------------|----------------|----------------|-----------------|-----------------|
1023 |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
1024 |---------------|----------------|----------------|-----------------|-----------------|
1025 |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
1026 |---------------|----------------|----------------|-----------------|-----------------|
1027 |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
1028 |---------------|----------------|----------------|-----------------|-----------------|
1029 |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 |
1030 |---------------|----------------|----------------|-----------------|-----------------|
1031 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 |
1032 |---------------|----------------|----------------|-----------------|-----------------|
1033 |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 |
1034 +-------------------------------------------------------------------------------------+
1035
1036 -@- On STM32F405xx/407xx and STM32F415xx/417xx devices:
1037 (++) when VOS = '0', the maximum value of fHCLK = 144MHz.
1038 (++) when VOS = '1', the maximum value of fHCLK = 168MHz.
1039 [..]
1040 On STM32F42xxx/43xxx devices:
1041 (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
1042 (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
1043 (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
1044 [..]
1045 On STM32F401x devices:
1046 (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
1047 (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
1048 On STM32F411xE devices:
1049 (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
1050 (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
1051 (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
1052
1053 You can use PWR_MainRegulatorModeConfig() function to control VOS bits.
1054
1055 @endverbatim
1056 * @{
1057 */
1058
1059 /**
1060 * @brief Configures the system clock (SYSCLK).
1061 * @note The HSI is used (enabled by hardware) as system clock source after
1062 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
1063 * of failure of the HSE used directly or indirectly as system clock
1064 * (if the Clock Security System CSS is enabled).
1065 * @note A switch from one clock source to another occurs only if the target
1066 * clock source is ready (clock stable after startup delay or PLL locked).
1067 * If a clock source which is not yet ready is selected, the switch will
1068 * occur when the clock source will be ready.
1069 * You can use RCC_GetSYSCLKSource() function to know which clock is
1070 * currently used as system clock source.
1071 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
1072 * This parameter can be one of the following values:
1073 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
1074 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
1075 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
1076 * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F446xx devices
1077 * @retval None
1078 */
RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)1079 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
1080 {
1081 uint32_t tmpreg = 0;
1082
1083 /* Check the parameters */
1084 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
1085
1086 tmpreg = RCC->CFGR;
1087
1088 /* Clear SW[1:0] bits */
1089 tmpreg &= ~RCC_CFGR_SW;
1090
1091 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
1092 tmpreg |= RCC_SYSCLKSource;
1093
1094 /* Store the new value */
1095 RCC->CFGR = tmpreg;
1096 }
1097
1098 /**
1099 * @brief Returns the clock source used as system clock.
1100 * @param None
1101 * @retval The clock source used as system clock. The returned value can be one
1102 * of the following:
1103 * - 0x00: HSI used as system clock
1104 * - 0x04: HSE used as system clock
1105 * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
1106 * - 0x0C: PLL R used as system clock (only for STM32F446xx devices)
1107 */
RCC_GetSYSCLKSource(void)1108 uint8_t RCC_GetSYSCLKSource(void)
1109 {
1110 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
1111 }
1112
1113 /**
1114 * @brief Configures the AHB clock (HCLK).
1115 * @note Depending on the device voltage range, the software has to set correctly
1116 * these bits to ensure that HCLK not exceed the maximum allowed frequency
1117 * (for more details refer to section above
1118 * "CPU, AHB and APB busses clocks configuration functions")
1119 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
1120 * the system clock (SYSCLK).
1121 * This parameter can be one of the following values:
1122 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
1123 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
1124 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
1125 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
1126 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
1127 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
1128 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
1129 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
1130 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
1131 * @retval None
1132 */
RCC_HCLKConfig(uint32_t RCC_SYSCLK)1133 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
1134 {
1135 uint32_t tmpreg = 0;
1136
1137 /* Check the parameters */
1138 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
1139
1140 tmpreg = RCC->CFGR;
1141
1142 /* Clear HPRE[3:0] bits */
1143 tmpreg &= ~RCC_CFGR_HPRE;
1144
1145 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
1146 tmpreg |= RCC_SYSCLK;
1147
1148 /* Store the new value */
1149 RCC->CFGR = tmpreg;
1150 }
1151
1152
1153 /**
1154 * @brief Configures the Low Speed APB clock (PCLK1).
1155 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
1156 * the AHB clock (HCLK).
1157 * This parameter can be one of the following values:
1158 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
1159 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
1160 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
1161 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
1162 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
1163 * @retval None
1164 */
RCC_PCLK1Config(uint32_t RCC_HCLK)1165 void RCC_PCLK1Config(uint32_t RCC_HCLK)
1166 {
1167 uint32_t tmpreg = 0;
1168
1169 /* Check the parameters */
1170 assert_param(IS_RCC_PCLK(RCC_HCLK));
1171
1172 tmpreg = RCC->CFGR;
1173
1174 /* Clear PPRE1[2:0] bits */
1175 tmpreg &= ~RCC_CFGR_PPRE1;
1176
1177 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
1178 tmpreg |= RCC_HCLK;
1179
1180 /* Store the new value */
1181 RCC->CFGR = tmpreg;
1182 }
1183
1184 /**
1185 * @brief Configures the High Speed APB clock (PCLK2).
1186 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
1187 * the AHB clock (HCLK).
1188 * This parameter can be one of the following values:
1189 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
1190 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
1191 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
1192 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
1193 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
1194 * @retval None
1195 */
RCC_PCLK2Config(uint32_t RCC_HCLK)1196 void RCC_PCLK2Config(uint32_t RCC_HCLK)
1197 {
1198 uint32_t tmpreg = 0;
1199
1200 /* Check the parameters */
1201 assert_param(IS_RCC_PCLK(RCC_HCLK));
1202
1203 tmpreg = RCC->CFGR;
1204
1205 /* Clear PPRE2[2:0] bits */
1206 tmpreg &= ~RCC_CFGR_PPRE2;
1207
1208 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
1209 tmpreg |= RCC_HCLK << 3;
1210
1211 /* Store the new value */
1212 RCC->CFGR = tmpreg;
1213 }
1214
1215 /**
1216 * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
1217 * PCLK1 and PCLK2.
1218 *
1219 * @note The system frequency computed by this function is not the real
1220 * frequency in the chip. It is calculated based on the predefined
1221 * constant and the selected clock source:
1222 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1223 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
1224 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
1225 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
1226 * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
1227 * 16 MHz) but the real value may vary depending on the variations
1228 * in voltage and temperature.
1229 * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
1230 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
1231 * frequency of the crystal used. Otherwise, this function may
1232 * have wrong result.
1233 *
1234 * @note The result of this function could be not correct when using fractional
1235 * value for HSE crystal.
1236 *
1237 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
1238 * the clocks frequencies.
1239 *
1240 * @note This function can be used by the user application to compute the
1241 * baudrate for the communication peripherals or configure other parameters.
1242 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
1243 * must be called to update the structure's field. Otherwise, any
1244 * configuration based on this function will be incorrect.
1245 *
1246 * @retval None
1247 */
RCC_GetClocksFreq(RCC_ClocksTypeDef * RCC_Clocks)1248 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
1249 {
1250 uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
1251 #if defined(STM32F446xx)
1252 uint32_t pllr = 2;
1253 #endif /* STM32F446xx */
1254
1255 /* Get SYSCLK source -------------------------------------------------------*/
1256 tmp = RCC->CFGR & RCC_CFGR_SWS;
1257
1258 switch (tmp)
1259 {
1260 case 0x00: /* HSI used as system clock source */
1261 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
1262 break;
1263 case 0x04: /* HSE used as system clock source */
1264 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
1265 break;
1266 case 0x08: /* PLL P used as system clock source */
1267
1268 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1269 SYSCLK = PLL_VCO / PLLP
1270 */
1271 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
1272 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
1273
1274 if (pllsource != 0)
1275 {
1276 /* HSE used as PLL clock source */
1277 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1278 }
1279 else
1280 {
1281 /* HSI used as PLL clock source */
1282 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1283 }
1284
1285 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
1286 RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
1287 break;
1288
1289 #if defined(STM32F446xx)
1290 case 0x0C: /* PLL R used as system clock source */
1291 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1292 SYSCLK = PLL_VCO / PLLR
1293 */
1294 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
1295 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
1296
1297 if (pllsource != 0)
1298 {
1299 /* HSE used as PLL clock source */
1300 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1301 }
1302 else
1303 {
1304 /* HSI used as PLL clock source */
1305 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
1306 }
1307
1308 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
1309 RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
1310 break;
1311 #endif /* STM32F446xx */
1312
1313 default:
1314 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
1315 break;
1316 }
1317 /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
1318
1319 /* Get HCLK prescaler */
1320 tmp = RCC->CFGR & RCC_CFGR_HPRE;
1321 tmp = tmp >> 4;
1322 presc = APBAHBPrescTable[tmp];
1323 /* HCLK clock frequency */
1324 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
1325
1326 /* Get PCLK1 prescaler */
1327 tmp = RCC->CFGR & RCC_CFGR_PPRE1;
1328 tmp = tmp >> 10;
1329 presc = APBAHBPrescTable[tmp];
1330 /* PCLK1 clock frequency */
1331 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
1332
1333 /* Get PCLK2 prescaler */
1334 tmp = RCC->CFGR & RCC_CFGR_PPRE2;
1335 tmp = tmp >> 13;
1336 presc = APBAHBPrescTable[tmp];
1337 /* PCLK2 clock frequency */
1338 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
1339 }
1340
1341 /**
1342 * @}
1343 */
1344
1345 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
1346 * @brief Peripheral clocks configuration functions
1347 *
1348 @verbatim
1349 ===============================================================================
1350 ##### Peripheral clocks configuration functions #####
1351 ===============================================================================
1352 [..] This section provide functions allowing to configure the Peripheral clocks.
1353
1354 (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided
1355 by 2 to 31.
1356
1357 (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
1358 except internal SRAM, Flash and JTAG. Before to start using a peripheral
1359 you have to enable its interface clock. You can do this using
1360 RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
1361
1362 (#) To reset the peripherals configuration (to the default state after device reset)
1363 you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
1364 RCC_APB1PeriphResetCmd() functions.
1365
1366 (#) To further reduce power consumption in SLEEP mode the peripheral clocks
1367 can be disabled prior to executing the WFI or WFE instructions.
1368 You can do this using RCC_AHBPeriphClockLPModeCmd(),
1369 RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.
1370
1371 @endverbatim
1372 * @{
1373 */
1374
1375 /**
1376 * @brief Configures the RTC clock (RTCCLK).
1377 * @note As the RTC clock configuration bits are in the Backup domain and write
1378 * access is denied to this domain after reset, you have to enable write
1379 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
1380 * the RTC clock source (to be done once after reset).
1381 * @note Once the RTC clock is configured it can't be changed unless the
1382 * Backup domain is reset using RCC_BackupResetCmd() function, or by
1383 * a Power On Reset (POR).
1384 *
1385 * @param RCC_RTCCLKSource: specifies the RTC clock source.
1386 * This parameter can be one of the following values:
1387 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
1388 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
1389 * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
1390 * as RTC clock, where x:[2,31]
1391 *
1392 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
1393 * work in STOP and STANDBY modes, and can be used as wakeup source.
1394 * However, when the HSE clock is used as RTC clock source, the RTC
1395 * cannot be used in STOP and STANDBY modes.
1396 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
1397 * RTC clock source).
1398 *
1399 * @retval None
1400 */
RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)1401 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1402 {
1403 uint32_t tmpreg = 0;
1404
1405 /* Check the parameters */
1406 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1407
1408 if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
1409 { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
1410 tmpreg = RCC->CFGR;
1411
1412 /* Clear RTCPRE[4:0] bits */
1413 tmpreg &= ~RCC_CFGR_RTCPRE;
1414
1415 /* Configure HSE division factor for RTC clock */
1416 tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
1417
1418 /* Store the new value */
1419 RCC->CFGR = tmpreg;
1420 }
1421
1422 /* Select the RTC clock source */
1423 RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
1424 }
1425
1426 /**
1427 * @brief Enables or disables the RTC clock.
1428 * @note This function must be used only after the RTC clock source was selected
1429 * using the RCC_RTCCLKConfig function.
1430 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
1431 * @retval None
1432 */
RCC_RTCCLKCmd(FunctionalState NewState)1433 void RCC_RTCCLKCmd(FunctionalState NewState)
1434 {
1435 /* Check the parameters */
1436 assert_param(IS_FUNCTIONAL_STATE(NewState));
1437
1438 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
1439 }
1440
1441 /**
1442 * @brief Forces or releases the Backup domain reset.
1443 * @note This function resets the RTC peripheral (including the backup registers)
1444 * and the RTC clock source selection in RCC_CSR register.
1445 * @note The BKPSRAM is not affected by this reset.
1446 * @param NewState: new state of the Backup domain reset.
1447 * This parameter can be: ENABLE or DISABLE.
1448 * @retval None
1449 */
RCC_BackupResetCmd(FunctionalState NewState)1450 void RCC_BackupResetCmd(FunctionalState NewState)
1451 {
1452 /* Check the parameters */
1453 assert_param(IS_FUNCTIONAL_STATE(NewState));
1454 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1455 }
1456
1457 #if defined(STM32F446xx)
1458 /**
1459 * @brief Configures the I2S clock source (I2SCLK).
1460 * @note This function must be called before enabling the I2S APB clock.
1461 *
1462 * @param RCC_I2SAPBx: specifies the APBx I2S clock source.
1463 * This parameter can be one of the following values:
1464 * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
1465 * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
1466 *
1467 * @param RCC_I2SCLKSource: specifies the I2S clock source.
1468 * This parameter can be one of the following values:
1469 * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
1470 * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
1471 * used as I2S clock source
1472 * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
1473 * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
1474 * @retval None
1475 */
RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx,uint32_t RCC_I2SCLKSource)1476 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
1477 {
1478 /* Check the parameters */
1479 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1480 assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
1481
1482 if(RCC_I2SAPBx == RCC_I2SBus_APB1)
1483 {
1484 /* Clear APB1 I2Sx clock source selection bits */
1485 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC;
1486 /* Set new APB1 I2Sx clock source*/
1487 RCC->DCKCFGR |= RCC_I2SCLKSource;
1488 }
1489 else
1490 {
1491 /* Clear APB2 I2Sx clock source selection bits */
1492 RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC;
1493 /* Set new APB2 I2Sx clock source */
1494 RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
1495 }
1496 }
1497
1498 /**
1499 * @brief Configures the SAIx clock source (SAIxCLK).
1500 * @note This function must be called before enabling the SAIx APB clock.
1501 *
1502 * @param RCC_SAIInstance: specifies the SAIx clock source.
1503 * This parameter can be one of the following values:
1504 * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
1505 * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
1506 *
1507 * @param RCC_SAICLKSource: specifies the SAI clock source.
1508 * This parameter can be one of the following values:
1509 * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
1510 * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
1511 * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
1512 * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
1513 * @retval None
1514 */
RCC_SAICLKConfig(uint32_t RCC_SAIInstance,uint32_t RCC_SAICLKSource)1515 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
1516 {
1517 /* Check the parameters */
1518 assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
1519 assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
1520
1521 if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
1522 {
1523 /* Clear SAI1 clock source selection bits */
1524 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC;
1525 /* Set new SAI1 clock source */
1526 RCC->DCKCFGR |= RCC_SAICLKSource;
1527 }
1528 else
1529 {
1530 /* Clear SAI2 clock source selection bits */
1531 RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC;
1532 /* Set new SAI2 clock source */
1533 RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
1534 }
1535 }
1536 #endif /* STM32F446xx */
1537
1538 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
1539 /**
1540 * @brief Configures the I2S clock source (I2SCLK).
1541 * @note This function must be called before enabling the I2S APB clock.
1542 * @param RCC_I2SCLKSource: specifies the I2S clock source.
1543 * This parameter can be one of the following values:
1544 * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
1545 * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
1546 * used as I2S clock source
1547 * @retval None
1548 */
RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)1549 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1550 {
1551 /* Check the parameters */
1552 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1553
1554 *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
1555 }
1556
1557 /**
1558 * @brief Configures SAI1BlockA clock source selection.
1559 *
1560 * @note This function can be used only for STM32F42xxx/43xxx devices.
1561 *
1562 * @note This function must be called before enabling PLLSAI, PLLI2S and
1563 * the SAI clock.
1564 * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
1565 * This parameter can be one of the following values:
1566 * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1567 * as SAI1 Block A clock
1568 * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1569 * as SAI1 Block A clock
1570 * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin
1571 * used as SAI1 Block A clock
1572 * @retval None
1573 */
RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)1574 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
1575 {
1576 uint32_t tmpreg = 0;
1577
1578 /* Check the parameters */
1579 assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
1580
1581 tmpreg = RCC->DCKCFGR;
1582
1583 /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
1584 tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
1585
1586 /* Set SAI Block A source selection value */
1587 tmpreg |= RCC_SAIBlockACLKSource;
1588
1589 /* Store the new value */
1590 RCC->DCKCFGR = tmpreg;
1591 }
1592
1593 /**
1594 * @brief Configures SAI1BlockB clock source selection.
1595 *
1596 * @note This function can be used only for STM32F42xxx/43xxx devices.
1597 *
1598 * @note This function must be called before enabling PLLSAI, PLLI2S and
1599 * the SAI clock.
1600 * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
1601 * This parameter can be one of the following values:
1602 * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
1603 * as SAI1 Block B clock
1604 * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
1605 * as SAI1 Block B clock
1606 * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin
1607 * used as SAI1 Block B clock
1608 * @retval None
1609 */
RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)1610 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
1611 {
1612 uint32_t tmpreg = 0;
1613
1614 /* Check the parameters */
1615 assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
1616
1617 tmpreg = RCC->DCKCFGR;
1618
1619 /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */
1620 tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
1621
1622 /* Set SAI Block B source selection value */
1623 tmpreg |= RCC_SAIBlockBCLKSource;
1624
1625 /* Store the new value */
1626 RCC->DCKCFGR = tmpreg;
1627 }
1628 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
1629
1630 /**
1631 * @brief Configures the SAI clock Divider coming from PLLI2S.
1632 *
1633 * @note This function can be used only for STM32F42xxx/43xxx devices.
1634 *
1635 * @note This function must be called before enabling the PLLI2S.
1636 *
1637 * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
1638 * This parameter must be a number between 1 and 32.
1639 * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
1640 *
1641 * @retval None
1642 */
RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)1643 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
1644 {
1645 uint32_t tmpreg = 0;
1646
1647 /* Check the parameters */
1648 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
1649
1650 tmpreg = RCC->DCKCFGR;
1651
1652 /* Clear PLLI2SDIVQ[4:0] bits */
1653 tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
1654
1655 /* Set PLLI2SDIVQ values */
1656 tmpreg |= (RCC_PLLI2SDivQ - 1);
1657
1658 /* Store the new value */
1659 RCC->DCKCFGR = tmpreg;
1660 }
1661
1662 /**
1663 * @brief Configures the SAI clock Divider coming from PLLSAI.
1664 *
1665 * @note This function can be used only for STM32F42xxx/43xxx devices.
1666 *
1667 * @note This function must be called before enabling the PLLSAI.
1668 *
1669 * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
1670 * This parameter must be a number between 1 and 32.
1671 * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
1672 *
1673 * @retval None
1674 */
RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)1675 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
1676 {
1677 uint32_t tmpreg = 0;
1678
1679 /* Check the parameters */
1680 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
1681
1682 tmpreg = RCC->DCKCFGR;
1683
1684 /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
1685 tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
1686
1687 /* Set PLLSAIDIVQ values */
1688 tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
1689
1690 /* Store the new value */
1691 RCC->DCKCFGR = tmpreg;
1692 }
1693
1694 /**
1695 * @brief Configures the LTDC clock Divider coming from PLLSAI.
1696 *
1697 * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices.
1698 *
1699 * @note This function must be called before enabling the PLLSAI.
1700 *
1701 * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
1702 * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
1703 * This parameter can be one of the following values:
1704 * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
1705 * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
1706 * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
1707 * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
1708 *
1709 * @retval None
1710 */
RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)1711 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
1712 {
1713 uint32_t tmpreg = 0;
1714
1715 /* Check the parameters */
1716 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR));
1717
1718 tmpreg = RCC->DCKCFGR;
1719
1720 /* Clear PLLSAIDIVR[2:0] bits */
1721 tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR;
1722
1723 /* Set PLLSAIDIVR values */
1724 tmpreg |= RCC_PLLSAIDivR;
1725
1726 /* Store the new value */
1727 RCC->DCKCFGR = tmpreg;
1728 }
1729
1730 /**
1731 * @brief Configures the Timers clocks prescalers selection.
1732 *
1733 * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
1734 *
1735 * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
1736 * This parameter can be one of the following values:
1737 * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is
1738 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
1739 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
1740 * division by 4 or more.
1741 *
1742 * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is
1743 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
1744 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
1745 * to division by 8 or more.
1746 * @retval None
1747 */
RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)1748 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
1749 {
1750 /* Check the parameters */
1751 assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
1752
1753 *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
1754 }
1755
1756 /**
1757 * @brief Enables or disables the AHB1 peripheral clock.
1758 * @note After reset, the peripheral clock (used for registers read/write access)
1759 * is disabled and the application software has to enable this clock before
1760 * using it.
1761 * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
1762 * This parameter can be any combination of the following values:
1763 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
1764 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
1765 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
1766 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
1767 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
1768 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
1769 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
1770 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
1771 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
1772 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
1773 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
1774 * @arg RCC_AHB1Periph_CRC: CRC clock
1775 * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
1776 * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
1777 * @arg RCC_AHB1Periph_DMA1: DMA1 clock
1778 * @arg RCC_AHB1Periph_DMA2: DMA2 clock
1779 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
1780 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
1781 * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
1782 * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
1783 * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
1784 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
1785 * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
1786 * @param NewState: new state of the specified peripheral clock.
1787 * This parameter can be: ENABLE or DISABLE.
1788 * @retval None
1789 */
RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph,FunctionalState NewState)1790 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1791 {
1792 /* Check the parameters */
1793 assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
1794
1795 assert_param(IS_FUNCTIONAL_STATE(NewState));
1796 if (NewState != DISABLE)
1797 {
1798 RCC->AHB1ENR |= RCC_AHB1Periph;
1799 }
1800 else
1801 {
1802 RCC->AHB1ENR &= ~RCC_AHB1Periph;
1803 }
1804 }
1805
1806 /**
1807 * @brief Enables or disables the AHB2 peripheral clock.
1808 * @note After reset, the peripheral clock (used for registers read/write access)
1809 * is disabled and the application software has to enable this clock before
1810 * using it.
1811 * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
1812 * This parameter can be any combination of the following values:
1813 * @arg RCC_AHB2Periph_DCMI: DCMI clock
1814 * @arg RCC_AHB2Periph_CRYP: CRYP clock
1815 * @arg RCC_AHB2Periph_HASH: HASH clock
1816 * @arg RCC_AHB2Periph_RNG: RNG clock
1817 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
1818 * @param NewState: new state of the specified peripheral clock.
1819 * This parameter can be: ENABLE or DISABLE.
1820 * @retval None
1821 */
RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph,FunctionalState NewState)1822 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1823 {
1824 /* Check the parameters */
1825 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1826 assert_param(IS_FUNCTIONAL_STATE(NewState));
1827
1828 if (NewState != DISABLE)
1829 {
1830 RCC->AHB2ENR |= RCC_AHB2Periph;
1831 }
1832 else
1833 {
1834 RCC->AHB2ENR &= ~RCC_AHB2Periph;
1835 }
1836 }
1837
1838 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
1839 /**
1840 * @brief Enables or disables the AHB3 peripheral clock.
1841 * @note After reset, the peripheral clock (used for registers read/write access)
1842 * is disabled and the application software has to enable this clock before
1843 * using it.
1844 * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
1845 * This parameter must be:
1846 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
1847 * - RCC_AHB3Periph_QSPI (STM32F446xx devices)
1848 * @param NewState: new state of the specified peripheral clock.
1849 * This parameter can be: ENABLE or DISABLE.
1850 * @retval None
1851 */
RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph,FunctionalState NewState)1852 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1853 {
1854 /* Check the parameters */
1855 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1856 assert_param(IS_FUNCTIONAL_STATE(NewState));
1857
1858 if (NewState != DISABLE)
1859 {
1860 RCC->AHB3ENR |= RCC_AHB3Periph;
1861 }
1862 else
1863 {
1864 RCC->AHB3ENR &= ~RCC_AHB3Periph;
1865 }
1866 }
1867 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
1868
1869 /**
1870 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
1871 * @note After reset, the peripheral clock (used for registers read/write access)
1872 * is disabled and the application software has to enable this clock before
1873 * using it.
1874 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
1875 * This parameter can be any combination of the following values:
1876 * @arg RCC_APB1Periph_TIM2: TIM2 clock
1877 * @arg RCC_APB1Periph_TIM3: TIM3 clock
1878 * @arg RCC_APB1Periph_TIM4: TIM4 clock
1879 * @arg RCC_APB1Periph_TIM5: TIM5 clock
1880 * @arg RCC_APB1Periph_TIM6: TIM6 clock
1881 * @arg RCC_APB1Periph_TIM7: TIM7 clock
1882 * @arg RCC_APB1Periph_TIM12: TIM12 clock
1883 * @arg RCC_APB1Periph_TIM13: TIM13 clock
1884 * @arg RCC_APB1Periph_TIM14: TIM14 clock
1885 * @arg RCC_APB1Periph_WWDG: WWDG clock
1886 * @arg RCC_APB1Periph_SPI2: SPI2 clock
1887 * @arg RCC_APB1Periph_SPI3: SPI3 clock
1888 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
1889 * @arg RCC_APB1Periph_USART2: USART2 clock
1890 * @arg RCC_APB1Periph_USART3: USART3 clock
1891 * @arg RCC_APB1Periph_UART4: UART4 clock
1892 * @arg RCC_APB1Periph_UART5: UART5 clock
1893 * @arg RCC_APB1Periph_I2C1: I2C1 clock
1894 * @arg RCC_APB1Periph_I2C2: I2C2 clock
1895 * @arg RCC_APB1Periph_I2C3: I2C3 clock
1896 * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
1897 * @arg RCC_APB1Periph_CAN1: CAN1 clock
1898 * @arg RCC_APB1Periph_CAN2: CAN2 clock
1899 * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
1900 * @arg RCC_APB1Periph_PWR: PWR clock
1901 * @arg RCC_APB1Periph_DAC: DAC clock
1902 * @arg RCC_APB1Periph_UART7: UART7 clock
1903 * @arg RCC_APB1Periph_UART8: UART8 clock
1904 * @param NewState: new state of the specified peripheral clock.
1905 * This parameter can be: ENABLE or DISABLE.
1906 * @retval None
1907 */
RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)1908 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1909 {
1910 /* Check the parameters */
1911 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1912 assert_param(IS_FUNCTIONAL_STATE(NewState));
1913
1914 if (NewState != DISABLE)
1915 {
1916 RCC->APB1ENR |= RCC_APB1Periph;
1917 }
1918 else
1919 {
1920 RCC->APB1ENR &= ~RCC_APB1Periph;
1921 }
1922 }
1923
1924 /**
1925 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
1926 * @note After reset, the peripheral clock (used for registers read/write access)
1927 * is disabled and the application software has to enable this clock before
1928 * using it.
1929 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
1930 * This parameter can be any combination of the following values:
1931 * @arg RCC_APB2Periph_TIM1: TIM1 clock
1932 * @arg RCC_APB2Periph_TIM8: TIM8 clock
1933 * @arg RCC_APB2Periph_USART1: USART1 clock
1934 * @arg RCC_APB2Periph_USART6: USART6 clock
1935 * @arg RCC_APB2Periph_ADC1: ADC1 clock
1936 * @arg RCC_APB2Periph_ADC2: ADC2 clock
1937 * @arg RCC_APB2Periph_ADC3: ADC3 clock
1938 * @arg RCC_APB2Periph_SDIO: SDIO clock
1939 * @arg RCC_APB2Periph_SPI1: SPI1 clock
1940 * @arg RCC_APB2Periph_SPI4: SPI4 clock
1941 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1942 * @arg RCC_APB2Periph_TIM9: TIM9 clock
1943 * @arg RCC_APB2Periph_TIM10: TIM10 clock
1944 * @arg RCC_APB2Periph_TIM11: TIM11 clock
1945 * @arg RCC_APB2Periph_SPI5: SPI5 clock
1946 * @arg RCC_APB2Periph_SPI6: SPI6 clock
1947 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
1948 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
1949 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
1950 * @param NewState: new state of the specified peripheral clock.
1951 * This parameter can be: ENABLE or DISABLE.
1952 * @retval None
1953 */
RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)1954 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1955 {
1956 /* Check the parameters */
1957 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1958 assert_param(IS_FUNCTIONAL_STATE(NewState));
1959
1960 if (NewState != DISABLE)
1961 {
1962 RCC->APB2ENR |= RCC_APB2Periph;
1963 }
1964 else
1965 {
1966 RCC->APB2ENR &= ~RCC_APB2Periph;
1967 }
1968 }
1969
1970 /**
1971 * @brief Forces or releases AHB1 peripheral reset.
1972 * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
1973 * This parameter can be any combination of the following values:
1974 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
1975 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
1976 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
1977 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
1978 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
1979 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
1980 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
1981 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
1982 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
1983 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
1984 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices)
1985 * @arg RCC_AHB1Periph_CRC: CRC clock
1986 * @arg RCC_AHB1Periph_DMA1: DMA1 clock
1987 * @arg RCC_AHB1Periph_DMA2: DMA2 clock
1988 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
1989 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
1990 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
1991 *
1992 * @param NewState: new state of the specified peripheral reset.
1993 * This parameter can be: ENABLE or DISABLE.
1994 * @retval None
1995 */
RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph,FunctionalState NewState)1996 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1997 {
1998 /* Check the parameters */
1999 assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
2000 assert_param(IS_FUNCTIONAL_STATE(NewState));
2001
2002 if (NewState != DISABLE)
2003 {
2004 RCC->AHB1RSTR |= RCC_AHB1Periph;
2005 }
2006 else
2007 {
2008 RCC->AHB1RSTR &= ~RCC_AHB1Periph;
2009 }
2010 }
2011
2012 /**
2013 * @brief Forces or releases AHB2 peripheral reset.
2014 * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
2015 * This parameter can be any combination of the following values:
2016 * @arg RCC_AHB2Periph_DCMI: DCMI clock
2017 * @arg RCC_AHB2Periph_CRYP: CRYP clock
2018 * @arg RCC_AHB2Periph_HASH: HASH clock
2019 * @arg RCC_AHB2Periph_RNG: RNG clock
2020 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
2021 * @param NewState: new state of the specified peripheral reset.
2022 * This parameter can be: ENABLE or DISABLE.
2023 * @retval None
2024 */
RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph,FunctionalState NewState)2025 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
2026 {
2027 /* Check the parameters */
2028 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
2029 assert_param(IS_FUNCTIONAL_STATE(NewState));
2030
2031 if (NewState != DISABLE)
2032 {
2033 RCC->AHB2RSTR |= RCC_AHB2Periph;
2034 }
2035 else
2036 {
2037 RCC->AHB2RSTR &= ~RCC_AHB2Periph;
2038 }
2039 }
2040
2041 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
2042 /**
2043 * @brief Forces or releases AHB3 peripheral reset.
2044 * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
2045 * This parameter must be:
2046 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
2047 * - RCC_AHB3Periph_QSPI (STM32F446xx devices)
2048 * @param NewState: new state of the specified peripheral reset.
2049 * This parameter can be: ENABLE or DISABLE.
2050 * @retval None
2051 */
RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph,FunctionalState NewState)2052 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
2053 {
2054 /* Check the parameters */
2055 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
2056 assert_param(IS_FUNCTIONAL_STATE(NewState));
2057
2058 if (NewState != DISABLE)
2059 {
2060 RCC->AHB3RSTR |= RCC_AHB3Periph;
2061 }
2062 else
2063 {
2064 RCC->AHB3RSTR &= ~RCC_AHB3Periph;
2065 }
2066 }
2067 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
2068
2069 /**
2070 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
2071 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
2072 * This parameter can be any combination of the following values:
2073 * @arg RCC_APB1Periph_TIM2: TIM2 clock
2074 * @arg RCC_APB1Periph_TIM3: TIM3 clock
2075 * @arg RCC_APB1Periph_TIM4: TIM4 clock
2076 * @arg RCC_APB1Periph_TIM5: TIM5 clock
2077 * @arg RCC_APB1Periph_TIM6: TIM6 clock
2078 * @arg RCC_APB1Periph_TIM7: TIM7 clock
2079 * @arg RCC_APB1Periph_TIM12: TIM12 clock
2080 * @arg RCC_APB1Periph_TIM13: TIM13 clock
2081 * @arg RCC_APB1Periph_TIM14: TIM14 clock
2082 * @arg RCC_APB1Periph_WWDG: WWDG clock
2083 * @arg RCC_APB1Periph_SPI2: SPI2 clock
2084 * @arg RCC_APB1Periph_SPI3: SPI3 clock
2085 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
2086 * @arg RCC_APB1Periph_USART2: USART2 clock
2087 * @arg RCC_APB1Periph_USART3: USART3 clock
2088 * @arg RCC_APB1Periph_UART4: UART4 clock
2089 * @arg RCC_APB1Periph_UART5: UART5 clock
2090 * @arg RCC_APB1Periph_I2C1: I2C1 clock
2091 * @arg RCC_APB1Periph_I2C2: I2C2 clock
2092 * @arg RCC_APB1Periph_I2C3: I2C3 clock
2093 * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
2094 * @arg RCC_APB1Periph_CAN1: CAN1 clock
2095 * @arg RCC_APB1Periph_CAN2: CAN2 clock
2096 * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
2097 * @arg RCC_APB1Periph_PWR: PWR clock
2098 * @arg RCC_APB1Periph_DAC: DAC clock
2099 * @arg RCC_APB1Periph_UART7: UART7 clock
2100 * @arg RCC_APB1Periph_UART8: UART8 clock
2101 * @param NewState: new state of the specified peripheral reset.
2102 * This parameter can be: ENABLE or DISABLE.
2103 * @retval None
2104 */
RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)2105 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
2106 {
2107 /* Check the parameters */
2108 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
2109 assert_param(IS_FUNCTIONAL_STATE(NewState));
2110 if (NewState != DISABLE)
2111 {
2112 RCC->APB1RSTR |= RCC_APB1Periph;
2113 }
2114 else
2115 {
2116 RCC->APB1RSTR &= ~RCC_APB1Periph;
2117 }
2118 }
2119
2120 /**
2121 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
2122 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
2123 * This parameter can be any combination of the following values:
2124 * @arg RCC_APB2Periph_TIM1: TIM1 clock
2125 * @arg RCC_APB2Periph_TIM8: TIM8 clock
2126 * @arg RCC_APB2Periph_USART1: USART1 clock
2127 * @arg RCC_APB2Periph_USART6: USART6 clock
2128 * @arg RCC_APB2Periph_ADC1: ADC1 clock
2129 * @arg RCC_APB2Periph_ADC2: ADC2 clock
2130 * @arg RCC_APB2Periph_ADC3: ADC3 clock
2131 * @arg RCC_APB2Periph_SDIO: SDIO clock
2132 * @arg RCC_APB2Periph_SPI1: SPI1 clock
2133 * @arg RCC_APB2Periph_SPI4: SPI4 clock
2134 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
2135 * @arg RCC_APB2Periph_TIM9: TIM9 clock
2136 * @arg RCC_APB2Periph_TIM10: TIM10 clock
2137 * @arg RCC_APB2Periph_TIM11: TIM11 clock
2138 * @arg RCC_APB2Periph_SPI5: SPI5 clock
2139 * @arg RCC_APB2Periph_SPI6: SPI6 clock
2140 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
2141 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
2142 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
2143 * @param NewState: new state of the specified peripheral reset.
2144 * This parameter can be: ENABLE or DISABLE.
2145 * @retval None
2146 */
RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)2147 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
2148 {
2149 /* Check the parameters */
2150 assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
2151 assert_param(IS_FUNCTIONAL_STATE(NewState));
2152 if (NewState != DISABLE)
2153 {
2154 RCC->APB2RSTR |= RCC_APB2Periph;
2155 }
2156 else
2157 {
2158 RCC->APB2RSTR &= ~RCC_APB2Periph;
2159 }
2160 }
2161
2162 /**
2163 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
2164 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2165 * power consumption.
2166 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2167 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2168 * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
2169 * This parameter can be any combination of the following values:
2170 * @arg RCC_AHB1Periph_GPIOA: GPIOA clock
2171 * @arg RCC_AHB1Periph_GPIOB: GPIOB clock
2172 * @arg RCC_AHB1Periph_GPIOC: GPIOC clock
2173 * @arg RCC_AHB1Periph_GPIOD: GPIOD clock
2174 * @arg RCC_AHB1Periph_GPIOE: GPIOE clock
2175 * @arg RCC_AHB1Periph_GPIOF: GPIOF clock
2176 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
2177 * @arg RCC_AHB1Periph_GPIOG: GPIOG clock
2178 * @arg RCC_AHB1Periph_GPIOI: GPIOI clock
2179 * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices)
2180 * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices)
2181 * @arg RCC_AHB1Periph_CRC: CRC clock
2182 * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
2183 * @arg RCC_AHB1Periph_DMA1: DMA1 clock
2184 * @arg RCC_AHB1Periph_DMA2: DMA2 clock
2185 * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
2186 * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
2187 * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock
2188 * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock
2189 * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
2190 * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
2191 * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
2192 * @param NewState: new state of the specified peripheral clock.
2193 * This parameter can be: ENABLE or DISABLE.
2194 * @retval None
2195 */
RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph,FunctionalState NewState)2196 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
2197 {
2198 /* Check the parameters */
2199 assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
2200 assert_param(IS_FUNCTIONAL_STATE(NewState));
2201 if (NewState != DISABLE)
2202 {
2203 RCC->AHB1LPENR |= RCC_AHB1Periph;
2204 }
2205 else
2206 {
2207 RCC->AHB1LPENR &= ~RCC_AHB1Periph;
2208 }
2209 }
2210
2211 /**
2212 * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
2213 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2214 * power consumption.
2215 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2216 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2217 * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
2218 * This parameter can be any combination of the following values:
2219 * @arg RCC_AHB2Periph_DCMI: DCMI clock
2220 * @arg RCC_AHB2Periph_CRYP: CRYP clock
2221 * @arg RCC_AHB2Periph_HASH: HASH clock
2222 * @arg RCC_AHB2Periph_RNG: RNG clock
2223 * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
2224 * @param NewState: new state of the specified peripheral clock.
2225 * This parameter can be: ENABLE or DISABLE.
2226 * @retval None
2227 */
RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph,FunctionalState NewState)2228 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
2229 {
2230 /* Check the parameters */
2231 assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
2232 assert_param(IS_FUNCTIONAL_STATE(NewState));
2233 if (NewState != DISABLE)
2234 {
2235 RCC->AHB2LPENR |= RCC_AHB2Periph;
2236 }
2237 else
2238 {
2239 RCC->AHB2LPENR &= ~RCC_AHB2Periph;
2240 }
2241 }
2242
2243 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
2244 /**
2245 * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
2246 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2247 * power consumption.
2248 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2249 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2250 * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
2251 * This parameter must be:
2252 * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
2253 * - RCC_AHB3Periph_QSPI (STM32F446xx devices)
2254 * @param NewState: new state of the specified peripheral clock.
2255 * This parameter can be: ENABLE or DISABLE.
2256 * @retval None
2257 */
RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph,FunctionalState NewState)2258 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
2259 {
2260 /* Check the parameters */
2261 assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
2262 assert_param(IS_FUNCTIONAL_STATE(NewState));
2263 if (NewState != DISABLE)
2264 {
2265 RCC->AHB3LPENR |= RCC_AHB3Periph;
2266 }
2267 else
2268 {
2269 RCC->AHB3LPENR &= ~RCC_AHB3Periph;
2270 }
2271 }
2272 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
2273
2274 /**
2275 * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
2276 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2277 * power consumption.
2278 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2279 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2280 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
2281 * This parameter can be any combination of the following values:
2282 * @arg RCC_APB1Periph_TIM2: TIM2 clock
2283 * @arg RCC_APB1Periph_TIM3: TIM3 clock
2284 * @arg RCC_APB1Periph_TIM4: TIM4 clock
2285 * @arg RCC_APB1Periph_TIM5: TIM5 clock
2286 * @arg RCC_APB1Periph_TIM6: TIM6 clock
2287 * @arg RCC_APB1Periph_TIM7: TIM7 clock
2288 * @arg RCC_APB1Periph_TIM12: TIM12 clock
2289 * @arg RCC_APB1Periph_TIM13: TIM13 clock
2290 * @arg RCC_APB1Periph_TIM14: TIM14 clock
2291 * @arg RCC_APB1Periph_WWDG: WWDG clock
2292 * @arg RCC_APB1Periph_SPI2: SPI2 clock
2293 * @arg RCC_APB1Periph_SPI3: SPI3 clock
2294 * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
2295 * @arg RCC_APB1Periph_USART2: USART2 clock
2296 * @arg RCC_APB1Periph_USART3: USART3 clock
2297 * @arg RCC_APB1Periph_UART4: UART4 clock
2298 * @arg RCC_APB1Periph_UART5: UART5 clock
2299 * @arg RCC_APB1Periph_I2C1: I2C1 clock
2300 * @arg RCC_APB1Periph_I2C2: I2C2 clock
2301 * @arg RCC_APB1Periph_I2C3: I2C3 clock
2302 * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
2303 * @arg RCC_APB1Periph_CAN1: CAN1 clock
2304 * @arg RCC_APB1Periph_CAN2: CAN2 clock
2305 * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
2306 * @arg RCC_APB1Periph_PWR: PWR clock
2307 * @arg RCC_APB1Periph_DAC: DAC clock
2308 * @arg RCC_APB1Periph_UART7: UART7 clock
2309 * @arg RCC_APB1Periph_UART8: UART8 clock
2310 * @param NewState: new state of the specified peripheral clock.
2311 * This parameter can be: ENABLE or DISABLE.
2312 * @retval None
2313 */
RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph,FunctionalState NewState)2314 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
2315 {
2316 /* Check the parameters */
2317 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
2318 assert_param(IS_FUNCTIONAL_STATE(NewState));
2319 if (NewState != DISABLE)
2320 {
2321 RCC->APB1LPENR |= RCC_APB1Periph;
2322 }
2323 else
2324 {
2325 RCC->APB1LPENR &= ~RCC_APB1Periph;
2326 }
2327 }
2328
2329 /**
2330 * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
2331 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2332 * power consumption.
2333 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2334 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2335 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
2336 * This parameter can be any combination of the following values:
2337 * @arg RCC_APB2Periph_TIM1: TIM1 clock
2338 * @arg RCC_APB2Periph_TIM8: TIM8 clock
2339 * @arg RCC_APB2Periph_USART1: USART1 clock
2340 * @arg RCC_APB2Periph_USART6: USART6 clock
2341 * @arg RCC_APB2Periph_ADC1: ADC1 clock
2342 * @arg RCC_APB2Periph_ADC2: ADC2 clock
2343 * @arg RCC_APB2Periph_ADC3: ADC3 clock
2344 * @arg RCC_APB2Periph_SDIO: SDIO clock
2345 * @arg RCC_APB2Periph_SPI1: SPI1 clock
2346 * @arg RCC_APB2Periph_SPI4: SPI4 clock
2347 * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
2348 * @arg RCC_APB2Periph_TIM9: TIM9 clock
2349 * @arg RCC_APB2Periph_TIM10: TIM10 clock
2350 * @arg RCC_APB2Periph_TIM11: TIM11 clock
2351 * @arg RCC_APB2Periph_SPI5: SPI5 clock
2352 * @arg RCC_APB2Periph_SPI6: SPI6 clock
2353 * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
2354 * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
2355 * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
2356 * @param NewState: new state of the specified peripheral clock.
2357 * This parameter can be: ENABLE or DISABLE.
2358 * @retval None
2359 */
RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph,FunctionalState NewState)2360 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
2361 {
2362 /* Check the parameters */
2363 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
2364 assert_param(IS_FUNCTIONAL_STATE(NewState));
2365 if (NewState != DISABLE)
2366 {
2367 RCC->APB2LPENR |= RCC_APB2Periph;
2368 }
2369 else
2370 {
2371 RCC->APB2LPENR &= ~RCC_APB2Periph;
2372 }
2373 }
2374
2375 /**
2376 * @brief Configures the External Low Speed oscillator mode (LSE mode).
2377 * @note This mode is only available for STM32F411xx/STM32F446xx devices.
2378 * @param Mode: specifies the LSE mode.
2379 * This parameter can be one of the following values:
2380 * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
2381 * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
2382 * @retval None
2383 */
RCC_LSEModeConfig(uint8_t RCC_Mode)2384 void RCC_LSEModeConfig(uint8_t RCC_Mode)
2385 {
2386 /* Check the parameters */
2387 assert_param(IS_RCC_LSE_MODE(RCC_Mode));
2388
2389 if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
2390 {
2391 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
2392 }
2393 else
2394 {
2395 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
2396 }
2397 }
2398
2399 #if defined(STM32F446xx)
2400 /**
2401 * @brief Configures the 48MHz clock Source.
2402 * @note This feature is only available for STM32F446xx devices.
2403 * @param RCC_ClockSource: specifies the 48MHz clock Source.
2404 * This parameter can be one of the following values:
2405 * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
2406 * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
2407 * @retval None
2408 */
RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)2409 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
2410 {
2411 /* Check the parameters */
2412 assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
2413
2414 if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
2415 {
2416 SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
2417 }
2418 else
2419 {
2420 CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
2421 }
2422 }
2423
2424 /**
2425 * @brief Configures the SDIO clock Source.
2426 * @note This feature is only available for STM32F446xx devices.
2427 * @param RCC_ClockSource: specifies the SDIO clock Source.
2428 * This parameter can be one of the following values:
2429 * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
2430 * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
2431 * @retval None
2432 */
RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)2433 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
2434 {
2435 /* Check the parameters */
2436 assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
2437
2438 if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
2439 {
2440 SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
2441 }
2442 else
2443 {
2444 CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
2445 }
2446 }
2447 #endif /* STM32F446xx */
2448
2449 #if defined(STM32F446xx)
2450 /**
2451 * @brief Enables or disables the AHB1 clock gating for the specified IPs.
2452 * @note This feature is only available for STM32F446xx devices.
2453 * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating.
2454 * This parameter can be any combination of the following values:
2455 * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
2456 * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock
2457 * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
2458 * @arg RCC_AHB1ClockGating_SPARE: Spare clock
2459 * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
2460 * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
2461 * @arg RCC_AHB1ClockGating_RCC: RCC clock
2462 * @param NewState: new state of the specified peripheral clock.
2463 * This parameter can be: ENABLE or DISABLE.
2464 * @retval None
2465 */
RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating,FunctionalState NewState)2466 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
2467 {
2468 /* Check the parameters */
2469 assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
2470
2471 assert_param(IS_FUNCTIONAL_STATE(NewState));
2472 if (NewState != DISABLE)
2473 {
2474 RCC->CKGATENR &= ~RCC_AHB1ClockGating;
2475 }
2476 else
2477 {
2478 RCC->CKGATENR |= RCC_AHB1ClockGating;
2479 }
2480 }
2481
2482 /**
2483 * @brief Configures the SPDIFRX clock Source.
2484 * @note This feature is only available for STM32F446xx devices.
2485 * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
2486 * This parameter can be one of the following values:
2487 * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
2488 * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
2489 * @retval None
2490 */
RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)2491 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
2492 {
2493 /* Check the parameters */
2494 assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
2495
2496 if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
2497 {
2498 SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
2499 }
2500 else
2501 {
2502 CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
2503 }
2504 }
2505
2506 /**
2507 * @brief Configures the CEC clock Source.
2508 * @note This feature is only available for STM32F446xx devices.
2509 * @param RCC_ClockSource: specifies the CEC clock Source.
2510 * This parameter can be one of the following values:
2511 * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
2512 * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
2513 * @retval None
2514 */
RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)2515 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
2516 {
2517 /* Check the parameters */
2518 assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
2519
2520 if(RCC_ClockSource == RCC_CECCLKSource_LSE)
2521 {
2522 SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
2523 }
2524 else
2525 {
2526 CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
2527 }
2528 }
2529
2530 /**
2531 * @brief Configures the FMPI2C1 clock Source.
2532 * @note This feature is only available for STM32F446xx devices.
2533 * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
2534 * This parameter can be one of the following values:
2535 * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
2536 * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
2537 * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
2538 * @retval None
2539 */
RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)2540 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
2541 {
2542 /* Check the parameters */
2543 assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
2544
2545 /* Clear FMPI2C1 clock source selection source bits */
2546 RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL;
2547 /* Set new FMPI2C1 clock source */
2548 RCC->DCKCFGR2 |= RCC_ClockSource;
2549 }
2550 #endif /* STM32F446xx */
2551 /**
2552 * @}
2553 */
2554
2555 /** @defgroup RCC_Group4 Interrupts and flags management functions
2556 * @brief Interrupts and flags management functions
2557 *
2558 @verbatim
2559 ===============================================================================
2560 ##### Interrupts and flags management functions #####
2561 ===============================================================================
2562
2563 @endverbatim
2564 * @{
2565 */
2566
2567 /**
2568 * @brief Enables or disables the specified RCC interrupts.
2569 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
2570 * This parameter can be any combination of the following values:
2571 * @arg RCC_IT_LSIRDY: LSI ready interrupt
2572 * @arg RCC_IT_LSERDY: LSE ready interrupt
2573 * @arg RCC_IT_HSIRDY: HSI ready interrupt
2574 * @arg RCC_IT_HSERDY: HSE ready interrupt
2575 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
2576 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
2577 * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
2578 * @param NewState: new state of the specified RCC interrupts.
2579 * This parameter can be: ENABLE or DISABLE.
2580 * @retval None
2581 */
RCC_ITConfig(uint8_t RCC_IT,FunctionalState NewState)2582 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
2583 {
2584 /* Check the parameters */
2585 assert_param(IS_RCC_IT(RCC_IT));
2586 assert_param(IS_FUNCTIONAL_STATE(NewState));
2587 if (NewState != DISABLE)
2588 {
2589 /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
2590 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
2591 }
2592 else
2593 {
2594 /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
2595 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
2596 }
2597 }
2598
2599 /**
2600 * @brief Checks whether the specified RCC flag is set or not.
2601 * @param RCC_FLAG: specifies the flag to check.
2602 * This parameter can be one of the following values:
2603 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
2604 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
2605 * @arg RCC_FLAG_PLLRDY: main PLL clock ready
2606 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
2607 * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices)
2608 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
2609 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
2610 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
2611 * @arg RCC_FLAG_PINRST: Pin reset
2612 * @arg RCC_FLAG_PORRST: POR/PDR reset
2613 * @arg RCC_FLAG_SFTRST: Software reset
2614 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
2615 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
2616 * @arg RCC_FLAG_LPWRRST: Low Power reset
2617 * @retval The new state of RCC_FLAG (SET or RESET).
2618 */
RCC_GetFlagStatus(uint8_t RCC_FLAG)2619 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
2620 {
2621 uint32_t tmp = 0;
2622 uint32_t statusreg = 0;
2623 FlagStatus bitstatus = RESET;
2624
2625 /* Check the parameters */
2626 assert_param(IS_RCC_FLAG(RCC_FLAG));
2627
2628 /* Get the RCC register index */
2629 tmp = RCC_FLAG >> 5;
2630 if (tmp == 1) /* The flag to check is in CR register */
2631 {
2632 statusreg = RCC->CR;
2633 }
2634 else if (tmp == 2) /* The flag to check is in BDCR register */
2635 {
2636 statusreg = RCC->BDCR;
2637 }
2638 else /* The flag to check is in CSR register */
2639 {
2640 statusreg = RCC->CSR;
2641 }
2642
2643 /* Get the flag position */
2644 tmp = RCC_FLAG & FLAG_MASK;
2645 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
2646 {
2647 bitstatus = SET;
2648 }
2649 else
2650 {
2651 bitstatus = RESET;
2652 }
2653 /* Return the flag status */
2654 return bitstatus;
2655 }
2656
2657 /**
2658 * @brief Clears the RCC reset flags.
2659 * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
2660 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
2661 * @param None
2662 * @retval None
2663 */
RCC_ClearFlag(void)2664 void RCC_ClearFlag(void)
2665 {
2666 /* Set RMVF bit to clear the reset flags */
2667 RCC->CSR |= RCC_CSR_RMVF;
2668 }
2669
2670 /**
2671 * @brief Checks whether the specified RCC interrupt has occurred or not.
2672 * @param RCC_IT: specifies the RCC interrupt source to check.
2673 * This parameter can be one of the following values:
2674 * @arg RCC_IT_LSIRDY: LSI ready interrupt
2675 * @arg RCC_IT_LSERDY: LSE ready interrupt
2676 * @arg RCC_IT_HSIRDY: HSI ready interrupt
2677 * @arg RCC_IT_HSERDY: HSE ready interrupt
2678 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
2679 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
2680 * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices)
2681 * @arg RCC_IT_CSS: Clock Security System interrupt
2682 * @retval The new state of RCC_IT (SET or RESET).
2683 */
RCC_GetITStatus(uint8_t RCC_IT)2684 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
2685 {
2686 ITStatus bitstatus = RESET;
2687
2688 /* Check the parameters */
2689 assert_param(IS_RCC_GET_IT(RCC_IT));
2690
2691 /* Check the status of the specified RCC interrupt */
2692 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
2693 {
2694 bitstatus = SET;
2695 }
2696 else
2697 {
2698 bitstatus = RESET;
2699 }
2700 /* Return the RCC_IT status */
2701 return bitstatus;
2702 }
2703
2704 /**
2705 * @brief Clears the RCC's interrupt pending bits.
2706 * @param RCC_IT: specifies the interrupt pending bit to clear.
2707 * This parameter can be any combination of the following values:
2708 * @arg RCC_IT_LSIRDY: LSI ready interrupt
2709 * @arg RCC_IT_LSERDY: LSE ready interrupt
2710 * @arg RCC_IT_HSIRDY: HSI ready interrupt
2711 * @arg RCC_IT_HSERDY: HSE ready interrupt
2712 * @arg RCC_IT_PLLRDY: main PLL ready interrupt
2713 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
2714 * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
2715 * @arg RCC_IT_CSS: Clock Security System interrupt
2716 * @retval None
2717 */
RCC_ClearITPendingBit(uint8_t RCC_IT)2718 void RCC_ClearITPendingBit(uint8_t RCC_IT)
2719 {
2720 /* Check the parameters */
2721 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
2722
2723 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
2724 pending bits */
2725 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
2726 }
2727
2728 /**
2729 * @}
2730 */
2731
2732 /**
2733 * @}
2734 */
2735
2736 /**
2737 * @}
2738 */
2739
2740 /**
2741 * @}
2742 */
2743
2744 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2745