1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_rcc.h 4 * @author MCD Application Team 5 * @version V1.5.1 6 * @date 22-May-2015 7 * @brief This file contains all the functions prototypes for the RCC firmware library. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 12 * 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 * You may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at: 16 * 17 * http://www.st.com/software_license_agreement_liberty_v2 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ****************************************************************************** 26 */ 27 28 /* Define to prevent recursive inclusion -------------------------------------*/ 29 #ifndef __STM32F4xx_RCC_H 30 #define __STM32F4xx_RCC_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes ------------------------------------------------------------------*/ 37 #include "stm32f4xx.h" 38 39 /** @addtogroup STM32F4xx_StdPeriph_Driver 40 * @{ 41 */ 42 43 /** @addtogroup RCC 44 * @{ 45 */ 46 47 /* Exported types ------------------------------------------------------------*/ 48 typedef struct 49 { 50 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ 51 uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ 52 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ 53 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ 54 }RCC_ClocksTypeDef; 55 56 /* Exported constants --------------------------------------------------------*/ 57 58 /** @defgroup RCC_Exported_Constants 59 * @{ 60 */ 61 62 /** @defgroup RCC_HSE_configuration 63 * @{ 64 */ 65 #define RCC_HSE_OFF ((uint8_t)0x00) 66 #define RCC_HSE_ON ((uint8_t)0x01) 67 #define RCC_HSE_Bypass ((uint8_t)0x05) 68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 69 ((HSE) == RCC_HSE_Bypass)) 70 /** 71 * @} 72 */ 73 74 /** @defgroup RCC_LSE_Dual_Mode_Selection 75 * @{ 76 */ 77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ 80 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 81 /** 82 * @} 83 */ 84 85 /** @defgroup RCC_PLLSAIDivR_Factor 86 * @{ 87 */ 88 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) 89 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) 90 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) 91 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) 92 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ 93 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ 94 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ 95 ((VALUE) == RCC_PLLSAIDivR_Div16)) 96 /** 97 * @} 98 */ 99 100 /** @defgroup RCC_PLL_Clock_Source 101 * @{ 102 */ 103 #define RCC_PLLSource_HSI ((uint32_t)0x00000000) 104 #define RCC_PLLSource_HSE ((uint32_t)0x00400000) 105 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ 106 ((SOURCE) == RCC_PLLSource_HSE)) 107 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) 108 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) 109 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 110 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) 111 #if defined(STM32F446xx) 112 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 113 #endif /* STM32F446xx */ 114 115 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) 116 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 117 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) 118 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 119 #if defined(STM32F446xx) 120 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 121 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) 122 #endif /* STM32F446xx */ 123 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) 124 #if defined(STM32F446xx) 125 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 126 #endif /* STM32F446xx */ 127 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 128 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 129 130 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 131 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 132 /** 133 * @} 134 */ 135 136 /** @defgroup RCC_System_Clock_Source 137 * @{ 138 */ 139 140 #if defined(STM32F446xx) 141 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 142 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 143 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) 144 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) 145 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 146 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 147 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ 148 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) 149 /* Add legacy definition */ 150 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK 151 #endif /* STM32F446xx */ 152 153 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 154 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 155 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 156 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 157 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 158 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 159 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 160 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 161 /** 162 * @} 163 */ 164 165 /** @defgroup RCC_AHB_Clock_Source 166 * @{ 167 */ 168 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 169 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 170 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 171 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 172 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 173 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 174 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 175 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 176 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 177 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 178 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 179 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 180 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 181 ((HCLK) == RCC_SYSCLK_Div512)) 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_APB1_APB2_Clock_Source 187 * @{ 188 */ 189 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 190 #define RCC_HCLK_Div2 ((uint32_t)0x00001000) 191 #define RCC_HCLK_Div4 ((uint32_t)0x00001400) 192 #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 193 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) 194 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 195 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 196 ((PCLK) == RCC_HCLK_Div16)) 197 /** 198 * @} 199 */ 200 201 /** @defgroup RCC_Interrupt_Source 202 * @{ 203 */ 204 #define RCC_IT_LSIRDY ((uint8_t)0x01) 205 #define RCC_IT_LSERDY ((uint8_t)0x02) 206 #define RCC_IT_HSIRDY ((uint8_t)0x04) 207 #define RCC_IT_HSERDY ((uint8_t)0x08) 208 #define RCC_IT_PLLRDY ((uint8_t)0x10) 209 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 210 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 211 #define RCC_IT_CSS ((uint8_t)0x80) 212 213 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 214 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 215 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 216 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 217 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) 218 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) 219 220 /** 221 * @} 222 */ 223 224 /** @defgroup RCC_LSE_Configuration 225 * @{ 226 */ 227 #define RCC_LSE_OFF ((uint8_t)0x00) 228 #define RCC_LSE_ON ((uint8_t)0x01) 229 #define RCC_LSE_Bypass ((uint8_t)0x04) 230 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 231 ((LSE) == RCC_LSE_Bypass)) 232 /** 233 * @} 234 */ 235 236 /** @defgroup RCC_RTC_Clock_Source 237 * @{ 238 */ 239 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 240 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 241 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) 242 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 243 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 244 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) 245 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 246 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) 247 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) 248 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) 249 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) 250 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) 251 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 252 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) 253 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) 254 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) 255 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 256 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) 257 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 258 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) 259 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) 260 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) 261 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 262 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 263 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 264 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) 265 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 266 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) 267 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) 268 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) 269 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) 270 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) 271 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 272 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 273 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ 274 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ 275 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ 276 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ 277 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 278 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 279 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ 280 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ 281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ 282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ 283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ 284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ 285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ 288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ 289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ 293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ 294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ 296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ 297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ 298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ 300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ 301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ 302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) 303 /** 304 * @} 305 */ 306 307 #if defined(STM32F446xx) 308 /** @defgroup RCC_I2S_Clock_Source 309 * @{ 310 */ 311 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) 312 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 313 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 314 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) 315 316 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ 317 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) 318 /** 319 * @} 320 */ 321 322 /** @defgroup RCC_I2S_APBBus 323 * @{ 324 */ 325 #define RCC_I2SBus_APB1 ((uint8_t)0x00) 326 #define RCC_I2SBus_APB2 ((uint8_t)0x01) 327 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) 328 /** 329 * @} 330 */ 331 332 /** @defgroup RCC_SAI_Clock_Source 333 * @{ 334 */ 335 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) 336 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 337 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 338 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) 339 340 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ 341 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) 342 /** 343 * @} 344 */ 345 346 /** @defgroup RCC_SAI_Instance 347 * @{ 348 */ 349 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00) 350 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01) 351 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) 352 /** 353 * @} 354 */ 355 #endif /* STM32F446xx */ 356 357 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 358 /** @defgroup RCC_I2S_Clock_Source 359 * @{ 360 */ 361 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) 362 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 363 364 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 365 /** 366 * @} 367 */ 368 369 /** @defgroup RCC_SAI_BlockA_Clock_Source 370 * @{ 371 */ 372 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) 373 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) 374 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) 375 376 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ 377 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ 378 ((SOURCE) == RCC_SAIACLKSource_Ext)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup RCC_SAI_BlockB_Clock_Source 384 * @{ 385 */ 386 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) 387 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) 388 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) 389 390 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ 391 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ 392 ((SOURCE) == RCC_SAIBCLKSource_Ext)) 393 /** 394 * @} 395 */ 396 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 397 398 /** @defgroup RCC_TIM_PRescaler_Selection 399 * @{ 400 */ 401 #define RCC_TIMPrescDesactivated ((uint8_t)0x00) 402 #define RCC_TIMPrescActivated ((uint8_t)0x01) 403 404 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) 405 /** 406 * @} 407 */ 408 409 #if defined(STM32F446xx) 410 /** @defgroup RCC_SDIO_Clock_Source_Selection 411 * @{ 412 */ 413 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) 414 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) 415 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ 416 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) 417 /** 418 * @} 419 */ 420 421 422 /** @defgroup RCC_48MHZ_Clock_Source_Selection 423 * @{ 424 */ 425 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) 426 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) 427 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ 428 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) 429 /** 430 * @} 431 */ 432 #endif /* STM32F446xx */ 433 434 #if defined(STM32F446xx) 435 /** @defgroup RCC_SPDIFRX_Clock_Source_Selection 436 * @{ 437 */ 438 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) 439 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) 440 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ 441 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) 442 /** 443 * @} 444 */ 445 446 /** @defgroup RCC_CEC_Clock_Source_Selection 447 * @{ 448 */ 449 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) 450 #define RCC_CECCLKSource_LSE ((uint8_t)0x01) 451 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ 452 ((CLKSOURCE) == RCC_CECCLKSource_LSE)) 453 /** 454 * @} 455 */ 456 457 /** @defgroup RCC_FMPI2C1_Clock_Source 458 * @{ 459 */ 460 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) 461 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 462 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 463 464 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ 465 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) 466 /** 467 * @} 468 */ 469 470 /** @defgroup RCC_AHB1_ClockGating 471 * @{ 472 */ 473 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) 474 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) 475 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) 476 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) 477 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) 478 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) 479 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) 480 481 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) 482 483 /** 484 * @} 485 */ 486 #endif /* STM32F446xx */ 487 488 /** @defgroup RCC_AHB1_Peripherals 489 * @{ 490 */ 491 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) 492 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 493 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) 494 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) 495 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) 496 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) 497 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) 498 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) 499 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 500 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) 501 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) 502 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 503 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) 504 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) 505 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) 506 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) 507 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) 508 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) 509 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) 510 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 511 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) 512 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) 513 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) 514 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) 515 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) 516 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) 517 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) 518 519 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) 520 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) 521 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) 522 523 /** 524 * @} 525 */ 526 527 /** @defgroup RCC_AHB2_Peripherals 528 * @{ 529 */ 530 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) 531 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) 532 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) 533 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) 534 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) 535 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) 536 /** 537 * @} 538 */ 539 540 /** @defgroup RCC_AHB3_Peripherals 541 * @{ 542 */ 543 #if defined(STM32F40_41xxx) 544 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 545 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 546 #endif /* STM32F40_41xxx */ 547 548 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) 549 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 550 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 551 #endif /* STM32F427_437xx || STM32F429_439xx */ 552 553 #if defined(STM32F446xx) 554 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 555 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 556 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 557 #endif /* STM32F446xx */ 558 559 /** 560 * @} 561 */ 562 563 /** @defgroup RCC_APB1_Peripherals 564 * @{ 565 */ 566 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 567 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 568 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 569 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 570 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 571 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 572 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 573 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 574 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 575 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 576 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 577 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 578 #if defined(STM32F446xx) 579 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) 580 #endif /* STM32F446xx */ 581 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 582 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 583 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 584 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 585 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 586 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 587 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) 588 #if defined(STM32F446xx) 589 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) 590 #endif /* STM32F446xx */ 591 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 592 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 593 #if defined(STM32F446xx) 594 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000) 595 #endif /* STM32F446xx */ 596 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 597 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 598 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) 599 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) 600 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) 601 /** 602 * @} 603 */ 604 605 /** @defgroup RCC_APB2_Peripherals 606 * @{ 607 */ 608 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 609 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 610 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) 611 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) 612 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 613 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 614 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) 615 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 616 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 617 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 618 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) 619 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 620 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) 621 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) 622 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) 623 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) 624 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) 625 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) 626 #if defined(STM32F446xx) 627 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) 628 #endif /* STM32F446xx */ 629 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) 630 631 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00)) 632 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00)) 633 634 /** 635 * @} 636 */ 637 638 /** @defgroup RCC_MCO1_Clock_Source_Prescaler 639 * @{ 640 */ 641 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) 642 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 643 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 644 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) 645 #define RCC_MCO1Div_1 ((uint32_t)0x00000000) 646 #define RCC_MCO1Div_2 ((uint32_t)0x04000000) 647 #define RCC_MCO1Div_3 ((uint32_t)0x05000000) 648 #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 649 #define RCC_MCO1Div_5 ((uint32_t)0x07000000) 650 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ 651 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 652 653 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ 654 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ 655 ((DIV) == RCC_MCO1Div_5)) 656 /** 657 * @} 658 */ 659 660 /** @defgroup RCC_MCO2_Clock_Source_Prescaler 661 * @{ 662 */ 663 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 664 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) 665 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) 666 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) 667 #define RCC_MCO2Div_1 ((uint32_t)0x00000000) 668 #define RCC_MCO2Div_2 ((uint32_t)0x20000000) 669 #define RCC_MCO2Div_3 ((uint32_t)0x28000000) 670 #define RCC_MCO2Div_4 ((uint32_t)0x30000000) 671 #define RCC_MCO2Div_5 ((uint32_t)0x38000000) 672 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 673 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) 674 675 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ 676 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 677 ((DIV) == RCC_MCO2Div_5)) 678 /** 679 * @} 680 */ 681 682 /** @defgroup RCC_Flag 683 * @{ 684 */ 685 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 686 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 687 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 688 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 689 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) 690 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 691 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 692 #define RCC_FLAG_BORRST ((uint8_t)0x79) 693 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 694 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 695 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 696 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 697 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 698 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 699 700 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 701 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 702 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 703 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 704 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 705 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 706 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) 707 708 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 709 /** 710 * @} 711 */ 712 713 /** 714 * @} 715 */ 716 717 /* Exported macro ------------------------------------------------------------*/ 718 /* Exported functions --------------------------------------------------------*/ 719 720 /* Function used to set the RCC clock configuration to the default reset state */ 721 void RCC_DeInit(void); 722 723 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 724 void RCC_HSEConfig(uint8_t RCC_HSE); 725 ErrorStatus RCC_WaitForHSEStartUp(void); 726 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 727 void RCC_HSICmd(FunctionalState NewState); 728 void RCC_LSEConfig(uint8_t RCC_LSE); 729 void RCC_LSICmd(FunctionalState NewState); 730 731 void RCC_PLLCmd(FunctionalState NewState); 732 #if defined(STM32F446xx) 733 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR); 734 #endif /* STM32F446xx */ 735 736 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 737 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); 738 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 739 740 void RCC_PLLI2SCmd(FunctionalState NewState); 741 #if defined(STM32F40_41xxx) || defined(STM32F401xx) 742 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); 743 #endif /* STM32F40_41xxx || STM32F401xx */ 744 #if defined(STM32F411xE) 745 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); 746 #endif /* STM32F411xE */ 747 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) 748 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); 749 #endif /* STM32F427_437xx || STM32F429_439xx */ 750 #if defined(STM32F446xx) 751 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR); 752 #endif /* STM32F446xx */ 753 754 void RCC_PLLSAICmd(FunctionalState NewState); 755 #if defined(STM32F446xx) 756 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ); 757 #endif /* STM32F446xx */ 758 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 759 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); 760 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 761 762 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 763 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); 764 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); 765 766 /* System, AHB and APB busses clocks configuration functions ******************/ 767 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 768 uint8_t RCC_GetSYSCLKSource(void); 769 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 770 void RCC_PCLK1Config(uint32_t RCC_HCLK); 771 void RCC_PCLK2Config(uint32_t RCC_HCLK); 772 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 773 774 /* Peripheral clocks configuration functions **********************************/ 775 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 776 void RCC_RTCCLKCmd(FunctionalState NewState); 777 void RCC_BackupResetCmd(FunctionalState NewState); 778 779 #if defined(STM32F446xx) 780 void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); 781 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); 782 #endif /* STM32F446xx */ 783 784 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 785 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 786 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); 787 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); 788 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ 789 790 void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); 791 void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); 792 793 void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); 794 void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); 795 796 void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 797 void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 798 void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 799 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 800 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 801 802 void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 803 void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 804 void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 805 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 806 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 807 808 void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); 809 void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); 810 void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); 811 void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 812 void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 813 814 /* Features available only for STM32F411xx/STM32F446xx devices */ 815 void RCC_LSEModeConfig(uint8_t RCC_Mode); 816 817 /* Features available only for STM32F446xx devices */ 818 #if defined(STM32F446xx) 819 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource); 820 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource); 821 #endif /* STM32F446xx */ 822 823 /* Features available only for STM32F446xx devices */ 824 #if defined(STM32F446xx) 825 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState); 826 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource); 827 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource); 828 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource); 829 #endif /* STM32F446xx */ 830 831 /* Interrupts and flags management functions **********************************/ 832 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 833 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 834 void RCC_ClearFlag(void); 835 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 836 void RCC_ClearITPendingBit(uint8_t RCC_IT); 837 838 #ifdef __cplusplus 839 } 840 #endif 841 842 #endif /* __STM32F4xx_RCC_H */ 843 844 /** 845 * @} 846 */ 847 848 /** 849 * @} 850 */ 851 852 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 853