1 /**
2 ******************************************************************************
3 * @file stm32f4xx_syscfg.c
4 * @author MCD Application Team
5 * @version V1.5.1
6 * @date 22-May-2015
7 * @brief This file provides firmware functions to manage the SYSCFG peripheral.
8 *
9 @verbatim
10
11 ===============================================================================
12 ##### How to use this driver #####
13 ===============================================================================
14 [..] This driver provides functions for:
15
16 (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
17
18 (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for
19 STM32F42xxx/43xxx devices Devices.
20
21 (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
22
23 (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
24
25 -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
26 using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
27
28 @endverbatim
29 ******************************************************************************
30 * @attention
31 *
32 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
33 *
34 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
35 * You may not use this file except in compliance with the License.
36 * You may obtain a copy of the License at:
37 *
38 * http://www.st.com/software_license_agreement_liberty_v2
39 *
40 * Unless required by applicable law or agreed to in writing, software
41 * distributed under the License is distributed on an "AS IS" BASIS,
42 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
43 * See the License for the specific language governing permissions and
44 * limitations under the License.
45 *
46 ******************************************************************************
47 */
48
49 /* Includes ------------------------------------------------------------------*/
50 #include "stm32f4xx_syscfg.h"
51 #include "stm32f4xx_rcc.h"
52
53 /** @addtogroup STM32F4xx_StdPeriph_Driver
54 * @{
55 */
56
57 /** @defgroup SYSCFG
58 * @brief SYSCFG driver modules
59 * @{
60 */
61
62 /* Private typedef -----------------------------------------------------------*/
63 /* Private define ------------------------------------------------------------*/
64 /* ------------ RCC registers bit address in the alias region ----------- */
65 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
66 /* --- MEMRMP Register ---*/
67 /* Alias word address of UFB_MODE bit */
68 #define MEMRMP_OFFSET SYSCFG_OFFSET
69 #define UFB_MODE_BitNumber ((uint8_t)0x8)
70 #define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
71
72
73 /* --- PMC Register ---*/
74 /* Alias word address of MII_RMII_SEL bit */
75 #define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
76 #define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
77 #define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
78
79 /* --- CMPCR Register ---*/
80 /* Alias word address of CMP_PD bit */
81 #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
82 #define CMP_PD_BitNumber ((uint8_t)0x00)
83 #define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
84
85 /* Private macro -------------------------------------------------------------*/
86 /* Private variables ---------------------------------------------------------*/
87 /* Private function prototypes -----------------------------------------------*/
88 /* Private functions ---------------------------------------------------------*/
89
90 /** @defgroup SYSCFG_Private_Functions
91 * @{
92 */
93
94 /**
95 * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
96 * registers to their default reset values.
97 * @param None
98 * @retval None
99 */
SYSCFG_DeInit(void)100 void SYSCFG_DeInit(void)
101 {
102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
103 RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
104 }
105
106 /**
107 * @brief Changes the mapping of the specified pin.
108 * @param SYSCFG_Memory: selects the memory remapping.
109 * This parameter can be one of the following values:
110 * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
111 * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
112 * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
113 * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
114 * @arg SYSCFG_MemoryRemap_ExtMEM: External Memory mapped at 0x00000000 for STM32F446xx devices.
115 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
116 * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
117 * @retval None
118 */
SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)119 void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
120 {
121 /* Check the parameters */
122 assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
123
124 SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
125 }
126
127 /**
128 * @brief Enables or disables the Internal FLASH Bank Swapping.
129 *
130 * @note This function can be used only for STM32F42xxx/43xxx devices.
131 *
132 * @param NewState: new state of Internal FLASH Bank swapping.
133 * This parameter can be one of the following values:
134 * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
135 * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
136 * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
137 and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
138 * @retval None
139 */
SYSCFG_MemorySwappingBank(FunctionalState NewState)140 void SYSCFG_MemorySwappingBank(FunctionalState NewState)
141 {
142 /* Check the parameters */
143 assert_param(IS_FUNCTIONAL_STATE(NewState));
144
145 *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState;
146 }
147
148 /**
149 * @brief Selects the GPIO pin used as EXTI Line.
150 * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
151 * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I)
152 * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H)
153 * for STM32401xx devices.
154 *
155 * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
156 * This parameter can be EXTI_PinSourcex where x can be (0..15, except
157 * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx
158 * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can
159 * be (0..7) for STM32F42xxx/43xxx devices.
160 *
161 * @retval None
162 */
SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx,uint8_t EXTI_PinSourcex)163 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
164 {
165 uint32_t tmp = 0x00;
166
167 /* Check the parameters */
168 assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
169 assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
170
171 tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
172 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
173 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
174 }
175
176 /**
177 * @brief Selects the ETHERNET media interface
178 * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
179 * This parameter can be one of the following values:
180 * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
181 * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
182 * @retval None
183 */
SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)184 void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
185 {
186 assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface));
187 /* Configure MII_RMII selection bit */
188 *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface;
189 }
190
191 /**
192 * @brief Enables or disables the I/O Compensation Cell.
193 * @note The I/O compensation cell can be used only when the device supply
194 * voltage ranges from 2.4 to 3.6 V.
195 * @param NewState: new state of the I/O Compensation Cell.
196 * This parameter can be one of the following values:
197 * @arg ENABLE: I/O compensation cell enabled
198 * @arg DISABLE: I/O compensation cell power-down mode
199 * @retval None
200 */
SYSCFG_CompensationCellCmd(FunctionalState NewState)201 void SYSCFG_CompensationCellCmd(FunctionalState NewState)
202 {
203 /* Check the parameters */
204 assert_param(IS_FUNCTIONAL_STATE(NewState));
205
206 *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
207 }
208
209 /**
210 * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
211 * @param None
212 * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
213 */
SYSCFG_GetCompensationCellStatus(void)214 FlagStatus SYSCFG_GetCompensationCellStatus(void)
215 {
216 FlagStatus bitstatus = RESET;
217
218 if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
219 {
220 bitstatus = SET;
221 }
222 else
223 {
224 bitstatus = RESET;
225 }
226 return bitstatus;
227 }
228
229 /**
230 * @}
231 */
232
233 /**
234 * @}
235 */
236
237 /**
238 * @}
239 */
240
241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
242