1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved 4 * 5 * STM32MP135C DISCO BOARD configuration 6 * 1x DDR3L 4Gb, 16-bit, 533MHz. 7 * Reference used MT41K256M16TW-107 P from Micron 8 * 9 * DDR type / Platform DDR3/3L 10 * freq 533MHz 11 * width 16 12 * datasheet 1 13 * DDR density 4 14 * timing mode optimized 15 * Scheduling/QoS options : type = 6 16 * address mapping : RBC 17 * Tc > + 85C : N 18 */ 19#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53" 20#define DDR_MEM_SPEED 533000 21#define DDR_MEM_SIZE 0x20000000 22 23#define DDR_MSTR 0x00040401 24#define DDR_MRCTRL0 0x00000010 25#define DDR_MRCTRL1 0x00000000 26#define DDR_DERATEEN 0x00000000 27#define DDR_DERATEINT 0x00800000 28#define DDR_PWRCTL 0x00000000 29#define DDR_PWRTMG 0x00400010 30#define DDR_HWLPCTL 0x00000000 31#define DDR_RFSHCTL0 0x00210000 32#define DDR_RFSHCTL3 0x00000000 33#define DDR_RFSHTMG 0x0081008B 34#define DDR_CRCPARCTL0 0x00000000 35#define DDR_DRAMTMG0 0x121B2414 36#define DDR_DRAMTMG1 0x000A041B 37#define DDR_DRAMTMG2 0x0607080F 38#define DDR_DRAMTMG3 0x0050400C 39#define DDR_DRAMTMG4 0x07040607 40#define DDR_DRAMTMG5 0x06060403 41#define DDR_DRAMTMG6 0x02020002 42#define DDR_DRAMTMG7 0x00000202 43#define DDR_DRAMTMG8 0x00001005 44#define DDR_DRAMTMG14 0x000000A0 45#define DDR_ZQCTL0 0xC2000040 46#define DDR_DFITMG0 0x02050105 47#define DDR_DFITMG1 0x00000202 48#define DDR_DFILPCFG0 0x07000000 49#define DDR_DFIUPD0 0xC0400003 50#define DDR_DFIUPD1 0x00000000 51#define DDR_DFIUPD2 0x00000000 52#define DDR_DFIPHYMSTR 0x00000000 53#define DDR_ADDRMAP1 0x00080808 54#define DDR_ADDRMAP2 0x00000000 55#define DDR_ADDRMAP3 0x00000000 56#define DDR_ADDRMAP4 0x00001F1F 57#define DDR_ADDRMAP5 0x07070707 58#define DDR_ADDRMAP6 0x0F070707 59#define DDR_ADDRMAP9 0x00000000 60#define DDR_ADDRMAP10 0x00000000 61#define DDR_ADDRMAP11 0x00000000 62#define DDR_ODTCFG 0x06000600 63#define DDR_ODTMAP 0x00000001 64#define DDR_SCHED 0x00000F01 65#define DDR_SCHED1 0x00000000 66#define DDR_PERFHPR1 0x00000001 67#define DDR_PERFLPR1 0x04000200 68#define DDR_PERFWR1 0x08000400 69#define DDR_DBG0 0x00000000 70#define DDR_DBG1 0x00000000 71#define DDR_DBGCMD 0x00000000 72#define DDR_POISONCFG 0x00000000 73#define DDR_PCCFG 0x00000010 74#define DDR_PCFGR_0 0x00000000 75#define DDR_PCFGW_0 0x00000000 76#define DDR_PCFGQOS0_0 0x00100009 77#define DDR_PCFGQOS1_0 0x00000020 78#define DDR_PCFGWQOS0_0 0x01100B03 79#define DDR_PCFGWQOS1_0 0x01000200 80#define DDR_PGCR 0x01442E02 81#define DDR_PTR0 0x0022AA5B 82#define DDR_PTR1 0x04841104 83#define DDR_PTR2 0x042DA068 84#define DDR_ACIOCR 0x10400812 85#define DDR_DXCCR 0x00000C40 86#define DDR_DSGCR 0xF200011F 87#define DDR_DCR 0x0000000B 88#define DDR_DTPR0 0x36D477D0 89#define DDR_DTPR1 0x098B00D8 90#define DDR_DTPR2 0x10023600 91#define DDR_MR0 0x00000830 92#define DDR_MR1 0x00000000 93#define DDR_MR2 0x00000208 94#define DDR_MR3 0x00000000 95#define DDR_ODTCR 0x00010000 96#define DDR_ZQ0CR1 0x00000038 97#define DDR_DX0GCR 0x0000CE81 98#define DDR_DX1GCR 0x0000CE81 99 100#include "stm32mp13-ddr.dtsi" 101