1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ 7 #define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ 8 9 /* PLL output is enable when x=1, with x=p,q or r */ 10 #define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) 11 12 /* st,clksrc: mandatory clock source */ 13 #define CLK_MPU_HSI 0x00000200 14 #define CLK_MPU_HSE 0x00000201 15 #define CLK_MPU_PLL1P 0x00000202 16 #define CLK_MPU_PLL1P_DIV 0x00000203 17 18 #define CLK_AXI_HSI 0x00000240 19 #define CLK_AXI_HSE 0x00000241 20 #define CLK_AXI_PLL2P 0x00000242 21 22 #define CLK_MCU_HSI 0x00000480 23 #define CLK_MCU_HSE 0x00000481 24 #define CLK_MCU_CSI 0x00000482 25 #define CLK_MCU_PLL3P 0x00000483 26 27 #define CLK_PLL12_HSI 0x00000280 28 #define CLK_PLL12_HSE 0x00000281 29 30 #define CLK_PLL3_HSI 0x00008200 31 #define CLK_PLL3_HSE 0x00008201 32 #define CLK_PLL3_CSI 0x00008202 33 34 #define CLK_PLL4_HSI 0x00008240 35 #define CLK_PLL4_HSE 0x00008241 36 #define CLK_PLL4_CSI 0x00008242 37 #define CLK_PLL4_I2SCKIN 0x00008243 38 39 #define CLK_RTC_DISABLED 0x00001400 40 #define CLK_RTC_LSE 0x00001401 41 #define CLK_RTC_LSI 0x00001402 42 #define CLK_RTC_HSE 0x00001403 43 44 #define CLK_MCO1_HSI 0x00008000 45 #define CLK_MCO1_HSE 0x00008001 46 #define CLK_MCO1_CSI 0x00008002 47 #define CLK_MCO1_LSI 0x00008003 48 #define CLK_MCO1_LSE 0x00008004 49 #define CLK_MCO1_DISABLED 0x0000800F 50 51 #define CLK_MCO2_MPU 0x00008040 52 #define CLK_MCO2_AXI 0x00008041 53 #define CLK_MCO2_MCU 0x00008042 54 #define CLK_MCO2_PLL4P 0x00008043 55 #define CLK_MCO2_HSE 0x00008044 56 #define CLK_MCO2_HSI 0x00008045 57 #define CLK_MCO2_DISABLED 0x0000804F 58 59 /* st,pkcs: peripheral kernel clock source */ 60 61 #define CLK_I2C12_PCLK1 0x00008C00 62 #define CLK_I2C12_PLL4R 0x00008C01 63 #define CLK_I2C12_HSI 0x00008C02 64 #define CLK_I2C12_CSI 0x00008C03 65 #define CLK_I2C12_DISABLED 0x00008C07 66 67 #define CLK_I2C35_PCLK1 0x00008C40 68 #define CLK_I2C35_PLL4R 0x00008C41 69 #define CLK_I2C35_HSI 0x00008C42 70 #define CLK_I2C35_CSI 0x00008C43 71 #define CLK_I2C35_DISABLED 0x00008C47 72 73 #define CLK_I2C46_PCLK5 0x00000C00 74 #define CLK_I2C46_PLL3Q 0x00000C01 75 #define CLK_I2C46_HSI 0x00000C02 76 #define CLK_I2C46_CSI 0x00000C03 77 #define CLK_I2C46_DISABLED 0x00000C07 78 79 #define CLK_SAI1_PLL4Q 0x00008C80 80 #define CLK_SAI1_PLL3Q 0x00008C81 81 #define CLK_SAI1_I2SCKIN 0x00008C82 82 #define CLK_SAI1_CKPER 0x00008C83 83 #define CLK_SAI1_PLL3R 0x00008C84 84 #define CLK_SAI1_DISABLED 0x00008C87 85 86 #define CLK_SAI2_PLL4Q 0x00008CC0 87 #define CLK_SAI2_PLL3Q 0x00008CC1 88 #define CLK_SAI2_I2SCKIN 0x00008CC2 89 #define CLK_SAI2_CKPER 0x00008CC3 90 #define CLK_SAI2_SPDIF 0x00008CC4 91 #define CLK_SAI2_PLL3R 0x00008CC5 92 #define CLK_SAI2_DISABLED 0x00008CC7 93 94 #define CLK_SAI3_PLL4Q 0x00008D00 95 #define CLK_SAI3_PLL3Q 0x00008D01 96 #define CLK_SAI3_I2SCKIN 0x00008D02 97 #define CLK_SAI3_CKPER 0x00008D03 98 #define CLK_SAI3_PLL3R 0x00008D04 99 #define CLK_SAI3_DISABLED 0x00008D07 100 101 #define CLK_SAI4_PLL4Q 0x00008D40 102 #define CLK_SAI4_PLL3Q 0x00008D41 103 #define CLK_SAI4_I2SCKIN 0x00008D42 104 #define CLK_SAI4_CKPER 0x00008D43 105 #define CLK_SAI4_PLL3R 0x00008D44 106 #define CLK_SAI4_DISABLED 0x00008D47 107 108 #define CLK_SPI2S1_PLL4P 0x00008D80 109 #define CLK_SPI2S1_PLL3Q 0x00008D81 110 #define CLK_SPI2S1_I2SCKIN 0x00008D82 111 #define CLK_SPI2S1_CKPER 0x00008D83 112 #define CLK_SPI2S1_PLL3R 0x00008D84 113 #define CLK_SPI2S1_DISABLED 0x00008D87 114 115 #define CLK_SPI2S23_PLL4P 0x00008DC0 116 #define CLK_SPI2S23_PLL3Q 0x00008DC1 117 #define CLK_SPI2S23_I2SCKIN 0x00008DC2 118 #define CLK_SPI2S23_CKPER 0x00008DC3 119 #define CLK_SPI2S23_PLL3R 0x00008DC4 120 #define CLK_SPI2S23_DISABLED 0x00008DC7 121 122 #define CLK_SPI45_PCLK2 0x00008E00 123 #define CLK_SPI45_PLL4Q 0x00008E01 124 #define CLK_SPI45_HSI 0x00008E02 125 #define CLK_SPI45_CSI 0x00008E03 126 #define CLK_SPI45_HSE 0x00008E04 127 #define CLK_SPI45_DISABLED 0x00008E07 128 129 #define CLK_SPI6_PCLK5 0x00000C40 130 #define CLK_SPI6_PLL4Q 0x00000C41 131 #define CLK_SPI6_HSI 0x00000C42 132 #define CLK_SPI6_CSI 0x00000C43 133 #define CLK_SPI6_HSE 0x00000C44 134 #define CLK_SPI6_PLL3Q 0x00000C45 135 #define CLK_SPI6_DISABLED 0x00000C47 136 137 #define CLK_UART6_PCLK2 0x00008E40 138 #define CLK_UART6_PLL4Q 0x00008E41 139 #define CLK_UART6_HSI 0x00008E42 140 #define CLK_UART6_CSI 0x00008E43 141 #define CLK_UART6_HSE 0x00008E44 142 #define CLK_UART6_DISABLED 0x00008E47 143 144 #define CLK_UART24_PCLK1 0x00008E80 145 #define CLK_UART24_PLL4Q 0x00008E81 146 #define CLK_UART24_HSI 0x00008E82 147 #define CLK_UART24_CSI 0x00008E83 148 #define CLK_UART24_HSE 0x00008E84 149 #define CLK_UART24_DISABLED 0x00008E87 150 151 #define CLK_UART35_PCLK1 0x00008EC0 152 #define CLK_UART35_PLL4Q 0x00008EC1 153 #define CLK_UART35_HSI 0x00008EC2 154 #define CLK_UART35_CSI 0x00008EC3 155 #define CLK_UART35_HSE 0x00008EC4 156 #define CLK_UART35_DISABLED 0x00008EC7 157 158 #define CLK_UART78_PCLK1 0x00008F00 159 #define CLK_UART78_PLL4Q 0x00008F01 160 #define CLK_UART78_HSI 0x00008F02 161 #define CLK_UART78_CSI 0x00008F03 162 #define CLK_UART78_HSE 0x00008F04 163 #define CLK_UART78_DISABLED 0x00008F07 164 165 #define CLK_UART1_PCLK5 0x00000C80 166 #define CLK_UART1_PLL3Q 0x00000C81 167 #define CLK_UART1_HSI 0x00000C82 168 #define CLK_UART1_CSI 0x00000C83 169 #define CLK_UART1_PLL4Q 0x00000C84 170 #define CLK_UART1_HSE 0x00000C85 171 #define CLK_UART1_DISABLED 0x00000C87 172 173 #define CLK_SDMMC12_HCLK6 0x00008F40 174 #define CLK_SDMMC12_PLL3R 0x00008F41 175 #define CLK_SDMMC12_PLL4P 0x00008F42 176 #define CLK_SDMMC12_HSI 0x00008F43 177 #define CLK_SDMMC12_DISABLED 0x00008F47 178 179 #define CLK_SDMMC3_HCLK2 0x00008F80 180 #define CLK_SDMMC3_PLL3R 0x00008F81 181 #define CLK_SDMMC3_PLL4P 0x00008F82 182 #define CLK_SDMMC3_HSI 0x00008F83 183 #define CLK_SDMMC3_DISABLED 0x00008F87 184 185 #define CLK_ETH_PLL4P 0x00008FC0 186 #define CLK_ETH_PLL3Q 0x00008FC1 187 #define CLK_ETH_DISABLED 0x00008FC3 188 189 #define CLK_QSPI_ACLK 0x00009000 190 #define CLK_QSPI_PLL3R 0x00009001 191 #define CLK_QSPI_PLL4P 0x00009002 192 #define CLK_QSPI_CKPER 0x00009003 193 194 #define CLK_FMC_ACLK 0x00009040 195 #define CLK_FMC_PLL3R 0x00009041 196 #define CLK_FMC_PLL4P 0x00009042 197 #define CLK_FMC_CKPER 0x00009043 198 199 #define CLK_FDCAN_HSE 0x000090C0 200 #define CLK_FDCAN_PLL3Q 0x000090C1 201 #define CLK_FDCAN_PLL4Q 0x000090C2 202 #define CLK_FDCAN_PLL4R 0x000090C3 203 204 #define CLK_SPDIF_PLL4P 0x00009140 205 #define CLK_SPDIF_PLL3Q 0x00009141 206 #define CLK_SPDIF_HSI 0x00009142 207 #define CLK_SPDIF_DISABLED 0x00009143 208 209 #define CLK_CEC_LSE 0x00009180 210 #define CLK_CEC_LSI 0x00009181 211 #define CLK_CEC_CSI_DIV122 0x00009182 212 #define CLK_CEC_DISABLED 0x00009183 213 214 #define CLK_USBPHY_HSE 0x000091C0 215 #define CLK_USBPHY_PLL4R 0x000091C1 216 #define CLK_USBPHY_HSE_DIV2 0x000091C2 217 #define CLK_USBPHY_DISABLED 0x000091C3 218 219 #define CLK_USBO_PLL4R 0x800091C0 220 #define CLK_USBO_USBPHY 0x800091C1 221 222 #define CLK_RNG1_CSI 0x00000CC0 223 #define CLK_RNG1_PLL4R 0x00000CC1 224 #define CLK_RNG1_LSE 0x00000CC2 225 #define CLK_RNG1_LSI 0x00000CC3 226 227 #define CLK_RNG2_CSI 0x00009200 228 #define CLK_RNG2_PLL4R 0x00009201 229 #define CLK_RNG2_LSE 0x00009202 230 #define CLK_RNG2_LSI 0x00009203 231 232 #define CLK_CKPER_HSI 0x00000D00 233 #define CLK_CKPER_CSI 0x00000D01 234 #define CLK_CKPER_HSE 0x00000D02 235 #define CLK_CKPER_DISABLED 0x00000D03 236 237 #define CLK_STGEN_HSI 0x00000D40 238 #define CLK_STGEN_HSE 0x00000D41 239 #define CLK_STGEN_DISABLED 0x00000D43 240 241 #define CLK_DSI_DSIPLL 0x00009240 242 #define CLK_DSI_PLL4P 0x00009241 243 244 #define CLK_ADC_PLL4R 0x00009280 245 #define CLK_ADC_CKPER 0x00009281 246 #define CLK_ADC_PLL3Q 0x00009282 247 #define CLK_ADC_DISABLED 0x00009283 248 249 #define CLK_LPTIM45_PCLK3 0x000092C0 250 #define CLK_LPTIM45_PLL4P 0x000092C1 251 #define CLK_LPTIM45_PLL3Q 0x000092C2 252 #define CLK_LPTIM45_LSE 0x000092C3 253 #define CLK_LPTIM45_LSI 0x000092C4 254 #define CLK_LPTIM45_CKPER 0x000092C5 255 #define CLK_LPTIM45_DISABLED 0x000092C7 256 257 #define CLK_LPTIM23_PCLK3 0x00009300 258 #define CLK_LPTIM23_PLL4Q 0x00009301 259 #define CLK_LPTIM23_CKPER 0x00009302 260 #define CLK_LPTIM23_LSE 0x00009303 261 #define CLK_LPTIM23_LSI 0x00009304 262 #define CLK_LPTIM23_DISABLED 0x00009307 263 264 #define CLK_LPTIM1_PCLK1 0x00009340 265 #define CLK_LPTIM1_PLL4P 0x00009341 266 #define CLK_LPTIM1_PLL3Q 0x00009342 267 #define CLK_LPTIM1_LSE 0x00009343 268 #define CLK_LPTIM1_LSI 0x00009344 269 #define CLK_LPTIM1_CKPER 0x00009345 270 #define CLK_LPTIM1_DISABLED 0x00009347 271 272 /* define for st,pll /csg */ 273 #define SSCG_MODE_CENTER_SPREAD 0 274 #define SSCG_MODE_DOWN_SPREAD 1 275 276 /* define for st,drive */ 277 #define LSEDRV_LOWEST 0 278 #define LSEDRV_MEDIUM_LOW 1 279 #define LSEDRV_MEDIUM_HIGH 2 280 #define LSEDRV_HIGHEST 3 281 282 #endif 283