1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22			nvmem-cells = <&part_number_otp>;
23			nvmem-cell-names = "part_number";
24		};
25	};
26
27	psci {
28		compatible = "arm,psci-1.0";
29		method = "smc";
30	};
31
32	intc: interrupt-controller@a0021000 {
33		compatible = "arm,cortex-a7-gic";
34		#interrupt-cells = <3>;
35		interrupt-controller;
36		reg = <0xa0021000 0x1000>,
37		      <0xa0022000 0x2000>;
38	};
39
40	clocks {
41		clk_hse: clk-hse {
42			#clock-cells = <0>;
43			compatible = "fixed-clock";
44			clock-frequency = <24000000>;
45		};
46
47		clk_hsi: clk-hsi {
48			#clock-cells = <0>;
49			compatible = "fixed-clock";
50			clock-frequency = <64000000>;
51		};
52
53		clk_lse: clk-lse {
54			#clock-cells = <0>;
55			compatible = "fixed-clock";
56			clock-frequency = <32768>;
57		};
58
59		clk_lsi: clk-lsi {
60			#clock-cells = <0>;
61			compatible = "fixed-clock";
62			clock-frequency = <32000>;
63		};
64
65		clk_csi: clk-csi {
66			#clock-cells = <0>;
67			compatible = "fixed-clock";
68			clock-frequency = <4000000>;
69		};
70	};
71
72	soc {
73		compatible = "simple-bus";
74		#address-cells = <1>;
75		#size-cells = <1>;
76		interrupt-parent = <&intc>;
77		ranges;
78
79		timers12: timer@40006000 {
80			#address-cells = <1>;
81			#size-cells = <0>;
82			compatible = "st,stm32-timers";
83			reg = <0x40006000 0x400>;
84			clocks = <&rcc TIM12_K>;
85			clock-names = "int";
86			status = "disabled";
87		};
88
89		usart2: serial@4000e000 {
90			compatible = "st,stm32h7-uart";
91			reg = <0x4000e000 0x400>;
92			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
93			clocks = <&rcc USART2_K>;
94			resets = <&rcc USART2_R>;
95			status = "disabled";
96		};
97
98		usart3: serial@4000f000 {
99			compatible = "st,stm32h7-uart";
100			reg = <0x4000f000 0x400>;
101			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
102			clocks = <&rcc USART3_K>;
103			resets = <&rcc USART3_R>;
104			status = "disabled";
105		};
106
107		uart4: serial@40010000 {
108			compatible = "st,stm32h7-uart";
109			reg = <0x40010000 0x400>;
110			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
111			clocks = <&rcc UART4_K>;
112			resets = <&rcc UART4_R>;
113			wakeup-source;
114			status = "disabled";
115		};
116
117		uart5: serial@40011000 {
118			compatible = "st,stm32h7-uart";
119			reg = <0x40011000 0x400>;
120			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
121			clocks = <&rcc UART5_K>;
122			resets = <&rcc UART5_R>;
123			status = "disabled";
124		};
125
126		i2c2: i2c@40013000 {
127			compatible = "st,stm32mp15-i2c";
128			reg = <0x40013000 0x400>;
129			interrupt-names = "event", "error";
130			interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
131				     <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
132			clocks = <&rcc I2C2_K>;
133			resets = <&rcc I2C2_R>;
134			#address-cells = <1>;
135			#size-cells = <0>;
136			st,syscfg-fmp = <&syscfg 0x4 0x2>;
137			wakeup-source;
138			status = "disabled";
139		};
140
141		uart7: serial@40018000 {
142			compatible = "st,stm32h7-uart";
143			reg = <0x40018000 0x400>;
144			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
145			clocks = <&rcc UART7_K>;
146			resets = <&rcc UART7_R>;
147			status = "disabled";
148		};
149
150		uart8: serial@40019000 {
151			compatible = "st,stm32h7-uart";
152			reg = <0x40019000 0x400>;
153			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
154			clocks = <&rcc UART8_K>;
155			resets = <&rcc UART8_R>;
156			status = "disabled";
157		};
158
159		usart6: serial@44003000 {
160			compatible = "st,stm32h7-uart";
161			reg = <0x44003000 0x400>;
162			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
163			clocks = <&rcc USART6_K>;
164			resets = <&rcc USART6_R>;
165			status = "disabled";
166		};
167
168		timers15: timer@44006000 {
169			#address-cells = <1>;
170			#size-cells = <0>;
171			compatible = "st,stm32-timers";
172			reg = <0x44006000 0x400>;
173			clocks = <&rcc TIM15_K>;
174			clock-names = "int";
175			status = "disabled";
176		};
177
178		usbotg_hs: usb-otg@49000000 {
179			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
180			reg = <0x49000000 0x10000>;
181			clocks = <&rcc USBO_K>;
182			clock-names = "otg";
183			resets = <&rcc USBO_R>;
184			reset-names = "dwc2";
185			interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
186			g-rx-fifo-size = <512>;
187			g-np-tx-fifo-size = <32>;
188			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
189			dr_mode = "otg";
190			usb33d-supply = <&usb33>;
191			status = "disabled";
192		};
193
194		rcc: rcc@50000000 {
195			compatible = "st,stm32mp1-rcc", "syscon";
196			reg = <0x50000000 0x1000>;
197			#address-cells = <1>;
198			#size-cells = <0>;
199			#clock-cells = <1>;
200			#reset-cells = <1>;
201			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
202			secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
203			secure-interrupt-names = "wakeup";
204		};
205
206		pwr_regulators: pwr@50001000 {
207			compatible = "st,stm32mp1,pwr-reg";
208			reg = <0x50001000 0x10>;
209			st,tzcr = <&rcc 0x0 0x1>;
210
211			reg11: reg11 {
212				regulator-name = "reg11";
213				regulator-min-microvolt = <1100000>;
214				regulator-max-microvolt = <1100000>;
215			};
216
217			reg18: reg18 {
218				regulator-name = "reg18";
219				regulator-min-microvolt = <1800000>;
220				regulator-max-microvolt = <1800000>;
221			};
222
223			usb33: usb33 {
224				regulator-name = "usb33";
225				regulator-min-microvolt = <3300000>;
226				regulator-max-microvolt = <3300000>;
227			};
228		};
229
230		pwr_mcu: pwr_mcu@50001014 {
231			compatible = "st,stm32mp151-pwr-mcu", "syscon";
232			reg = <0x50001014 0x4>;
233		};
234
235		pwr_irq: pwr@50001020 {
236			compatible = "st,stm32mp1-pwr";
237			reg = <0x50001020 0x100>;
238			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
239			interrupt-controller;
240			#interrupt-cells = <3>;
241		};
242
243		exti: interrupt-controller@5000d000 {
244			compatible = "st,stm32mp1-exti", "syscon";
245			interrupt-controller;
246			#interrupt-cells = <2>;
247			reg = <0x5000d000 0x400>;
248
249			/* exti_pwr is an extra interrupt controller used for
250			 * EXTI 55 to 60. It's mapped on pwr interrupt
251			 * controller.
252			 */
253			exti_pwr: exti-pwr {
254				interrupt-controller;
255				#interrupt-cells = <2>;
256				interrupt-parent = <&pwr_irq>;
257				st,irq-number = <6>;
258			};
259		};
260
261		syscfg: syscon@50020000 {
262			compatible = "st,stm32mp157-syscfg", "syscon";
263			reg = <0x50020000 0x400>;
264			clocks = <&rcc SYSCFG>;
265		};
266
267		hash1: hash@54002000 {
268			compatible = "st,stm32f756-hash";
269			reg = <0x54002000 0x400>;
270			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
271			clocks = <&rcc HASH1>;
272			resets = <&rcc HASH1_R>;
273			status = "disabled";
274		};
275
276		rng1: rng@54003000 {
277			compatible = "st,stm32-rng";
278			reg = <0x54003000 0x400>;
279			clocks = <&rcc RNG1_K>;
280			resets = <&rcc RNG1_R>;
281			status = "disabled";
282		};
283
284		fmc: memory-controller@58002000 {
285			#address-cells = <2>;
286			#size-cells = <1>;
287			compatible = "st,stm32mp1-fmc2-ebi";
288			reg = <0x58002000 0x1000>;
289			clocks = <&rcc FMC_K>;
290			resets = <&rcc FMC_R>;
291			status = "disabled";
292
293			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
294				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
295				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
296				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
297				 <4 0 0x80000000 0x10000000>; /* NAND */
298
299			nand-controller@4,0 {
300				#address-cells = <1>;
301				#size-cells = <0>;
302				compatible = "st,stm32mp1-fmc2-nfc";
303				reg = <4 0x00000000 0x1000>,
304				      <4 0x08010000 0x1000>,
305				      <4 0x08020000 0x1000>,
306				      <4 0x01000000 0x1000>,
307				      <4 0x09010000 0x1000>,
308				      <4 0x09020000 0x1000>;
309				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
310				status = "disabled";
311			};
312		};
313
314		qspi: spi@58003000 {
315			compatible = "st,stm32f469-qspi";
316			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
317			reg-names = "qspi", "qspi_mm";
318			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
319			clocks = <&rcc QSPI_K>;
320			resets = <&rcc QSPI_R>;
321			status = "disabled";
322		};
323
324		sdmmc1: mmc@58005000 {
325			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
326			arm,primecell-periphid = <0x00253180>;
327			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
328			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
329			interrupt-names = "cmd_irq";
330			clocks = <&rcc SDMMC1_K>;
331			clock-names = "apb_pclk";
332			resets = <&rcc SDMMC1_R>;
333			cap-sd-highspeed;
334			cap-mmc-highspeed;
335			max-frequency = <120000000>;
336			status = "disabled";
337		};
338
339		sdmmc2: mmc@58007000 {
340			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
341			arm,primecell-periphid = <0x00253180>;
342			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
343			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
344			interrupt-names = "cmd_irq";
345			clocks = <&rcc SDMMC2_K>;
346			clock-names = "apb_pclk";
347			resets = <&rcc SDMMC2_R>;
348			cap-sd-highspeed;
349			cap-mmc-highspeed;
350			max-frequency = <120000000>;
351			status = "disabled";
352		};
353
354		iwdg2: watchdog@5a002000 {
355			compatible = "st,stm32mp1-iwdg";
356			reg = <0x5a002000 0x400>;
357			secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
358			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
359			clock-names = "pclk", "lsi";
360			status = "disabled";
361		};
362
363		ddr: ddr@5a003000 {
364			compatible = "st,stm32mp1-ddr";
365			reg = <0x5A003000 0x550 0x5A004000 0x234>;
366			clocks = <&rcc AXIDCG>,
367				 <&rcc DDRC1>,
368				 <&rcc DDRC2>,
369				 <&rcc DDRPHYC>,
370				 <&rcc DDRCAPB>,
371				 <&rcc DDRPHYCAPB>;
372			clock-names = "axidcg",
373				      "ddrc1",
374				      "ddrc2",
375				      "ddrphyc",
376				      "ddrcapb",
377				      "ddrphycapb";
378			status = "okay";
379		};
380
381		usbphyc: usbphyc@5a006000 {
382			#address-cells = <1>;
383			#size-cells = <0>;
384			#clock-cells = <0>;
385			compatible = "st,stm32mp1-usbphyc";
386			reg = <0x5a006000 0x1000>;
387			clocks = <&rcc USBPHY_K>;
388			resets = <&rcc USBPHY_R>;
389			vdda1v1-supply = <&reg11>;
390			vdda1v8-supply = <&reg18>;
391			status = "disabled";
392
393			usbphyc_port0: usb-phy@0 {
394				#phy-cells = <0>;
395				reg = <0>;
396			};
397
398			usbphyc_port1: usb-phy@1 {
399				#phy-cells = <1>;
400				reg = <1>;
401			};
402		};
403
404		usart1: serial@5c000000 {
405			compatible = "st,stm32h7-uart";
406			reg = <0x5c000000 0x400>;
407			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
408			clocks = <&rcc USART1_K>;
409			resets = <&rcc USART1_R>;
410			status = "disabled";
411		};
412
413		spi6: spi@5c001000 {
414			#address-cells = <1>;
415			#size-cells = <0>;
416			compatible = "st,stm32h7-spi";
417			reg = <0x5c001000 0x400>;
418			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
419			clocks = <&rcc SPI6_K>;
420			resets = <&rcc SPI6_R>;
421			status = "disabled";
422		};
423
424		i2c4: i2c@5c002000 {
425			compatible = "st,stm32mp15-i2c";
426			reg = <0x5c002000 0x400>;
427			interrupt-names = "event", "error";
428			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
429					      <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
430			clocks = <&rcc I2C4_K>;
431			resets = <&rcc I2C4_R>;
432			#address-cells = <1>;
433			#size-cells = <0>;
434			st,syscfg-fmp = <&syscfg 0x4 0x8>;
435			wakeup-source;
436			status = "disabled";
437		};
438
439		iwdg1: watchdog@5c003000 {
440			compatible = "st,stm32mp1-iwdg";
441			reg = <0x5C003000 0x400>;
442			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
443			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
444			clock-names = "pclk", "lsi";
445			status = "disabled";
446		};
447
448		rtc: rtc@5c004000 {
449			compatible = "st,stm32mp1-rtc";
450			reg = <0x5c004000 0x400>;
451			clocks = <&rcc RTCAPB>, <&rcc RTC>;
452			clock-names = "pclk", "rtc_ck";
453			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
454			status = "disabled";
455		};
456
457		bsec: efuse@5c005000 {
458			compatible = "st,stm32mp15-bsec";
459			reg = <0x5c005000 0x400>;
460			#address-cells = <1>;
461			#size-cells = <1>;
462
463			cfg0_otp: cfg0_otp@0 {
464				reg = <0x0 0x1>;
465			};
466			part_number_otp: part_number_otp@4 {
467				reg = <0x4 0x1>;
468			};
469			monotonic_otp: monotonic_otp@10 {
470				reg = <0x10 0x4>;
471			};
472			nand_otp: nand_otp@24 {
473				reg = <0x24 0x4>;
474			};
475			uid_otp: uid_otp@34 {
476				reg = <0x34 0xc>;
477			};
478			package_otp: package_otp@40 {
479				reg = <0x40 0x4>;
480			};
481			hw2_otp: hw2_otp@48 {
482				reg = <0x48 0x4>;
483			};
484			ts_cal1: calib@5c {
485				reg = <0x5c 0x2>;
486			};
487			ts_cal2: calib@5e {
488				reg = <0x5e 0x2>;
489			};
490			pkh_otp: pkh_otp@60 {
491				reg = <0x60 0x20>;
492			};
493			mac_addr: mac_addr@e4 {
494				reg = <0xe4 0x8>;
495				st,non-secure-otp;
496			};
497		};
498
499		etzpc: etzpc@5c007000 {
500			compatible = "st,stm32-etzpc";
501			reg = <0x5C007000 0x400>;
502			clocks = <&rcc TZPC>;
503		};
504
505		stgen: stgen@5c008000 {
506			compatible = "st,stm32-stgen";
507			reg = <0x5C008000 0x1000>;
508		};
509
510		i2c6: i2c@5c009000 {
511			compatible = "st,stm32mp15-i2c";
512			reg = <0x5c009000 0x400>;
513			interrupt-names = "event", "error";
514			interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
515					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
516			clocks = <&rcc I2C6_K>;
517			resets = <&rcc I2C6_R>;
518			#address-cells = <1>;
519			#size-cells = <0>;
520			st,syscfg-fmp = <&syscfg 0x4 0x20>;
521			wakeup-source;
522			status = "disabled";
523		};
524
525		tamp: tamp@5c00a000 {
526			compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
527			reg = <0x5c00a000 0x400>;
528			secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
529			clocks = <&rcc RTCAPB>;
530		};
531
532		/*
533		 * Break node order to solve dependency probe issue between
534		 * pinctrl and exti.
535		 */
536		pinctrl: pinctrl@50002000 {
537			#address-cells = <1>;
538			#size-cells = <1>;
539			compatible = "st,stm32mp157-pinctrl";
540			ranges = <0 0x50002000 0xa400>;
541			interrupt-parent = <&exti>;
542			st,syscfg = <&exti 0x60 0xff>;
543			pins-are-numbered;
544
545			gpioa: gpio@50002000 {
546				gpio-controller;
547				#gpio-cells = <2>;
548				interrupt-controller;
549				#interrupt-cells = <2>;
550				reg = <0x0 0x400>;
551				clocks = <&rcc GPIOA>;
552				st,bank-name = "GPIOA";
553				status = "disabled";
554			};
555
556			gpiob: gpio@50003000 {
557				gpio-controller;
558				#gpio-cells = <2>;
559				interrupt-controller;
560				#interrupt-cells = <2>;
561				reg = <0x1000 0x400>;
562				clocks = <&rcc GPIOB>;
563				st,bank-name = "GPIOB";
564				status = "disabled";
565			};
566
567			gpioc: gpio@50004000 {
568				gpio-controller;
569				#gpio-cells = <2>;
570				interrupt-controller;
571				#interrupt-cells = <2>;
572				reg = <0x2000 0x400>;
573				clocks = <&rcc GPIOC>;
574				st,bank-name = "GPIOC";
575				status = "disabled";
576			};
577
578			gpiod: gpio@50005000 {
579				gpio-controller;
580				#gpio-cells = <2>;
581				interrupt-controller;
582				#interrupt-cells = <2>;
583				reg = <0x3000 0x400>;
584				clocks = <&rcc GPIOD>;
585				st,bank-name = "GPIOD";
586				status = "disabled";
587			};
588
589			gpioe: gpio@50006000 {
590				gpio-controller;
591				#gpio-cells = <2>;
592				interrupt-controller;
593				#interrupt-cells = <2>;
594				reg = <0x4000 0x400>;
595				clocks = <&rcc GPIOE>;
596				st,bank-name = "GPIOE";
597				status = "disabled";
598			};
599
600			gpiof: gpio@50007000 {
601				gpio-controller;
602				#gpio-cells = <2>;
603				interrupt-controller;
604				#interrupt-cells = <2>;
605				reg = <0x5000 0x400>;
606				clocks = <&rcc GPIOF>;
607				st,bank-name = "GPIOF";
608				status = "disabled";
609			};
610
611			gpiog: gpio@50008000 {
612				gpio-controller;
613				#gpio-cells = <2>;
614				interrupt-controller;
615				#interrupt-cells = <2>;
616				reg = <0x6000 0x400>;
617				clocks = <&rcc GPIOG>;
618				st,bank-name = "GPIOG";
619				status = "disabled";
620			};
621
622			gpioh: gpio@50009000 {
623				gpio-controller;
624				#gpio-cells = <2>;
625				interrupt-controller;
626				#interrupt-cells = <2>;
627				reg = <0x7000 0x400>;
628				clocks = <&rcc GPIOH>;
629				st,bank-name = "GPIOH";
630				status = "disabled";
631			};
632
633			gpioi: gpio@5000a000 {
634				gpio-controller;
635				#gpio-cells = <2>;
636				interrupt-controller;
637				#interrupt-cells = <2>;
638				reg = <0x8000 0x400>;
639				clocks = <&rcc GPIOI>;
640				st,bank-name = "GPIOI";
641				status = "disabled";
642			};
643
644			gpioj: gpio@5000b000 {
645				gpio-controller;
646				#gpio-cells = <2>;
647				interrupt-controller;
648				#interrupt-cells = <2>;
649				reg = <0x9000 0x400>;
650				clocks = <&rcc GPIOJ>;
651				st,bank-name = "GPIOJ";
652				status = "disabled";
653			};
654
655			gpiok: gpio@5000c000 {
656				gpio-controller;
657				#gpio-cells = <2>;
658				interrupt-controller;
659				#interrupt-cells = <2>;
660				reg = <0xa000 0x400>;
661				clocks = <&rcc GPIOK>;
662				st,bank-name = "GPIOK";
663				status = "disabled";
664			};
665		};
666
667		pinctrl_z: pinctrl@54004000 {
668			#address-cells = <1>;
669			#size-cells = <1>;
670			compatible = "st,stm32mp157-z-pinctrl";
671			ranges = <0 0x54004000 0x400>;
672			pins-are-numbered;
673			interrupt-parent = <&exti>;
674			st,syscfg = <&exti 0x60 0xff>;
675
676			gpioz: gpio@54004000 {
677				gpio-controller;
678				#gpio-cells = <2>;
679				interrupt-controller;
680				#interrupt-cells = <2>;
681				reg = <0 0x400>;
682				clocks = <&rcc GPIOZ>;
683				st,bank-name = "GPIOZ";
684				st,bank-ioport = <11>;
685				status = "disabled";
686			};
687		};
688	};
689};
690