1 /* 2 * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_FIP_DEF_H 8 #define STM32MP1_FIP_DEF_H 9 10 #if STM32MP15_OPTEE_RSV_SHM 11 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 12 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 13 #else 14 #define STM32MP_DDR_S_SIZE U(0x02000000) /* 32 MB */ 15 #define STM32MP_DDR_SHMEM_SIZE U(0) /* empty */ 16 #endif 17 18 #if TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP 19 #if STM32MP15 20 #define STM32MP_BL2_RO_SIZE U(0x00014000) /* 80 KB */ 21 #define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */ 22 #endif /* STM32MP15 */ 23 #else /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 24 #if STM32MP13 25 #if BL2_IN_XIP_MEM 26 #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ 27 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ 28 #else 29 /* STM32MP_BL2_RO_SIZE not used if !BL2_IN_XIP_MEM */ 30 #define STM32MP_BL2_SIZE U(0x0001B000) /* 108KB for BL2 */ 31 /* with 20KB for DTB, SYSRAM is full */ 32 #endif 33 #endif /* STM32MP13 */ 34 #if STM32MP15 35 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ 36 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ 37 #endif /* STM32MP15 */ 38 #endif /* TRUSTED_BOARD_BOOT && !STM32MP_USE_EXTERNAL_HEAP */ 39 40 #if STM32MP13 41 #if TRUSTED_BOARD_BOOT 42 #define STM32MP_BL2_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 43 #else /* TRUSTED_BOARD_BOOT */ 44 #define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ 45 #endif /* TRUSTED_BOARD_BOOT */ 46 #endif /* STM32MP13 */ 47 #if STM32MP15 48 #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ 49 #endif /* STM32MP15 */ 50 #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ 51 #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 52 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ 53 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ 54 55 #if STM32MP13 56 #define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ 57 STM32MP_BL2_DTB_SIZE) 58 #endif /* STM32MP13 */ 59 #if STM32MP15 60 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 61 STM32MP_SEC_SYSRAM_SIZE - \ 62 STM32MP_BL2_SIZE) 63 #endif /* STM32MP15 */ 64 65 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 66 67 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 68 STM32MP_BL2_RO_SIZE) 69 70 #if STM32MP13 71 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 72 STM32MP_SYSRAM_SIZE - \ 73 STM32MP_BL2_RW_BASE) 74 75 #define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE 76 #endif /* STM32MP13 */ 77 #if STM32MP15 78 #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ 79 STM32MP_SEC_SYSRAM_SIZE - \ 80 STM32MP_BL2_RW_BASE) 81 82 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 83 STM32MP_BL2_DTB_SIZE) 84 #endif /* STM32MP15 */ 85 86 #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE 87 88 #define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \ 89 STM32MP_BL32_DTB_SIZE) 90 91 92 #if defined(IMAGE_BL2) 93 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 94 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 95 #endif 96 #if defined(IMAGE_BL32) 97 #define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE 98 #define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE 99 #endif 100 101 #ifdef AARCH32_SP_OPTEE 102 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 103 104 #define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \ 105 STM32MP_OPTEE_BASE) 106 #endif 107 108 #if STM32MP13 109 #define STM32MP_FW_CONFIG_BASE SRAM3_BASE 110 #endif /* STM32MP13 */ 111 #if STM32MP15 112 #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ 113 STM32MP_SYSRAM_SIZE - \ 114 PAGE_SIZE) 115 #endif /* STM32MP15 */ 116 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 117 STM32MP_BL33_MAX_SIZE) 118 119 /* 120 * MAX_MMAP_REGIONS is usually: 121 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 122 */ 123 #if defined(IMAGE_BL32) 124 #define MAX_MMAP_REGIONS 10 125 #endif 126 127 /******************************************************************************* 128 * STM32MP1 RAW partition offset for devices without GPT 129 ******************************************************************************/ 130 #define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000) 131 #ifndef STM32MP_NOR_FIP_OFFSET 132 #define STM32MP_NOR_FIP_OFFSET U(0x00080000) 133 #endif 134 #ifndef STM32MP_NAND_FIP_OFFSET 135 #define STM32MP_NAND_FIP_OFFSET U(0x00200000) 136 #endif 137 138 #endif /* STM32MP1_FIP_DEF_H */ 139