1/*
2 * Copyright Linux Kernel Team
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * This file is derived from an intermediate build stage of the
7 * Linux kernel. The licenses of all input files to this process
8 * are compatible with GPL-2.0-only.
9 */
10
11/dts-v1/;
12
13/ {
14	model = "FVP_Base_AEMv8A-AEMv8A";
15	compatible = "arm,fvp-base,aemv8a-aemv8a", "arm,fvp-base";
16	interrupt-parent = <0x1>;
17	#address-cells = <0x2>;
18	#size-cells = <0x2>;
19
20	chosen {
21		stdout-path = "serial0:115200n8";
22		linux,initrd-start = <0x84000000>;
23		linux,initrd-end = <0x84000200>;
24	};
25
26	aliases {
27		serial0 = "/uart@1c090000";
28		serial1 = "/uart@1c0a0000";
29		serial2 = "/uart@1c0b0000";
30		serial3 = "/uart@1c0c0000";
31	};
32
33	psci {
34		compatible = "arm,psci-0.2";
35		method = "smc";
36	};
37
38	cpus {
39		#address-cells = <0x2>;
40		#size-cells = <0x0>;
41
42		cpu-map {
43
44			cluster0 {
45
46				core0 {
47					cpu = <0x2>;
48				};
49
50				core1 {
51					cpu = <0x3>;
52				};
53
54				core2 {
55					cpu = <0x4>;
56				};
57
58				core3 {
59					cpu = <0x5>;
60				};
61			};
62
63			cluster1 {
64
65				core0 {
66					cpu = <0x6>;
67				};
68
69				core1 {
70					cpu = <0x7>;
71				};
72
73				core2 {
74					cpu = <0x8>;
75				};
76
77				core3 {
78					cpu = <0x9>;
79				};
80			};
81		};
82
83		idle-states {
84			entry-method = "arm,psci";
85
86			cpu-sleep-0 {
87				compatible = "arm,idle-state";
88				arm,psci-suspend-param = <0x10000>;
89				local-timer-stop;
90				entry-latency-us = <0x12c>;
91				exit-latency-us = <0x4b0>;
92				min-residency-us = <0x7d0>;
93				phandle = <0xb>;
94			};
95
96			cluster-sleep-0 {
97				compatible = "arm,idle-state";
98				arm,psci-suspend-param = <0x1010000>;
99				local-timer-stop;
100				entry-latency-us = <0x190>;
101				exit-latency-us = <0x4b0>;
102				min-residency-us = <0x9c4>;
103				phandle = <0xc>;
104			};
105		};
106
107		cpu@0 {
108			compatible = "arm,armv8";
109			reg = <0x0 0x0>;
110			device_type = "cpu";
111			enable-method = "psci";
112			next-level-cache = <0xa>;
113			cpu-idle-states = <0xb 0xc>;
114			phandle = <0x2>;
115		};
116
117		cpu@1 {
118			compatible = "arm,armv8";
119			reg = <0x0 0x1>;
120			device_type = "cpu";
121			enable-method = "psci";
122			next-level-cache = <0xa>;
123			cpu-idle-states = <0xb 0xc>;
124			phandle = <0x3>;
125		};
126
127		cpu@2 {
128			compatible = "arm,armv8";
129			reg = <0x0 0x2>;
130			device_type = "cpu";
131			enable-method = "psci";
132			next-level-cache = <0xa>;
133			cpu-idle-states = <0xb 0xc>;
134			phandle = <0x4>;
135		};
136
137		cpu@3 {
138			compatible = "arm,armv8";
139			reg = <0x0 0x3>;
140			device_type = "cpu";
141			enable-method = "psci";
142			next-level-cache = <0xa>;
143			cpu-idle-states = <0xb 0xc>;
144			phandle = <0x5>;
145		};
146
147		cpu@100 {
148			compatible = "arm,armv8";
149			reg = <0x0 0x100>;
150			device_type = "cpu";
151			enable-method = "psci";
152			next-level-cache = <0xd>;
153			cpu-idle-states = <0xb 0xc>;
154			phandle = <0x6>;
155		};
156
157		cpu@101 {
158			compatible = "arm,armv8";
159			reg = <0x0 0x101>;
160			device_type = "cpu";
161			enable-method = "psci";
162			next-level-cache = <0xd>;
163			cpu-idle-states = <0xb 0xc>;
164			phandle = <0x7>;
165		};
166
167		cpu@102 {
168			compatible = "arm,armv8";
169			reg = <0x0 0x102>;
170			device_type = "cpu";
171			enable-method = "psci";
172			next-level-cache = <0xd>;
173			cpu-idle-states = <0xb 0xc>;
174			phandle = <0x8>;
175		};
176
177		cpu@103 {
178			compatible = "arm,armv8";
179			reg = <0x0 0x103>;
180			device_type = "cpu";
181			enable-method = "psci";
182			next-level-cache = <0xd>;
183			cpu-idle-states = <0xb 0xc>;
184			phandle = <0x9>;
185		};
186
187		l2-cache0 {
188			compatible = "cache";
189			phandle = <0xa>;
190		};
191
192		l2-cache1 {
193			compatible = "cache";
194			phandle = <0xd>;
195		};
196	};
197
198	timer {
199		compatible = "arm,armv8-timer";
200		interrupts = <0x1 0xd 0x8 0x1 0xe 0x8 0x1 0xb 0x8 0x1 0xa 0x8>;
201	};
202
203	pmu {
204		compatible = "arm,armv8-pmuv3";
205		interrupts = <0x0 0x3c 0x4 0x0 0x3d 0x4 0x0 0x3e 0x4 0x0 0x3f 0x4 0x0 0x40 0x4 0x0 0x41 0x4 0x0 0x42 0x4 0x0 0x43 0x4>;
206		interrupt-affinity = <0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9>;
207	};
208
209	interrupt-controller@2f000000 {
210		compatible = "arm,gic-v3";
211		#interrupt-cells = <0x3>;
212		#address-cells = <0x2>;
213		#size-cells = <0x2>;
214		ranges;
215		interrupt-controller;
216		reg = <0x0 0x2f000000 0x0 0x10000 0x0 0x2f100000 0x0 0x100000>;
217		interrupts = <0x1 0x9 0x4>;
218		phandle = <0x1>;
219	};
220
221	pci@40000000 {
222		#address-cells = <0x3>;
223		#size-cells = <0x2>;
224		#interrupt-cells = <0x1>;
225		compatible = "pci-host-ecam-generic";
226		device_type = "pci";
227		bus-range = <0x0 0x1>;
228		reg = <0x0 0x40000000 0x0 0x10000000>;
229		ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
230		interrupt-map = <0x0 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0xa8 0x4 0x0 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0xa9 0x4 0x0 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0xaa 0x4 0x0 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0xab 0x4>;
231		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
232		msi-parent = <0xe>;
233		msi-map = <0x0 0xe 0x0 0x10000>;
234		iommu-map = <0x0 0xf 0x0 0x10000>;
235		dma-coherent;
236		ats-supported;
237	};
238
239	smmu@2b400000 {
240		compatible = "arm,smmu-v3";
241		reg = <0x0 0x2b400000 0x0 0x20000>;
242		interrupts = <0x0 0x4a 0x1 0x0 0x4b 0x1 0x0 0x4d 0x1 0x0 0x4f 0x1>;
243		interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
244		dma-coherent;
245		#iommu-cells = <0x1>;
246		msi-parent = <0xe 0x10000>;
247		phandle = <0xf>;
248	};
249
250	clock35mhz {
251		compatible = "fixed-clock";
252		#clock-cells = <0x0>;
253		clock-frequency = <0x2160ec0>;
254		clock-output-names = "bp:clock35mhz";
255		phandle = <0x13>;
256	};
257
258	clock24mhz {
259		compatible = "fixed-clock";
260		#clock-cells = <0x0>;
261		clock-frequency = <0x16e3600>;
262		clock-output-names = "bp:clock24mhz";
263		phandle = <0x15>;
264	};
265
266	flash@8000000 {
267		compatible = "arm,vexpress-flash", "cfi-flash";
268		reg = <0x0 0x8000000 0x0 0x4000000 0x0 0xc000000 0x0 0x4000000>;
269		bank-width = <0x4>;
270	};
271
272	vram@18000000 {
273		compatible = "arm,vexpress-vram";
274		reg = <0x0 0x18000000 0x0 0x800000>;
275		phandle = <0x18>;
276	};
277
278	ethernet@1a000000 {
279		compatible = "smsc,lan91c111";
280		reg = <0x0 0x1a000000 0x0 0x10000>;
281		interrupts = <0x0 0xf 0x4>;
282	};
283
284	sysreg@1c010000 {
285		compatible = "arm,vexpress-sysreg";
286		reg = <0x0 0x1c010000 0x0 0x1000>;
287		gpio-controller;
288		#gpio-cells = <0x2>;
289		phandle = <0x10>;
290	};
291
292	mcc {
293		compatible = "arm,vexpress,config-bus";
294		arm,vexpress,config-bridge = <0x10>;
295
296		oscclk1 {
297			compatible = "arm,vexpress-osc";
298			arm,vexpress-sysreg,func = <0x1 0x1>;
299			freq-range = <0x16a6570 0x3c8eee0>;
300			#clock-cells = <0x0>;
301			clock-output-names = "bp:oscclk1";
302			phandle = <0x17>;
303		};
304
305		muxfpga {
306			compatible = "arm,vexpress-muxfpga";
307			arm,vexpress-sysreg,func = <0x7 0x0>;
308		};
309	};
310
311	sysctl-refclk {
312		compatible = "fixed-clock";
313		#clock-cells = <0x0>;
314		clock-frequency = <0xf4240>;
315		clock-output-names = "sysctl:refclk";
316		phandle = <0x11>;
317	};
318
319	sysctl-timclk {
320		compatible = "fixed-clock";
321		#clock-cells = <0x0>;
322		clock-frequency = <0x8000>;
323		clock-output-names = "sysctl:timclk";
324		phandle = <0x12>;
325	};
326
327	sysctl@1c020000 {
328		compatible = "arm,sp810", "arm,primecell";
329		reg = <0x0 0x1c020000 0x0 0x1000>;
330		clocks = <0x11 0x12 0x13>;
331		clock-names = "refclk", "timclk", "apb_pclk";
332		#clock-cells = <0x1>;
333		clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
334		assigned-clocks = <0x14 0x0 0x14 0x1 0x14 0x3 0x14 0x3>;
335		assigned-clock-parents = <0x12 0x12 0x12 0x12>;
336		phandle = <0x14>;
337	};
338
339	aaci@1c040000 {
340		compatible = "arm,pl041", "arm,primecell";
341		reg = <0x0 0x1c040000 0x0 0x1000>;
342		interrupts = <0x0 0xb 0x4>;
343		clocks = <0x15>;
344		clock-names = "apb_pclk";
345	};
346
347	bp-3v3 {
348		compatible = "regulator-fixed";
349		regulator-name = "3V3";
350		regulator-min-microvolt = <0x325aa0>;
351		regulator-max-microvolt = <0x325aa0>;
352		regulator-always-on;
353		phandle = <0x16>;
354	};
355
356	mmci@1c050000 {
357		compatible = "arm,pl180", "arm,primecell";
358		reg = <0x0 0x1c050000 0x0 0x1000>;
359		interrupts = <0x0 0x9 0x4 0x0 0xa 0x4>;
360		cd-gpios = <0x10 0x0 0x0>;
361		wp-gpios = <0x10 0x1 0x0>;
362		max-frequency = <0xb71b00>;
363		vmmc-supply = <0x16>;
364		clocks = <0x15 0x15>;
365		clock-names = "mclk", "apb_pclk";
366	};
367
368	kmi@1c060000 {
369		compatible = "arm,pl050", "arm,primecell";
370		reg = <0x0 0x1c060000 0x0 0x1000>;
371		interrupts = <0x0 0xc 0x4>;
372		clocks = <0x15 0x15>;
373		clock-names = "KMIREFCLK", "apb_pclk";
374	};
375
376	kmi@1c070000 {
377		compatible = "arm,pl050", "arm,primecell";
378		reg = <0x0 0x1c070000 0x0 0x1000>;
379		interrupts = <0x0 0xd 0x4>;
380		clocks = <0x15 0x15>;
381		clock-names = "KMIREFCLK", "apb_pclk";
382	};
383
384	uart@1c090000 {
385		compatible = "arm,pl011", "arm,primecell";
386		reg = <0x0 0x1c090000 0x0 0x1000>;
387		interrupts = <0x0 0x5 0x4>;
388		clocks = <0x15 0x15>;
389		clock-names = "uartclk", "apb_pclk";
390	};
391
392	uart@1c0a0000 {
393		compatible = "arm,pl011", "arm,primecell";
394		reg = <0x0 0x1c0a0000 0x0 0x1000>;
395		interrupts = <0x0 0x6 0x4>;
396		clocks = <0x15 0x15>;
397		clock-names = "uartclk", "apb_pclk";
398	};
399
400	uart@1c0b0000 {
401		compatible = "arm,pl011", "arm,primecell";
402		reg = <0x0 0x1c0b0000 0x0 0x1000>;
403		interrupts = <0x0 0x7 0x4>;
404		clocks = <0x15 0x15>;
405		clock-names = "uartclk", "apb_pclk";
406	};
407
408	uart@1c0c0000 {
409		compatible = "arm,pl011", "arm,primecell";
410		reg = <0x0 0x1c0c0000 0x0 0x1000>;
411		interrupts = <0x0 0x8 0x4>;
412		clocks = <0x15 0x15>;
413		clock-names = "uartclk", "apb_pclk";
414	};
415
416	wdt@1c0f0000 {
417		compatible = "arm,sp805", "arm,primecell";
418		reg = <0x0 0x1c0f0000 0x0 0x1000>;
419		interrupts = <0x0 0x0 0x4>;
420		clocks = <0x15 0x15>;
421		clock-names = "wdogclk", "apb_pclk";
422	};
423
424	timer@1c110000 {
425		compatible = "arm,sp804", "arm,primecell";
426		reg = <0x0 0x1c110000 0x0 0x1000>;
427		interrupts = <0x0 0x2 0x4>;
428		clocks = <0x14 0x0 0x14 0x1 0x13>;
429		clock-names = "timclken1", "timclken2", "apb_pclk";
430	};
431
432	timer@1c120000 {
433		compatible = "arm,sp804", "arm,primecell";
434		reg = <0x0 0x1c120000 0x0 0x1000>;
435		interrupts = <0x0 0x3 0x4>;
436		clocks = <0x14 0x2 0x14 0x3 0x13>;
437		clock-names = "timclken1", "timclken2", "apb_pclk";
438	};
439
440	virtio_block@1c0130000 {
441		compatible = "virtio,mmio";
442		reg = <0x0 0x1c130000 0x0 0x200>;
443		interrupts = <0x0 0x2a 0x4>;
444	};
445
446	rtc@1c170000 {
447		compatible = "arm,pl031", "arm,primecell";
448		reg = <0x0 0x1c170000 0x0 0x1000>;
449		interrupts = <0x0 0x4 0x4>;
450		clocks = <0x15>;
451		clock-names = "apb_pclk";
452	};
453
454	clcd@1c1f0000 {
455		compatible = "arm,pl111", "arm,primecell";
456		reg = <0x0 0x1c1f0000 0x0 0x1000>;
457		interrupt-names = "combined";
458		interrupts = <0x0 0xe 0x4>;
459		clocks = <0x17 0x15>;
460		clock-names = "clcdclk", "apb_pclk";
461		arm,pl11x,framebuffer = <0x18000000 0x180000>;
462		memory-region = <0x18>;
463		max-memory-bandwidth = <0x7bfa480>;
464
465		port {
466
467			endpoint {
468				remote-endpoint = <0x19>;
469				arm,pl11x,tft-r0g0b0-pads = <0x0 0x8 0x10>;
470				phandle = <0x1a>;
471			};
472		};
473
474		panel {
475			compatible = "panel-dpi";
476
477			port {
478
479				endpoint {
480					remote-endpoint = <0x1a>;
481					phandle = <0x19>;
482				};
483			};
484
485			panel-timing {
486				clock-frequency = <0x3c8ef5f>;
487				hactive = <0x400>;
488				hback-porch = <0x98>;
489				hfront-porch = <0x30>;
490				hsync-len = <0x68>;
491				vactive = <0x300>;
492				vback-porch = <0x17>;
493				vfront-porch = <0x3>;
494				vsync-len = <0x4>;
495			};
496		};
497	};
498
499	timer@2a810000 {
500		compatible = "arm,armv7-timer-mem";
501		reg = <0x0 0x2a810000 0x0 0x1000>;
502		clock-frequency = <0x2faf080>;
503		#address-cells = <0x2>;
504		#size-cells = <0x2>;
505		ranges;
506
507		frame@2a830000 {
508			frame-number = <0x1>;
509			interrupts = <0x0 0x1a 0x4>;
510			reg = <0x0 0x2a830000 0x0 0x1000>;
511		};
512	};
513
514	fake-hdlcd-clk {
515		compatible = "fixed-clock";
516		#clock-cells = <0x0>;
517		clock-frequency = <0x3c8eee0>;
518		clock-output-names = "pxlclk";
519		phandle = <0x1b>;
520	};
521
522	hdlcd@7ff60000 {
523		compatible = "arm,hdlcd";
524		reg = <0x0 0x7ff60000 0x0 0x1000>;
525		interrupts = <0x0 0x55 0x4>;
526		clocks = <0x1b>;
527		clock-names = "pxlclk";
528		status = "disabled";
529
530		port {
531
532			endpoint {
533				remote-endpoint = <0x1c>;
534				phandle = <0x1d>;
535			};
536		};
537	};
538
539	vencoder {
540		compatible = "drm,virtual-encoder";
541
542		port {
543
544			endpoint {
545				remote-endpoint = <0x1d>;
546				phandle = <0x1c>;
547			};
548		};
549
550		display-timings {
551
552			panel-timing {
553				clock-frequency = <0x3c8ef5f>;
554				hactive = <0x400>;
555				hback-porch = <0x98>;
556				hfront-porch = <0x30>;
557				hsync-len = <0x68>;
558				vactive = <0x300>;
559				vback-porch = <0x17>;
560				vfront-porch = <0x3>;
561				vsync-len = <0x4>;
562			};
563		};
564	};
565
566	memory@80000000 {
567		device_type = "memory";
568		reg = <0x0 0x80000000 0x0 0x80000000>;
569	};
570};
571