1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
10
11 #include <xen/console.h>
12 #include <xen/init.h>
13 #include <xen/irq.h>
14 #include <xen/sched.h>
15 #include <xen/timer.h>
16 #include <xen/serial.h>
17 #include <xen/iocap.h>
18 #ifdef CONFIG_HAS_PCI
19 #include <xen/pci.h>
20 #include <xen/pci_regs.h>
21 #include <xen/pci_ids.h>
22 #endif
23 #include <xen/8250-uart.h>
24 #include <xen/vmap.h>
25 #include <asm/io.h>
26 #ifdef CONFIG_HAS_DEVICE_TREE
27 #include <asm/device.h>
28 #endif
29 #ifdef CONFIG_X86
30 #include <asm/fixmap.h>
31 #endif
32
33 /*
34 * Configure serial port with a string:
35 * <baud>[/<base_baud>][,DPS[,<io-base>[,<irq>[,<port-bdf>[,<bridge-bdf>]]]]].
36 * The tail of the string can be omitted if platform defaults are sufficient.
37 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
38 * can be specified in place of a numeric baud rate. Polled mode is specified
39 * by requesting irq 0.
40 */
41 static char __initdata opt_com1[128] = "";
42 static char __initdata opt_com2[128] = "";
43 string_param("com1", opt_com1);
44 string_param("com2", opt_com2);
45
46 enum serial_param_type {
47 baud,
48 clock_hz,
49 data_bits,
50 io_base,
51 irq,
52 parity,
53 reg_shift,
54 reg_width,
55 stop_bits,
56 #ifdef CONFIG_HAS_PCI
57 bridge_bdf,
58 device,
59 port_bdf,
60 #endif
61 /* List all parameters before this line. */
62 num_serial_params
63 };
64
65 static struct ns16550 {
66 int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq;
67 u64 io_base; /* I/O port or memory-mapped I/O address. */
68 u64 io_size;
69 int reg_shift; /* Bits to shift register offset by */
70 int reg_width; /* Size of access to use, the registers
71 * themselves are still bytes */
72 char __iomem *remapped_io_base; /* Remapped virtual address of MMIO. */
73 /* UART with IRQ line: interrupt-driven I/O. */
74 struct irqaction irqaction;
75 u8 lsr_mask;
76 #ifdef CONFIG_ARM
77 struct vuart_info vuart;
78 #endif
79 /* UART with no IRQ line: periodically-polled I/O. */
80 struct timer timer;
81 struct timer resume_timer;
82 unsigned int timeout_ms;
83 bool_t intr_works;
84 bool_t dw_usr_bsy;
85 #ifdef CONFIG_HAS_PCI
86 /* PCI card parameters. */
87 bool_t pb_bdf_enable; /* if =1, pb-bdf effective, port behind bridge */
88 bool_t ps_bdf_enable; /* if =1, ps_bdf effective, port on pci card */
89 unsigned int pb_bdf[3]; /* pci bridge BDF */
90 unsigned int ps_bdf[3]; /* pci serial port BDF */
91 u32 bar;
92 u32 bar64;
93 u16 cr;
94 u8 bar_idx;
95 const struct ns16550_config_param *param; /* Points into .init.*! */
96 #endif
97 } ns16550_com[2] = { { 0 } };
98
99 struct serial_param_var {
100 char name[12];
101 enum serial_param_type type;
102 };
103
104 /*
105 * Enum struct keeping a table of all accepted parameter names for parsing
106 * com_console_options for serial port com1 and com2.
107 */
108 static const struct serial_param_var __initconst sp_vars[] = {
109 {"baud", baud},
110 {"clock-hz", clock_hz},
111 {"data-bits", data_bits},
112 {"io-base", io_base},
113 {"irq", irq},
114 {"parity", parity},
115 {"reg-shift", reg_shift},
116 {"reg-width", reg_width},
117 {"stop-bits", stop_bits},
118 #ifdef CONFIG_HAS_PCI
119 {"bridge", bridge_bdf},
120 {"dev", device},
121 {"port", port_bdf},
122 #endif
123 };
124
125 #ifdef CONFIG_HAS_PCI
126 struct ns16550_config {
127 u16 vendor_id;
128 u16 dev_id;
129 enum {
130 param_default, /* Must not be referenced by any table entry. */
131 param_trumanage,
132 param_oxford,
133 param_oxford_2port,
134 param_pericom_1port,
135 param_pericom_2port,
136 param_pericom_4port,
137 param_pericom_8port,
138 } param;
139 };
140
141 /* Defining uart config options for MMIO devices */
142 struct ns16550_config_param {
143 unsigned int reg_shift;
144 unsigned int reg_width;
145 unsigned int fifo_size;
146 u8 lsr_mask;
147 bool_t mmio;
148 bool_t bar0;
149 unsigned int max_ports;
150 unsigned int base_baud;
151 unsigned int uart_offset;
152 unsigned int first_offset;
153 };
154
155 /*
156 * Create lookup tables for specific devices. It is assumed that if
157 * the device found is MMIO, then you have indexed it here. Else, the
158 * driver does nothing for MMIO based devices.
159 */
160 static const struct ns16550_config_param __initconst uart_param[] = {
161 [param_default] = {
162 .reg_width = 1,
163 .lsr_mask = UART_LSR_THRE,
164 .max_ports = 1,
165 },
166 [param_trumanage] = {
167 .reg_shift = 2,
168 .reg_width = 1,
169 .fifo_size = 16,
170 .lsr_mask = (UART_LSR_THRE | UART_LSR_TEMT),
171 .mmio = 1,
172 .max_ports = 1,
173 },
174 [param_oxford] = {
175 .base_baud = 4000000,
176 .uart_offset = 0x200,
177 .first_offset = 0x1000,
178 .reg_width = 1,
179 .fifo_size = 16,
180 .lsr_mask = UART_LSR_THRE,
181 .mmio = 1,
182 .max_ports = 1, /* It can do more, but we would need more custom code.*/
183 },
184 [param_oxford_2port] = {
185 .base_baud = 4000000,
186 .uart_offset = 0x200,
187 .first_offset = 0x1000,
188 .reg_width = 1,
189 .fifo_size = 16,
190 .lsr_mask = UART_LSR_THRE,
191 .mmio = 1,
192 .max_ports = 2,
193 },
194 [param_pericom_1port] = {
195 .base_baud = 921600,
196 .uart_offset = 8,
197 .reg_width = 1,
198 .fifo_size = 16,
199 .lsr_mask = UART_LSR_THRE,
200 .bar0 = 1,
201 .max_ports = 1,
202 },
203 [param_pericom_2port] = {
204 .base_baud = 921600,
205 .uart_offset = 8,
206 .reg_width = 1,
207 .fifo_size = 16,
208 .lsr_mask = UART_LSR_THRE,
209 .bar0 = 1,
210 .max_ports = 2,
211 },
212 /*
213 * Of the two following ones, we can't really use all of their ports,
214 * unless ns16550_com[] would get grown.
215 */
216 [param_pericom_4port] = {
217 .base_baud = 921600,
218 .uart_offset = 8,
219 .reg_width = 1,
220 .fifo_size = 16,
221 .lsr_mask = UART_LSR_THRE,
222 .bar0 = 1,
223 .max_ports = 4,
224 },
225 [param_pericom_8port] = {
226 .base_baud = 921600,
227 .uart_offset = 8,
228 .reg_width = 1,
229 .fifo_size = 16,
230 .lsr_mask = UART_LSR_THRE,
231 .bar0 = 1,
232 .max_ports = 8,
233 }
234 };
235 static const struct ns16550_config __initconst uart_config[] =
236 {
237 /* Broadcom TruManage device */
238 {
239 .vendor_id = PCI_VENDOR_ID_BROADCOM,
240 .dev_id = 0x160a,
241 .param = param_trumanage,
242 },
243 /* OXPCIe952 1 Native UART */
244 {
245 .vendor_id = PCI_VENDOR_ID_OXSEMI,
246 .dev_id = 0xc11b,
247 .param = param_oxford,
248 },
249 /* OXPCIe952 1 Native UART */
250 {
251 .vendor_id = PCI_VENDOR_ID_OXSEMI,
252 .dev_id = 0xc11f,
253 .param = param_oxford,
254 },
255 /* OXPCIe952 1 Native UART */
256 {
257 .vendor_id = PCI_VENDOR_ID_OXSEMI,
258 .dev_id = 0xc138,
259 .param = param_oxford,
260 },
261 /* OXPCIe952 2 Native UART */
262 {
263 .vendor_id = PCI_VENDOR_ID_OXSEMI,
264 .dev_id = 0xc158,
265 .param = param_oxford_2port,
266 },
267 /* OXPCIe952 1 Native UART */
268 {
269 .vendor_id = PCI_VENDOR_ID_OXSEMI,
270 .dev_id = 0xc13d,
271 .param = param_oxford,
272 },
273 /* OXPCIe952 2 Native UART */
274 {
275 .vendor_id = PCI_VENDOR_ID_OXSEMI,
276 .dev_id = 0xc15d,
277 .param = param_oxford_2port,
278 },
279 /* OXPCIe952 1 Native UART */
280 {
281 .vendor_id = PCI_VENDOR_ID_OXSEMI,
282 .dev_id = 0xc40b,
283 .param = param_oxford,
284 },
285 /* OXPCIe200 1 Native UART */
286 {
287 .vendor_id = PCI_VENDOR_ID_OXSEMI,
288 .dev_id = 0xc40f,
289 .param = param_oxford,
290 },
291 /* OXPCIe200 1 Native UART */
292 {
293 .vendor_id = PCI_VENDOR_ID_OXSEMI,
294 .dev_id = 0xc41b,
295 .param = param_oxford,
296 },
297 /* OXPCIe200 1 Native UART */
298 {
299 .vendor_id = PCI_VENDOR_ID_OXSEMI,
300 .dev_id = 0xc41f,
301 .param = param_oxford,
302 },
303 /* OXPCIe200 1 Native UART */
304 {
305 .vendor_id = PCI_VENDOR_ID_OXSEMI,
306 .dev_id = 0xc42b,
307 .param = param_oxford,
308 },
309 /* OXPCIe200 1 Native UART */
310 {
311 .vendor_id = PCI_VENDOR_ID_OXSEMI,
312 .dev_id = 0xc42f,
313 .param = param_oxford,
314 },
315 /* OXPCIe200 1 Native UART */
316 {
317 .vendor_id = PCI_VENDOR_ID_OXSEMI,
318 .dev_id = 0xc43b,
319 .param = param_oxford,
320 },
321 /* OXPCIe200 1 Native UART */
322 {
323 .vendor_id = PCI_VENDOR_ID_OXSEMI,
324 .dev_id = 0xc43f,
325 .param = param_oxford,
326 },
327 /* OXPCIe200 1 Native UART */
328 {
329 .vendor_id = PCI_VENDOR_ID_OXSEMI,
330 .dev_id = 0xc44b,
331 .param = param_oxford,
332 },
333 /* OXPCIe200 1 Native UART */
334 {
335 .vendor_id = PCI_VENDOR_ID_OXSEMI,
336 .dev_id = 0xc44f,
337 .param = param_oxford,
338 },
339 /* OXPCIe200 1 Native UART */
340 {
341 .vendor_id = PCI_VENDOR_ID_OXSEMI,
342 .dev_id = 0xc45b,
343 .param = param_oxford,
344 },
345 /* OXPCIe200 1 Native UART */
346 {
347 .vendor_id = PCI_VENDOR_ID_OXSEMI,
348 .dev_id = 0xc45f,
349 .param = param_oxford,
350 },
351 /* OXPCIe200 1 Native UART */
352 {
353 .vendor_id = PCI_VENDOR_ID_OXSEMI,
354 .dev_id = 0xc46b,
355 .param = param_oxford,
356 },
357 /* OXPCIe200 1 Native UART */
358 {
359 .vendor_id = PCI_VENDOR_ID_OXSEMI,
360 .dev_id = 0xc46f,
361 .param = param_oxford,
362 },
363 /* OXPCIe200 1 Native UART */
364 {
365 .vendor_id = PCI_VENDOR_ID_OXSEMI,
366 .dev_id = 0xc47b,
367 .param = param_oxford,
368 },
369 /* OXPCIe200 1 Native UART */
370 {
371 .vendor_id = PCI_VENDOR_ID_OXSEMI,
372 .dev_id = 0xc47f,
373 .param = param_oxford,
374 },
375 /* OXPCIe200 1 Native UART */
376 {
377 .vendor_id = PCI_VENDOR_ID_OXSEMI,
378 .dev_id = 0xc48b,
379 .param = param_oxford,
380 },
381 /* OXPCIe200 1 Native UART */
382 {
383 .vendor_id = PCI_VENDOR_ID_OXSEMI,
384 .dev_id = 0xc48f,
385 .param = param_oxford,
386 },
387 /* OXPCIe200 1 Native UART */
388 {
389 .vendor_id = PCI_VENDOR_ID_OXSEMI,
390 .dev_id = 0xc49b,
391 .param = param_oxford,
392 },
393 /* OXPCIe200 1 Native UART */
394 {
395 .vendor_id = PCI_VENDOR_ID_OXSEMI,
396 .dev_id = 0xc49f,
397 .param = param_oxford,
398 },
399 /* OXPCIe200 1 Native UART */
400 {
401 .vendor_id = PCI_VENDOR_ID_OXSEMI,
402 .dev_id = 0xc4ab,
403 .param = param_oxford,
404 },
405 /* OXPCIe200 1 Native UART */
406 {
407 .vendor_id = PCI_VENDOR_ID_OXSEMI,
408 .dev_id = 0xc4af,
409 .param = param_oxford,
410 },
411 /* OXPCIe200 1 Native UART */
412 {
413 .vendor_id = PCI_VENDOR_ID_OXSEMI,
414 .dev_id = 0xc4bb,
415 .param = param_oxford,
416 },
417 /* OXPCIe200 1 Native UART */
418 {
419 .vendor_id = PCI_VENDOR_ID_OXSEMI,
420 .dev_id = 0xc4bf,
421 .param = param_oxford,
422 },
423 /* OXPCIe200 1 Native UART */
424 {
425 .vendor_id = PCI_VENDOR_ID_OXSEMI,
426 .dev_id = 0xc4cb,
427 .param = param_oxford,
428 },
429 /* OXPCIe200 1 Native UART */
430 {
431 .vendor_id = PCI_VENDOR_ID_OXSEMI,
432 .dev_id = 0xc4cf,
433 .param = param_oxford,
434 },
435 /* Pericom PI7C9X7951 Uno UART */
436 {
437 .vendor_id = PCI_VENDOR_ID_PERICOM,
438 .dev_id = 0x7951,
439 .param = param_pericom_1port
440 },
441 /* Pericom PI7C9X7952 Duo UART */
442 {
443 .vendor_id = PCI_VENDOR_ID_PERICOM,
444 .dev_id = 0x7952,
445 .param = param_pericom_2port
446 },
447 /* Pericom PI7C9X7954 Quad UART */
448 {
449 .vendor_id = PCI_VENDOR_ID_PERICOM,
450 .dev_id = 0x7954,
451 .param = param_pericom_4port
452 },
453 /* Pericom PI7C9X7958 Octal UART */
454 {
455 .vendor_id = PCI_VENDOR_ID_PERICOM,
456 .dev_id = 0x7958,
457 .param = param_pericom_8port
458 }
459 };
460 #endif
461
462 static void ns16550_delayed_resume(void *data);
463
ns_read_reg(struct ns16550 * uart,unsigned int reg)464 static u8 ns_read_reg(struct ns16550 *uart, unsigned int reg)
465 {
466 void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift);
467 #ifdef CONFIG_HAS_IOPORTS
468 if ( uart->remapped_io_base == NULL )
469 return inb(uart->io_base + reg);
470 #endif
471 switch ( uart->reg_width )
472 {
473 case 1:
474 return readb(addr);
475 case 4:
476 return readl(addr);
477 default:
478 return 0xff;
479 }
480 }
481
ns_write_reg(struct ns16550 * uart,unsigned int reg,u8 c)482 static void ns_write_reg(struct ns16550 *uart, unsigned int reg, u8 c)
483 {
484 void __iomem *addr = uart->remapped_io_base + (reg << uart->reg_shift);
485 #ifdef CONFIG_HAS_IOPORTS
486 if ( uart->remapped_io_base == NULL )
487 return outb(c, uart->io_base + reg);
488 #endif
489 switch ( uart->reg_width )
490 {
491 case 1:
492 writeb(c, addr);
493 break;
494 case 4:
495 writel(c, addr);
496 break;
497 default:
498 /* Ignored */
499 break;
500 }
501 }
502
ns16550_ioport_invalid(struct ns16550 * uart)503 static int ns16550_ioport_invalid(struct ns16550 *uart)
504 {
505 return ns_read_reg(uart, UART_IER) == 0xff;
506 }
507
handle_dw_usr_busy_quirk(struct ns16550 * uart)508 static void handle_dw_usr_busy_quirk(struct ns16550 *uart)
509 {
510 if ( uart->dw_usr_bsy &&
511 (ns_read_reg(uart, UART_IIR) & UART_IIR_BSY) == UART_IIR_BSY )
512 {
513 /* DesignWare 8250 detects if LCR is written while the UART is
514 * busy and raises a "busy detect" interrupt. Read the UART
515 * Status Register to clear this state.
516 *
517 * Allwinner/sunxi UART hardware is similar to DesignWare 8250
518 * and also contains a "busy detect" interrupt. So this quirk
519 * fix will also be used for Allwinner UART.
520 */
521 ns_read_reg(uart, UART_USR);
522 }
523 }
524
ns16550_interrupt(int irq,void * dev_id,struct cpu_user_regs * regs)525 static void ns16550_interrupt(
526 int irq, void *dev_id, struct cpu_user_regs *regs)
527 {
528 struct serial_port *port = dev_id;
529 struct ns16550 *uart = port->uart;
530
531 uart->intr_works = 1;
532
533 while ( !(ns_read_reg(uart, UART_IIR) & UART_IIR_NOINT) )
534 {
535 u8 lsr = ns_read_reg(uart, UART_LSR);
536
537 if ( (lsr & uart->lsr_mask) == uart->lsr_mask )
538 serial_tx_interrupt(port, regs);
539 if ( lsr & UART_LSR_DR )
540 serial_rx_interrupt(port, regs);
541
542 /* A "busy-detect" condition is observed on Allwinner/sunxi UART
543 * after LCR is written during setup. It needs to be cleared at
544 * this point or UART_IIR_NOINT will never be set and this loop
545 * will continue forever.
546 *
547 * This state can be cleared by calling the dw_usr_busy quirk
548 * handler that resolves "busy-detect" for DesignWare uart.
549 */
550 handle_dw_usr_busy_quirk(uart);
551 }
552 }
553
554 /* Safe: ns16550_poll() runs as softirq so not reentrant on a given CPU. */
555 static DEFINE_PER_CPU(struct serial_port *, poll_port);
556
__ns16550_poll(struct cpu_user_regs * regs)557 static void __ns16550_poll(struct cpu_user_regs *regs)
558 {
559 struct serial_port *port = this_cpu(poll_port);
560 struct ns16550 *uart = port->uart;
561
562 if ( uart->intr_works )
563 return; /* Interrupts work - no more polling */
564
565 while ( ns_read_reg(uart, UART_LSR) & UART_LSR_DR )
566 {
567 if ( ns16550_ioport_invalid(uart) )
568 goto out;
569
570 serial_rx_interrupt(port, regs);
571 }
572
573 if ( ( ns_read_reg(uart, UART_LSR) & uart->lsr_mask ) == uart->lsr_mask )
574 serial_tx_interrupt(port, regs);
575
576 out:
577 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
578 }
579
ns16550_poll(void * data)580 static void ns16550_poll(void *data)
581 {
582 this_cpu(poll_port) = data;
583 #ifdef run_in_exception_handler
584 run_in_exception_handler(__ns16550_poll);
585 #else
586 __ns16550_poll(guest_cpu_user_regs());
587 #endif
588 }
589
ns16550_tx_ready(struct serial_port * port)590 static int ns16550_tx_ready(struct serial_port *port)
591 {
592 struct ns16550 *uart = port->uart;
593
594 if ( ns16550_ioport_invalid(uart) )
595 return -EIO;
596
597 return ( (ns_read_reg(uart, UART_LSR) &
598 uart->lsr_mask ) == uart->lsr_mask ) ? uart->fifo_size : 0;
599 }
600
ns16550_putc(struct serial_port * port,char c)601 static void ns16550_putc(struct serial_port *port, char c)
602 {
603 struct ns16550 *uart = port->uart;
604 ns_write_reg(uart, UART_THR, c);
605 }
606
ns16550_getc(struct serial_port * port,char * pc)607 static int ns16550_getc(struct serial_port *port, char *pc)
608 {
609 struct ns16550 *uart = port->uart;
610
611 if ( ns16550_ioport_invalid(uart) ||
612 !(ns_read_reg(uart, UART_LSR) & UART_LSR_DR) )
613 return 0;
614
615 *pc = ns_read_reg(uart, UART_RBR);
616 return 1;
617 }
618
pci_serial_early_init(struct ns16550 * uart)619 static void pci_serial_early_init(struct ns16550 *uart)
620 {
621 #ifdef CONFIG_HAS_PCI
622 if ( !uart->ps_bdf_enable || uart->io_base >= 0x10000 )
623 return;
624
625 if ( uart->pb_bdf_enable )
626 pci_conf_write16(0, uart->pb_bdf[0], uart->pb_bdf[1], uart->pb_bdf[2],
627 PCI_IO_BASE,
628 (uart->io_base & 0xF000) |
629 ((uart->io_base & 0xF000) >> 8));
630
631 pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2],
632 PCI_BASE_ADDRESS_0,
633 uart->io_base | PCI_BASE_ADDRESS_SPACE_IO);
634 pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2],
635 PCI_COMMAND, PCI_COMMAND_IO);
636 #endif
637 }
638
ns16550_setup_preirq(struct ns16550 * uart)639 static void ns16550_setup_preirq(struct ns16550 *uart)
640 {
641 unsigned char lcr;
642 unsigned int divisor;
643
644 uart->intr_works = 0;
645
646 pci_serial_early_init(uart);
647
648 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
649
650 /* No interrupts. */
651 ns_write_reg(uart, UART_IER, 0);
652
653 /* Handle the DesignWare 8250 'busy-detect' quirk. */
654 handle_dw_usr_busy_quirk(uart);
655
656 /* Line control and baud-rate generator. */
657 ns_write_reg(uart, UART_LCR, lcr | UART_LCR_DLAB);
658 if ( uart->baud != BAUD_AUTO )
659 {
660 /* Baud rate specified: program it into the divisor latch. */
661 divisor = uart->clock_hz / (uart->baud << 4);
662 ns_write_reg(uart, UART_DLL, (char)divisor);
663 ns_write_reg(uart, UART_DLM, (char)(divisor >> 8));
664 }
665 else
666 {
667 /* Baud rate already set: read it out from the divisor latch. */
668 divisor = ns_read_reg(uart, UART_DLL);
669 divisor |= ns_read_reg(uart, UART_DLM) << 8;
670 if ( divisor )
671 uart->baud = uart->clock_hz / (divisor << 4);
672 else
673 printk(XENLOG_ERR
674 "Automatic baud rate determination was requested,"
675 " but a baud rate was not set up\n");
676 }
677 ns_write_reg(uart, UART_LCR, lcr);
678
679 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
680 ns_write_reg(uart, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
681
682 /* Enable and clear the FIFOs. Set a large trigger threshold. */
683 ns_write_reg(uart, UART_FCR,
684 UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX | UART_FCR_TRG14);
685 }
686
ns16550_init_preirq(struct serial_port * port)687 static void __init ns16550_init_preirq(struct serial_port *port)
688 {
689 struct ns16550 *uart = port->uart;
690
691 #ifdef CONFIG_HAS_IOPORTS
692 /* I/O ports are distinguished by their size (16 bits). */
693 if ( uart->io_base >= 0x10000 )
694 #endif
695 {
696 #ifdef CONFIG_X86
697 enum fixed_addresses idx = FIX_COM_BEGIN + (uart - ns16550_com);
698
699 set_fixmap_nocache(idx, uart->io_base);
700 uart->remapped_io_base = fix_to_virt(idx);
701 uart->remapped_io_base += uart->io_base & ~PAGE_MASK;
702 #else
703 uart->remapped_io_base = (char *)ioremap(uart->io_base, uart->io_size);
704 #endif
705 }
706
707 ns16550_setup_preirq(uart);
708
709 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
710 if ( ((ns_read_reg(uart, UART_IIR) & 0xc0) == 0xc0) &&
711 ((ns_read_reg(uart, UART_FCR) & UART_FCR_TRG14) == UART_FCR_TRG14) )
712 uart->fifo_size = 16;
713 }
714
ns16550_setup_postirq(struct ns16550 * uart)715 static void ns16550_setup_postirq(struct ns16550 *uart)
716 {
717 if ( uart->irq > 0 )
718 {
719 /* Master interrupt enable; also keep DTR/RTS asserted. */
720 ns_write_reg(uart,
721 UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
722
723 /* Enable receive interrupts. */
724 ns_write_reg(uart, UART_IER, UART_IER_ERDAI);
725 }
726
727 if ( uart->irq >= 0 )
728 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
729 }
730
ns16550_init_postirq(struct serial_port * port)731 static void __init ns16550_init_postirq(struct serial_port *port)
732 {
733 struct ns16550 *uart = port->uart;
734 int rc, bits;
735
736 if ( uart->irq < 0 )
737 return;
738
739 serial_async_transmit(port);
740
741 init_timer(&uart->timer, ns16550_poll, port, 0);
742 init_timer(&uart->resume_timer, ns16550_delayed_resume, port, 0);
743
744 /* Calculate time to fill RX FIFO and/or empty TX FIFO for polling. */
745 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
746 uart->timeout_ms = max_t(
747 unsigned int, 1, (bits * uart->fifo_size * 1000) / uart->baud);
748
749 if ( uart->irq > 0 )
750 {
751 uart->irqaction.handler = ns16550_interrupt;
752 uart->irqaction.name = "ns16550";
753 uart->irqaction.dev_id = port;
754 if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 )
755 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
756 }
757
758 ns16550_setup_postirq(uart);
759
760 #ifdef CONFIG_HAS_PCI
761 if ( uart->bar || uart->ps_bdf_enable )
762 {
763 if ( !uart->param )
764 pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1],
765 uart->ps_bdf[2]));
766 else
767 {
768 if ( uart->param->mmio &&
769 rangeset_add_range(mmio_ro_ranges,
770 uart->io_base,
771 uart->io_base + uart->io_size - 1) )
772 printk(XENLOG_INFO "Error while adding MMIO range of device to mmio_ro_ranges\n");
773
774 if ( pci_ro_device(0, uart->ps_bdf[0],
775 PCI_DEVFN(uart->ps_bdf[1], uart->ps_bdf[2])) )
776 printk(XENLOG_INFO "Could not mark config space of %02x:%02x.%u read-only.\n",
777 uart->ps_bdf[0], uart->ps_bdf[1],
778 uart->ps_bdf[2]);
779 }
780 }
781 #endif
782 }
783
ns16550_suspend(struct serial_port * port)784 static void ns16550_suspend(struct serial_port *port)
785 {
786 struct ns16550 *uart = port->uart;
787
788 stop_timer(&uart->timer);
789
790 #ifdef CONFIG_HAS_PCI
791 if ( uart->bar )
792 uart->cr = pci_conf_read16(0, uart->ps_bdf[0], uart->ps_bdf[1],
793 uart->ps_bdf[2], PCI_COMMAND);
794 #endif
795 }
796
_ns16550_resume(struct serial_port * port)797 static void _ns16550_resume(struct serial_port *port)
798 {
799 #ifdef CONFIG_HAS_PCI
800 struct ns16550 *uart = port->uart;
801
802 if ( uart->bar )
803 {
804 pci_conf_write32(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2],
805 PCI_BASE_ADDRESS_0 + uart->bar_idx*4, uart->bar);
806
807 /* If 64 bit BAR, write higher 32 bits to BAR+4 */
808 if ( uart->bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
809 pci_conf_write32(0, uart->ps_bdf[0],
810 uart->ps_bdf[1], uart->ps_bdf[2],
811 PCI_BASE_ADDRESS_0 + (uart->bar_idx+1)*4, uart->bar64);
812
813 pci_conf_write16(0, uart->ps_bdf[0], uart->ps_bdf[1], uart->ps_bdf[2],
814 PCI_COMMAND, uart->cr);
815 }
816 #endif
817
818 ns16550_setup_preirq(port->uart);
819 ns16550_setup_postirq(port->uart);
820 }
821
822 static int delayed_resume_tries;
ns16550_delayed_resume(void * data)823 static void ns16550_delayed_resume(void *data)
824 {
825 struct serial_port *port = data;
826 struct ns16550 *uart = port->uart;
827
828 if ( ns16550_ioport_invalid(port->uart) && delayed_resume_tries-- )
829 set_timer(&uart->resume_timer, NOW() + RESUME_DELAY);
830 else
831 _ns16550_resume(port);
832 }
833
ns16550_resume(struct serial_port * port)834 static void ns16550_resume(struct serial_port *port)
835 {
836 struct ns16550 *uart = port->uart;
837
838 /*
839 * Check for ioport access, before fully resuming operation.
840 * On some systems, there is a SuperIO card that provides
841 * this legacy ioport on the LPC bus.
842 *
843 * We need to wait for dom0's ACPI processing to run the proper
844 * AML to re-initialize the chip, before we can use the card again.
845 *
846 * This may cause a small amount of garbage to be written
847 * to the serial log while we wait patiently for that AML to
848 * be executed. However, this is preferable to spinning in an
849 * infinite loop, as seen on a Lenovo T430, when serial was enabled.
850 */
851 if ( ns16550_ioport_invalid(uart) )
852 {
853 delayed_resume_tries = RESUME_RETRIES;
854 set_timer(&uart->resume_timer, NOW() + RESUME_DELAY);
855 }
856 else
857 _ns16550_resume(port);
858 }
859
ns16550_endboot(struct serial_port * port)860 static void __init ns16550_endboot(struct serial_port *port)
861 {
862 #ifdef CONFIG_HAS_IOPORTS
863 struct ns16550 *uart = port->uart;
864 int rv;
865
866 if ( uart->remapped_io_base )
867 return;
868 rv = ioports_deny_access(hardware_domain, uart->io_base, uart->io_base + 7);
869 if ( rv != 0 )
870 BUG();
871 #endif
872 }
873
ns16550_irq(struct serial_port * port)874 static int __init ns16550_irq(struct serial_port *port)
875 {
876 struct ns16550 *uart = port->uart;
877 return ((uart->irq > 0) ? uart->irq : -1);
878 }
879
ns16550_start_tx(struct serial_port * port)880 static void ns16550_start_tx(struct serial_port *port)
881 {
882 struct ns16550 *uart = port->uart;
883 u8 ier = ns_read_reg(uart, UART_IER);
884
885 /* Unmask transmit holding register empty interrupt if currently masked. */
886 if ( !(ier & UART_IER_ETHREI) )
887 ns_write_reg(uart, UART_IER, ier | UART_IER_ETHREI);
888 }
889
ns16550_stop_tx(struct serial_port * port)890 static void ns16550_stop_tx(struct serial_port *port)
891 {
892 struct ns16550 *uart = port->uart;
893 u8 ier = ns_read_reg(uart, UART_IER);
894
895 /* Mask off transmit holding register empty interrupt if currently unmasked. */
896 if ( ier & UART_IER_ETHREI )
897 ns_write_reg(uart, UART_IER, ier & ~UART_IER_ETHREI);
898 }
899
900 #ifdef CONFIG_ARM
ns16550_vuart_info(struct serial_port * port)901 static const struct vuart_info *ns16550_vuart_info(struct serial_port *port)
902 {
903 struct ns16550 *uart = port->uart;
904
905 return &uart->vuart;
906 }
907 #endif
908
909 static struct uart_driver __read_mostly ns16550_driver = {
910 .init_preirq = ns16550_init_preirq,
911 .init_postirq = ns16550_init_postirq,
912 .endboot = ns16550_endboot,
913 .suspend = ns16550_suspend,
914 .resume = ns16550_resume,
915 .tx_ready = ns16550_tx_ready,
916 .putc = ns16550_putc,
917 .getc = ns16550_getc,
918 .irq = ns16550_irq,
919 .start_tx = ns16550_start_tx,
920 .stop_tx = ns16550_stop_tx,
921 #ifdef CONFIG_ARM
922 .vuart_info = ns16550_vuart_info,
923 #endif
924 };
925
parse_parity_char(int c)926 static int __init parse_parity_char(int c)
927 {
928 switch ( c )
929 {
930 case 'n':
931 return UART_PARITY_NONE;
932 case 'o':
933 return UART_PARITY_ODD;
934 case 'e':
935 return UART_PARITY_EVEN;
936 case 'm':
937 return UART_PARITY_MARK;
938 case 's':
939 return UART_PARITY_SPACE;
940 }
941 return 0;
942 }
943
check_existence(struct ns16550 * uart)944 static int __init check_existence(struct ns16550 *uart)
945 {
946 unsigned char status, scratch, scratch2, scratch3;
947
948 #ifdef CONFIG_HAS_IOPORTS
949 /*
950 * We can't poke MMIO UARTs until they get I/O remapped later. Assume that
951 * if we're getting MMIO UARTs, the arch code knows what it's doing.
952 */
953 if ( uart->io_base >= 0x10000 )
954 return 1;
955 #else
956 return 1; /* Everything is MMIO */
957 #endif
958
959 #ifdef CONFIG_HAS_PCI
960 pci_serial_early_init(uart);
961 #endif
962
963 /*
964 * Do a simple existence test first; if we fail this,
965 * there's no point trying anything else.
966 */
967 scratch = ns_read_reg(uart, UART_IER);
968 ns_write_reg(uart, UART_IER, 0);
969
970 /*
971 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
972 * 16C754B) allow only to modify them if an EFR bit is set.
973 */
974 scratch2 = ns_read_reg(uart, UART_IER) & 0x0f;
975 ns_write_reg(uart,UART_IER, 0x0F);
976 scratch3 = ns_read_reg(uart, UART_IER) & 0x0f;
977 ns_write_reg(uart, UART_IER, scratch);
978 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
979 return 0;
980
981 /*
982 * Check to see if a UART is really there.
983 * Use loopback test mode.
984 */
985 ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A);
986 status = ns_read_reg(uart, UART_MSR) & 0xF0;
987 return (status == 0x90);
988 }
989
990 #ifdef CONFIG_HAS_PCI
991 static int __init
pci_uart_config(struct ns16550 * uart,bool_t skip_amt,unsigned int idx)992 pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
993 {
994 u64 orig_base = uart->io_base;
995 unsigned int b, d, f, nextf, i;
996
997 /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */
998 for ( b = skip_amt ? 1 : 0; b < 0x100; b++ )
999 {
1000 for ( d = 0; d < 0x20; d++ )
1001 {
1002 for ( f = 0; f < 8; f = nextf )
1003 {
1004 unsigned int bar_idx = 0, port_idx = idx;
1005 uint32_t bar, bar_64 = 0, len, len_64;
1006 u64 size = 0;
1007 const struct ns16550_config_param *param = uart_param;
1008
1009 nextf = (f || (pci_conf_read16(0, b, d, f, PCI_HEADER_TYPE) &
1010 0x80)) ? f + 1 : 8;
1011
1012 switch ( pci_conf_read16(0, b, d, f, PCI_CLASS_DEVICE) )
1013 {
1014 case 0x0700: /* single port serial */
1015 case 0x0702: /* multi port serial */
1016 case 0x0780: /* other (e.g serial+parallel) */
1017 break;
1018 case 0xffff:
1019 if ( !f )
1020 nextf = 8;
1021 /* fall through */
1022 default:
1023 continue;
1024 }
1025
1026 /* Check for params in uart_config lookup table */
1027 for ( i = 0; i < ARRAY_SIZE(uart_config); i++ )
1028 {
1029 u16 vendor = pci_conf_read16(0, b, d, f, PCI_VENDOR_ID);
1030 u16 device = pci_conf_read16(0, b, d, f, PCI_DEVICE_ID);
1031
1032 if ( uart_config[i].vendor_id == vendor &&
1033 uart_config[i].dev_id == device )
1034 {
1035 param += uart_config[i].param;
1036 break;
1037 }
1038 }
1039
1040 if ( !param->bar0 )
1041 {
1042 bar_idx = idx;
1043 port_idx = 0;
1044 }
1045
1046 if ( port_idx >= param->max_ports )
1047 {
1048 idx -= param->max_ports;
1049 continue;
1050 }
1051
1052 uart->io_base = 0;
1053 bar = pci_conf_read32(0, b, d, f,
1054 PCI_BASE_ADDRESS_0 + bar_idx*4);
1055
1056 /* MMIO based */
1057 if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) )
1058 {
1059 pci_conf_write32(0, b, d, f,
1060 PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u);
1061 len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0 + bar_idx*4);
1062 pci_conf_write32(0, b, d, f,
1063 PCI_BASE_ADDRESS_0 + bar_idx*4, bar);
1064
1065 /* Handle 64 bit BAR if found */
1066 if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
1067 {
1068 bar_64 = pci_conf_read32(0, b, d, f,
1069 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4);
1070 pci_conf_write32(0, b, d, f,
1071 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, ~0u);
1072 len_64 = pci_conf_read32(0, b, d, f,
1073 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4);
1074 pci_conf_write32(0, b, d, f,
1075 PCI_BASE_ADDRESS_0 + (bar_idx+1)*4, bar_64);
1076 size = ((u64)~0 << 32) | PCI_BASE_ADDRESS_MEM_MASK;
1077 size &= ((u64)len_64 << 32) | len;
1078 }
1079 else
1080 size = len & PCI_BASE_ADDRESS_MEM_MASK;
1081
1082 uart->io_base = ((u64)bar_64 << 32) |
1083 (bar & PCI_BASE_ADDRESS_MEM_MASK);
1084 }
1085 /* IO based */
1086 else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) )
1087 {
1088 pci_conf_write32(0, b, d, f,
1089 PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u);
1090 len = pci_conf_read32(0, b, d, f, PCI_BASE_ADDRESS_0);
1091 pci_conf_write32(0, b, d, f,
1092 PCI_BASE_ADDRESS_0 + bar_idx*4, bar);
1093 size = len & PCI_BASE_ADDRESS_IO_MASK;
1094
1095 uart->io_base = bar & ~PCI_BASE_ADDRESS_SPACE_IO;
1096 }
1097
1098 /* If we have an io_base, then we succeeded in the lookup. */
1099 if ( !uart->io_base )
1100 continue;
1101
1102 size &= -size;
1103
1104 /*
1105 * Require length of actually used region to be at least
1106 * 8 bytes times (1 << reg_shift).
1107 */
1108 if ( size < param->first_offset +
1109 port_idx * param->uart_offset +
1110 (8 << param->reg_shift) )
1111 continue;
1112
1113 uart->param = param;
1114
1115 uart->reg_shift = param->reg_shift;
1116 uart->reg_width = param->reg_width;
1117 uart->lsr_mask = param->lsr_mask;
1118 uart->io_base += param->first_offset +
1119 port_idx * param->uart_offset;
1120 if ( param->base_baud )
1121 uart->clock_hz = param->base_baud * 16;
1122 if ( param->fifo_size )
1123 uart->fifo_size = param->fifo_size;
1124
1125 uart->ps_bdf[0] = b;
1126 uart->ps_bdf[1] = d;
1127 uart->ps_bdf[2] = f;
1128 uart->bar_idx = bar_idx;
1129 uart->bar = bar;
1130 uart->bar64 = bar_64;
1131 uart->io_size = max(8U << param->reg_shift,
1132 param->uart_offset);
1133 uart->irq = pci_conf_read8(0, b, d, f, PCI_INTERRUPT_PIN) ?
1134 pci_conf_read8(0, b, d, f, PCI_INTERRUPT_LINE) : 0;
1135
1136 return 0;
1137 }
1138 }
1139 }
1140
1141 if ( !skip_amt )
1142 return -1;
1143
1144 /* No AMT found, fallback to the defaults. */
1145 uart->io_base = orig_base;
1146
1147 return 0;
1148 }
1149 #endif
1150
1151 /*
1152 * Used to parse name value pairs and return which value it is along with
1153 * pointer for the extracted value.
1154 */
get_token(char * token,char ** value)1155 static enum __init serial_param_type get_token(char *token, char **value)
1156 {
1157 const char *param_name;
1158 unsigned int i;
1159
1160 param_name = strsep(&token, "=");
1161 if ( param_name == NULL )
1162 return num_serial_params;
1163
1164 /* Linear search for the parameter. */
1165 for ( i = 0; i < ARRAY_SIZE(sp_vars); i++ )
1166 {
1167 if ( strcmp(sp_vars[i].name, param_name) == 0 )
1168 {
1169 *value = token;
1170 return sp_vars[i].type;
1171 }
1172 }
1173
1174 return num_serial_params;
1175 }
1176
1177 #define PARSE_ERR(_f, _a...) \
1178 do { \
1179 printk( "ERROR: " _f "\n" , ## _a ); \
1180 return; \
1181 } while ( 0 )
1182
1183 #define PARSE_ERR_RET(_f, _a...) \
1184 do { \
1185 printk( "ERROR: " _f "\n" , ## _a ); \
1186 return false; \
1187 } while ( 0 )
1188
1189
parse_positional(struct ns16550 * uart,char ** str)1190 static bool __init parse_positional(struct ns16550 *uart, char **str)
1191 {
1192 int baud;
1193 const char *conf;
1194 char *name_val_pos;
1195
1196 conf = *str;
1197 name_val_pos = strchr(conf, '=');
1198
1199 /* Finding the end of the positional parameters. */
1200 while ( name_val_pos > *str )
1201 {
1202 /* Working backwards from the '=' sign. */
1203 name_val_pos--;
1204 if ( *name_val_pos == ',' )
1205 {
1206 *name_val_pos = '\0';
1207 name_val_pos++;
1208 break;
1209 }
1210 }
1211
1212 *str = name_val_pos;
1213 /* When there are no positional parameters, we return from the function. */
1214 if ( conf == *str )
1215 return true;
1216
1217 /* Parse positional parameters here. */
1218 if ( strncmp(conf, "auto", 4) == 0 )
1219 {
1220 uart->baud = BAUD_AUTO;
1221 conf += 4;
1222 }
1223 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
1224 uart->baud = baud;
1225
1226 if ( *conf == '/' )
1227 {
1228 conf++;
1229 uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4;
1230 }
1231
1232 if ( *conf == ',' && *++conf != ',' )
1233 {
1234 uart->data_bits = simple_strtoul(conf, &conf, 10);
1235
1236 uart->parity = parse_parity_char(*conf);
1237
1238 uart->stop_bits = simple_strtoul(conf + 1, &conf, 10);
1239 }
1240
1241 if ( *conf == ',' && *++conf != ',' )
1242 {
1243 #ifdef CONFIG_HAS_PCI
1244 if ( strncmp(conf, "pci", 3) == 0 )
1245 {
1246 if ( pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com) )
1247 return true;
1248 conf += 3;
1249 }
1250 else if ( strncmp(conf, "amt", 3) == 0 )
1251 {
1252 if ( pci_uart_config(uart, 0, uart - ns16550_com) )
1253 return true;
1254 conf += 3;
1255 }
1256 else
1257 #endif
1258 {
1259 uart->io_base = simple_strtoul(conf, &conf, 0);
1260 }
1261 }
1262
1263 if ( *conf == ',' && *++conf != ',' )
1264 uart->irq = simple_strtol(conf, &conf, 10);
1265
1266 #ifdef CONFIG_HAS_PCI
1267 if ( *conf == ',' && *++conf != ',' )
1268 {
1269 conf = parse_pci(conf, NULL, &uart->ps_bdf[0],
1270 &uart->ps_bdf[1], &uart->ps_bdf[2]);
1271 if ( !conf )
1272 PARSE_ERR_RET("Bad port PCI coordinates");
1273 uart->ps_bdf_enable = true;
1274 }
1275
1276 if ( *conf == ',' && *++conf != ',' )
1277 {
1278 if ( !parse_pci(conf, NULL, &uart->pb_bdf[0],
1279 &uart->pb_bdf[1], &uart->pb_bdf[2]) )
1280 PARSE_ERR_RET("Bad bridge PCI coordinates");
1281 uart->pb_bdf_enable = true;
1282 }
1283 #endif
1284
1285 return true;
1286 }
1287
parse_namevalue_pairs(char * str,struct ns16550 * uart)1288 static bool __init parse_namevalue_pairs(char *str, struct ns16550 *uart)
1289 {
1290 char *token, *start = str;
1291 char *param_value = NULL;
1292 bool dev_set = false;
1293
1294 if ( (str == NULL) || (*str == '\0') )
1295 return true;
1296
1297 do
1298 {
1299 /* When no tokens are found, start will be NULL */
1300 token = strsep(&start, ",");
1301
1302 switch ( get_token(token, ¶m_value) )
1303 {
1304 case baud:
1305 uart->baud = simple_strtoul(param_value, NULL, 0);
1306 break;
1307
1308 case clock_hz:
1309 uart->clock_hz = simple_strtoul(param_value, NULL, 0) << 4;
1310 break;
1311
1312 case io_base:
1313 if ( dev_set )
1314 {
1315 printk(XENLOG_WARNING
1316 "Can't use io_base with dev=pci or dev=amt options\n");
1317 break;
1318 }
1319 uart->io_base = simple_strtoul(param_value, NULL, 0);
1320 break;
1321
1322 case irq:
1323 uart->irq = simple_strtoul(param_value, NULL, 0);
1324 break;
1325
1326 case data_bits:
1327 uart->data_bits = simple_strtoul(param_value, NULL, 0);
1328 break;
1329
1330 case parity:
1331 uart->parity = parse_parity_char(*param_value);
1332 break;
1333
1334 case stop_bits:
1335 uart->stop_bits = simple_strtoul(param_value, NULL, 0);
1336 break;
1337
1338 case reg_shift:
1339 uart->reg_shift = simple_strtoul(param_value, NULL, 0);
1340 break;
1341
1342 case reg_width:
1343 uart->reg_width = simple_strtoul(param_value, NULL, 0);
1344 break;
1345
1346 #ifdef CONFIG_HAS_PCI
1347 case bridge_bdf:
1348 if ( !parse_pci(param_value, NULL, &uart->ps_bdf[0],
1349 &uart->ps_bdf[1], &uart->ps_bdf[2]) )
1350 PARSE_ERR_RET("Bad port PCI coordinates\n");
1351 uart->ps_bdf_enable = true;
1352 break;
1353
1354 case device:
1355 if ( strncmp(param_value, "pci", 3) == 0 )
1356 {
1357 pci_uart_config(uart, 1/* skip AMT */, uart - ns16550_com);
1358 dev_set = true;
1359 }
1360 else if ( strncmp(param_value, "amt", 3) == 0 )
1361 {
1362 pci_uart_config(uart, 0, uart - ns16550_com);
1363 dev_set = true;
1364 }
1365 break;
1366
1367 case port_bdf:
1368 if ( !parse_pci(param_value, NULL, &uart->pb_bdf[0],
1369 &uart->pb_bdf[1], &uart->pb_bdf[2]) )
1370 PARSE_ERR_RET("Bad port PCI coordinates\n");
1371 uart->pb_bdf_enable = true;
1372 break;
1373 #endif
1374
1375 default:
1376 PARSE_ERR_RET("Invalid parameter: %s\n", token);
1377 }
1378 } while ( start != NULL );
1379
1380 return true;
1381 }
1382
ns16550_parse_port_config(struct ns16550 * uart,const char * conf)1383 static void __init ns16550_parse_port_config(
1384 struct ns16550 *uart, const char *conf)
1385 {
1386 char com_console_options[128];
1387 char *str;
1388
1389 /* No user-specified configuration? */
1390 if ( (conf == NULL) || (*conf == '\0') )
1391 {
1392 /* Some platforms may automatically probe the UART configuartion. */
1393 if ( uart->baud != 0 )
1394 goto config_parsed;
1395 return;
1396 }
1397
1398 strlcpy(com_console_options, conf, ARRAY_SIZE(com_console_options));
1399 str = com_console_options;
1400
1401 /* parse positional parameters and get pointer for name-value pairs */
1402 if ( !parse_positional(uart, &str) )
1403 return;
1404
1405 if ( !parse_namevalue_pairs(str, uart) )
1406 return;
1407
1408 config_parsed:
1409 /* Sanity checks. */
1410 if ( (uart->baud != BAUD_AUTO) &&
1411 ((uart->baud < 1200) || (uart->baud > 115200)) )
1412 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
1413 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
1414 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
1415 if ( (uart->reg_width != 1) && (uart->reg_width != 4) )
1416 PARSE_ERR("Accepted values of reg_width are 1 and 4 only");
1417 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
1418 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
1419 if ( uart->io_base == 0 )
1420 PARSE_ERR("I/O base address must be specified.");
1421 if ( !check_existence(uart) )
1422 PARSE_ERR("16550-compatible serial UART not present");
1423
1424 /* Register with generic serial driver. */
1425 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
1426 }
1427
ns16550_init_common(struct ns16550 * uart)1428 static void ns16550_init_common(struct ns16550 *uart)
1429 {
1430 uart->clock_hz = UART_CLOCK_HZ;
1431
1432 /* Default is no transmit FIFO. */
1433 uart->fifo_size = 1;
1434
1435 /* Default lsr_mask = UART_LSR_THRE */
1436 uart->lsr_mask = UART_LSR_THRE;
1437 }
1438
ns16550_init(int index,struct ns16550_defaults * defaults)1439 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
1440 {
1441 struct ns16550 *uart;
1442
1443 if ( (index < 0) || (index > 1) )
1444 return;
1445
1446 uart = &ns16550_com[index];
1447
1448 ns16550_init_common(uart);
1449
1450 uart->baud = (defaults->baud ? :
1451 console_has((index == 0) ? "com1" : "com2")
1452 ? BAUD_AUTO : 0);
1453 uart->data_bits = defaults->data_bits;
1454 uart->parity = parse_parity_char(defaults->parity);
1455 uart->stop_bits = defaults->stop_bits;
1456 uart->irq = defaults->irq;
1457 uart->io_base = defaults->io_base;
1458 uart->io_size = 8;
1459 uart->reg_width = 1;
1460 uart->reg_shift = 0;
1461
1462 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
1463 }
1464
1465 #ifdef CONFIG_HAS_DEVICE_TREE
ns16550_uart_dt_init(struct dt_device_node * dev,const void * data)1466 static int __init ns16550_uart_dt_init(struct dt_device_node *dev,
1467 const void *data)
1468 {
1469 struct ns16550 *uart;
1470 int res;
1471 u32 reg_shift, reg_width;
1472 u64 io_size;
1473
1474 uart = &ns16550_com[0];
1475
1476 ns16550_init_common(uart);
1477
1478 uart->baud = BAUD_AUTO;
1479 uart->data_bits = 8;
1480 uart->parity = UART_PARITY_NONE;
1481 uart->stop_bits = 1;
1482
1483 res = dt_device_get_address(dev, 0, &uart->io_base, &io_size);
1484 if ( res )
1485 return res;
1486
1487 uart->io_size = io_size;
1488
1489 ASSERT(uart->io_size == io_size); /* Detect truncation */
1490
1491 res = dt_property_read_u32(dev, "reg-shift", ®_shift);
1492 if ( !res )
1493 uart->reg_shift = 0;
1494 else
1495 uart->reg_shift = reg_shift;
1496
1497 res = dt_property_read_u32(dev, "reg-io-width", ®_width);
1498 if ( !res )
1499 uart->reg_width = 1;
1500 else
1501 uart->reg_width = reg_width;
1502
1503 if ( uart->reg_width != 1 && uart->reg_width != 4 )
1504 return -EINVAL;
1505
1506 res = platform_get_irq(dev, 0);
1507 if ( ! res )
1508 return -EINVAL;
1509 uart->irq = res;
1510
1511 uart->dw_usr_bsy = dt_device_is_compatible(dev, "snps,dw-apb-uart");
1512
1513 uart->vuart.base_addr = uart->io_base;
1514 uart->vuart.size = uart->io_size;
1515 uart->vuart.data_off = UART_THR <<uart->reg_shift;
1516 uart->vuart.status_off = UART_LSR<<uart->reg_shift;
1517 uart->vuart.status = UART_LSR_THRE|UART_LSR_TEMT;
1518
1519 /* Register with generic serial driver. */
1520 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
1521
1522 dt_device_set_used_by(dev, DOMID_XEN);
1523
1524 return 0;
1525 }
1526
1527 static const struct dt_device_match ns16550_dt_match[] __initconst =
1528 {
1529 DT_MATCH_COMPATIBLE("ns16550"),
1530 DT_MATCH_COMPATIBLE("ns16550a"),
1531 DT_MATCH_COMPATIBLE("snps,dw-apb-uart"),
1532 { /* sentinel */ },
1533 };
1534
1535 DT_DEVICE_START(ns16550, "NS16550 UART", DEVICE_SERIAL)
1536 .dt_match = ns16550_dt_match,
1537 .init = ns16550_uart_dt_init,
1538 DT_DEVICE_END
1539
1540 #endif /* HAS_DEVICE_TREE */
1541 /*
1542 * Local variables:
1543 * mode: C
1544 * c-file-style: "BSD"
1545 * c-basic-offset: 4
1546 * tab-width: 4
1547 * indent-tabs-mode: nil
1548 * End:
1549 */
1550