1 /**
2 ******************************************************************************
3 * @file rtl8721dhp_rcc.h
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for peripheral reset and clock control driver.
8 ******************************************************************************
9 * @attention
10 *
11 * This module is a confidential and proprietary property of RealTek and
12 * possession or use of this module requires written permission of RealTek.
13 *
14 * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
15 ******************************************************************************
16 */
17
18 #ifndef _RTL8721D_HP_RCC_H_
19 #define _RTL8721D_HP_RCC_H_
20
21 /** @addtogroup AmebaD_Platform
22 * @{
23 */
24
25 /** @defgroup RCC
26 * @brief RCC driver modules
27 * @{
28 */
29
30
31 /** @defgroup HS_RCC
32 * @verbatim
33 *****************************************************************************************
34 * Introduction
35 *****************************************************************************************
36 * - functions prototypes for peripheral reset and clock control driver.
37 *
38 *****************************************************************************************
39 *
40 *****************************************************************************************
41 * how to use
42 *****************************************************************************************
43 * use UART0 as example:
44 * RCC_PeriphClockCmd(APBPeriph_UART0, APBPeriph_UART0_CLOCK, ENABLE);
45 *
46 *****************************************************************************************
47 * @endverbatim
48 */
49
50 /** @addtogroup HS_RCC
51 * @brief HS_RCC driver modules
52 * @{
53 */
54
55 /* Exported constants --------------------------------------------------------*/
56
57 /** @defgroup HS_RCC_CLK_Exported_Constants HS_RCC CLK Exported Constants
58 * @{
59 */
60
61 #define SYS_CLK_CTRL1 0x03 //0x210
62 #define SYS_CLK_CTRL2 0x02
63 #define SYS_CLK_CTRL3 0x01
64 #define SYS_CLK_CTRL4 0x00
65 #define APBPeriph_CLOCK_NULL 0 //if you dont want to set any clock, you can use this
66
67 #define APBPeriph_PSRAM_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_PSRAM_CKE | BIT_SHIFT_HSYS_PSRAM_CKSL_100)
68 #define APBPeriph_AUDIOC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HSYS_AC_CK)
69 #define APBPeriph_VENDOR_REG_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_VNDR_CKE)
70 #define APBPeriph_USI_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_USI_CKE)
71 #define APBPeriph_IRDA_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IRDA_CKE)
72 #define APBPeriph_IPC_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_IPC_CKE)
73 #define APBPeriph_GTIMER_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_TIMER0_CKE)
74 #define APBPeriph_SPI1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI1_CKE)
75 #define APBPeriph_SPI0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_SPI0_CKE)
76 #define APBPeriph_UART1_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART1_CKE)
77 #define APBPeriph_UART0_CLOCK (SYS_CLK_CTRL1 << 30 | BIT_HS_UART0_CKE)
78
79 #define APBPeriph_BT_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_BT_CKE)
80 #define APBPeriph_WL_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_WLAN_CKSL_AXIF | BIT_HSYS_WLAN_CKE_AXIF)
81 #define APBPeriph_GDMA0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_GDMA0_CKE)
82 #define APBPeriph_LCDC_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LCDC_CKE)
83 #define APBPeriph_I2S0_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_I2S0_CKE)
84 #define APBPeriph_SEC_ENG_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_IPSEC_CKE)
85 #define APBPeriph_LXBUS_CLOCK (SYS_CLK_CTRL2 << 30 | BIT_HSYS_LX1BUS_CKE)
86
87 #define APBPeriph_SPORT_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SPORT_CKE)
88 #define APBPeriph_OTG_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_USBOTG_CKE)
89 #define APBPeriph_SDIOH_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDH_CKE_SCLK | BIT_HSYS_SDH_CKE_BCLK)
90 #define APBPeriph_SDIOD_CLOCK (SYS_CLK_CTRL3 << 30 | BIT_HSYS_SDD_CKE)
91 /**
92 * @}
93 */
94
95 /** @defgroup AON_RCC_CLK_Exported_Constants Exported Constants
96 * @{
97 */
98 #define APBPeriph_RTC_CLOCK (BIT_AON_RTC_CKE)
99 #define APBPeriph_CTOUCH_CLOCK (BIT_AON_CTOUCH_CKE)
100 #define APBPeriph_CK32KGEN_CLOCK (BIT_AON_CK32KGEN_CKE)
101 #define APBPeriph_KEYSCAN_CLOCK (BIT_AON_KEYSCAN_CKE)
102 #define APBPeriph_TSF_CLOCK (BIT_AON_TSF_CKE)
103 /**
104 * @}
105 */
106
107 /** @defgroup HS_RCC_FUNC_Exported_Constants HS_RCC FUNC Exported Constants
108 * @{
109 */
110
111 #define SYS_FUNC_EN1 0x03 //0x200
112 #define SYS_FUNC_EN2 0x02 //0x204
113 #define SYS_FUNC_EN3 0x01 //0x208
114 #define SYS_FUNC_EN4 0x00 //0x
115 #define APBPeriph_NULL 0 //if you dont want to set any function, you can use this
116
117 #define APBPeriph_PSRAM (SYS_FUNC_EN1 << 30 | BIT_HSYS_PSRAM_FEN)
118 #define APBPeriph_AUDIOC (SYS_FUNC_EN1 << 30 | BIT_HSYS_AC_FEN)
119 #define APBPeriph_VENDOR_REG (SYS_FUNC_EN1 << 30 | BIT_HS_VNDR_FEN)
120 #define APBPeriph_USI_REG (SYS_FUNC_EN1 << 30 | BIT_HS_USI_FEN)
121 #define APBPeriph_IRDA_REG (SYS_FUNC_EN1 << 30 | BIT_HS_IRDA_FEN)
122 #define APBPeriph_IPC (SYS_FUNC_EN1 << 30 | BIT_HS_IPC_FEN)
123 #define APBPeriph_GTIMER (SYS_FUNC_EN1 << 30 | BIT_HS_TIMER0_FEN)
124 #define APBPeriph_SPI1 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI1_FEN)
125 #define APBPeriph_SPI0 (SYS_FUNC_EN1 << 30 | BIT_HS_SPI0_FEN)
126 #define APBPeriph_UART1 (SYS_FUNC_EN1 << 30 | BIT_HS_UART1_FEN_FUN | BIT_HS_UART1_FEN_GLB)
127 #define APBPeriph_UART0 (SYS_FUNC_EN1 << 30 | BIT_HS_UART0_FEN_FUN | BIT_HS_UART0_FEN_GLB)
128
129 #define APBPeriph_BT (SYS_FUNC_EN2 << 30 | BIT_HSYS_BT_FEN)
130 #define APBPeriph_WL (SYS_FUNC_EN2 << 30 | BIT_HSYS_WLAN_FEN_AXIF)
131 #define APBPeriph_GDMA0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_GDMA0_FEN)
132 #define APBPeriph_LCDC (SYS_FUNC_EN2 << 30 | BIT_HSYS_LCDC_FEN)
133 #define APBPeriph_I2S0 (SYS_FUNC_EN2 << 30 | BIT_HSYS_I2S0_FEN)
134 #define APBPeriph_SECURITY_ENGINE (SYS_FUNC_EN2 << 30 | BIT_HSYS_IPSEC_FEN)
135 #define APBPeriph_LXBUS (SYS_FUNC_EN2 << 30 | BIT_HSYS_LX1BUS_FEN)
136
137 #define APBPeriph_SPORT (SYS_FUNC_EN3 << 30 | BIT_HSYS_SPORT_FEN)
138 #define APBPeriph_OTG (SYS_FUNC_EN3 << 30 | BIT_HSYS_USBOTG_FEN)
139 #define APBPeriph_SDIOH (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDH_FEN_SCKGEN | BIT_HSYS_SDH_FEN)
140 #define APBPeriph_SDIOD (SYS_FUNC_EN3 << 30 | BIT_HSYS_SDD_FEN_OFF | BIT_HSYS_SDD_FEN_ON)
141 /**
142 * @}
143 */
144
145 /** @defgroup AON_RCC_FUNC_Exported_Constants Exported Constants
146 * @{
147 */
148 #define APBPeriph_RTC (BIT_AON_RTC_FEN)
149 #define APBPeriph_CTOUCH (BIT_AON_CTOUCH_FEN)
150 #define APBPeriph_CK32KGEN (BIT_AON_CK32KGEN_FEN)
151 #define APBPeriph_KEYSCAN (BIT_AON_KEYSCAN_FEN)
152 #define APBPeriph_TSF (BIT_AON_TSF_FEN)
153 /**
154 * @}
155 */
156
157 /* Exported functions --------------------------------------------------------*/
158 /** @defgroup HS_RCC_Exported_Functions HS_RCC Exported Functions
159 * @{
160 */
161 _LONG_CALL_ void RCC_PeriphClockCmd(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState);
162 _LONG_CALL_ void RCC_WIFIClockCmd(u8 NewState);
163 _LONG_CALL_ void RCC_PeriphClockSource_RTC(u32 Xtal);
164 _LONG_CALL_ void RCC_PeriphClockSource_I2C(UNUSED_WARN_DIS u32 Idx, u32 Source);
165 _LONG_CALL_ void RCC_PeriphClockSource_QDEC(UNUSED_WARN_DIS u32 Idx, u32 Source);
166 _LONG_CALL_ void RCC_PeriphClockSource_UART (UART_TypeDef* UARTx, u32 Source);
167
168 /**
169 * @brief Enables or disables the AON APB peripheral clock and function
170 * @param APBPeriph: specifies the APB peripheral to gates its clock.
171 * this parameter can be one of @ref AON_RCC_FUNC_Exported_Constants
172 * @param APBPeriph_Clock: specifies the APB peripheral clock config.
173 * this parameter can be one of @ref AON_RCC_CLK_Exported_Constants
174 * @param NewState: new state of the specified peripheral clock.
175 * This parameter can be: ENABLE or DISABLE.
176 */
RCC_PeriphClockCmd_AON(u32 APBPeriph,u32 APBPeriph_Clock,u8 NewState)177 __STATIC_INLINE void RCC_PeriphClockCmd_AON(u32 APBPeriph, u32 APBPeriph_Clock, u8 NewState)
178 {
179 u32 TempVal = 0;
180
181 //clock
182 if (APBPeriph_Clock != APBPeriph_CLOCK_NULL) {
183 if(NewState == ENABLE)
184 {
185 TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
186 TempVal |= APBPeriph_Clock;
187 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
188 } else {
189 TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
190 TempVal &= ~APBPeriph_Clock;
191 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
192 }
193 }
194
195 if (APBPeriph == APBPeriph_NULL)
196 return;
197
198 //function
199 if(NewState == ENABLE)
200 {
201 TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
202 TempVal |= APBPeriph;
203 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
204 } else {
205 TempVal = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL);
206 TempVal &= ~APBPeriph;
207 HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AON_ISO_CTRL, TempVal);
208 }
209
210 return;
211 }
212
213 /**
214 * @}
215 */
216
217 /**
218 * @}
219 */
220
221 /**
222 * @}
223 */
224
225 /**
226 * @}
227 */
228
229 /* Registers Definitions --------------------------------------------------------*/
230 /* Other definations --------------------------------------------------------*/
231
232 #endif /* _RTL8721D_HP_RCC_H_ */
233 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
234
235