1 /** 2 ****************************************************************************** 3 * @file rtl8721d_keyscan.h 4 * @author 5 * @version V1.0.0 6 * @date 2017-10-16 7 * @brief This file contains all the functions prototypes for the keyscan. 8 ****************************************************************************** 9 * @attention 10 * 11 * This module is a confidential and proprietary property of RealTek and 12 * possession or use of this module requires written permission of RealTek. 13 * 14 * Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved. 15 ****************************************************************************** 16 */ 17 18 19 #ifndef _RTL8721D_KEYSCAN_H_ 20 #define _RTL8721D_KEYSCAN_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @addtogroup KeyScan KeyScan 27 * @{ 28 */ 29 30 /** @addtogroup KeyScan 31 * @verbatim 32 ***************************************************************************************** 33 * Introduction 34 ***************************************************************************************** 35 * KEYSCAN: 36 * - Base Address: KEYSCAN_DEV 37 * - Sclk: 32K/10Mhz 38 * - Keypad Array: Up to 6*6 (36), multi-key detect 39 * - Scan Clock: Configurable, up to 10Mhz 40 * - Work Mode: Event Trigger Mode and Regular Scan Mode 41 * - Debounce Timer: Configurable 42 * - SocPs: Sleep Mode (clock gating & power gating) 43 * - IRQ: KeyScan_IRQ 44 * 45 ***************************************************************************************** 46 * How to use Normal KeyScan 47 ***************************************************************************************** 48 * To use the normal KeyScan mode, the following steps are mandatory: 49 * 50 * 1. Enable KeyScan peripheral clock 51 * 52 * 2. configure the KeyScan pinmux. 53 * 54 * 3. Program Scan clock, Work Mode, Columns and Rows select, Dobounce Timer, Threshold 55 * KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct) 56 * 57 * 4. Init Hardware use step3 parameters: 58 * KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct) 59 * 60 * 5. Enable the NVIC and the corresponding interrupt using following function if you need 61 * to use interrupt mode. 62 * KeyScan_INTConfig(): KeyScan IRQ Enable set 63 * KeyScan_INTMask(): KeyScan IRQ mask set 64 * InterruptRegister(): register the keyscan irq handler 65 * InterruptEn(): Enable the NVIC interrupt 66 * 67 * 6. Enable KeyScan module using KeyScan_Cmd(). 68 * 69 ***************************************************************************************** 70 * @endverbatim 71 */ 72 73 /* Exported types --------------------------------------------------------*/ 74 /** @defgroup KeyScan_Exported_Types KeyScan Exported Types 75 * @{ 76 */ 77 78 /** 79 * @brief KeyScan Init structure definition 80 */ 81 typedef struct { 82 u32 KS_ClkDiv; /*!< Specifies Keyscan clock divider. Scan_clk = Bus clock/(KS_ClkDiv+1). 83 This parameter must be set to a value in the 0x0-0xfff range. */ 84 85 u32 KS_WorkMode; /*!< Specifies Keyscan work mode. 86 This parameter can be a value of @ref KeyScan_Work_Mode_definitions */ 87 88 u32 KS_RowSel; /*!< Specifies which row(s) is used. 89 This parameter must be set to a value in the 0x1-0xff range. */ 90 91 u32 KS_ColSel; /*!< Specifies which column(s) is used. 92 This parameter must be set to a value in the 0x1-0xff range. */ 93 94 u32 KS_DebounceCnt; /*!< Specifies Keyscan Debounce Timer. Debounce Timer = (KS_DebounceCnt +1)* Scan_clk. 95 This parameter must be set to a value in the 0x0-0xfff range. */ 96 97 u32 KS_IntervalCnt; /*!< Specifies Keyscan Scan Interval Timer. Interval Timer = (KS_IntervalCnt +1)* Scan_clk. 98 This parameter must be set to a value in the 0x0-0xfff range. */ 99 100 u32 KS_ReleaseCnt; /*!< Specifies Keyscan All Release Timer. Release Timer = (KS_ReleaseCnt+1) * Scan_clk. 101 This parameter must be set to a value in the 0x0-0xfff range. */ 102 103 u32 KS_LimitLevel; /*!< Specifies the max allowable key number be pressed at a time 104 This parameter can be a value of @ref KeyScan_FIFO_LimitLevel_Control */ 105 106 u32 KS_ThreholdLevel; /*!< Specifies Keyscan FIFO threshold to trigger KS_FIFO_FULL 107 This parameter can be a value of @ref KeyScan_FIFO_ThreholdLevel_Control */ 108 109 u32 KS_OverCtrl; /*!< Specifies Keyscan FIFO over control. 110 This parameter can be a value of @ref KeyScan_FIFO_Overflow_Control */ 111 }KeyScan_InitTypeDef; 112 /** 113 * @} 114 */ 115 116 /* Exported constants --------------------------------------------------------*/ 117 /** @defgroup KeyScan_Exported_Constants KeyScan Exported Constants 118 * @{ 119 */ 120 121 /** @defgroup KeyScan_Peripheral_definitions 122 * @{ 123 */ 124 #define IS_KEYSCAN_ALL_PERIPH(PERIPH) ((PERIPH) == KEYSCAN_DEV) 125 /** 126 * @} 127 */ 128 129 /** @defgroup KeyScan_Work_Mode_definitions 130 * @{ 131 */ 132 #define KS_REGULAR_SCAN_MODE ((u32)0x00000000 << 3) 133 #define KS_EVENT_TRIGGER_MODE ((u32)0x00000001 << 3) 134 #define IS_KS_WORK_MODE(MODE) (((MODE) == KS_REGULAR_SCAN_MODE) || \ 135 ((MODE) == KS_EVENT_TRIGGER_MODE)) 136 /** 137 * @} 138 */ 139 140 /** @defgroup KeyScan_FIFO_Overflow_Control 141 * @{ 142 */ 143 #define KS_FIFO_OVER_CTRL_DIS_NEW ((u32)0x00000000 << 1) 144 #define KS_FIFO_OVER_CTRL_DIS_LAST ((u32)0x00000001 << 1) 145 #define IS_KS_FIFO_OVER_CTRL(CTRL) (((CTRL) == KS_FIFO_OVER_CTRL_DIS_NEW) || \ 146 ((CTRL) == KS_FIFO_OVER_CTRL_DIS_LAST)) 147 /** 148 * @} 149 */ 150 151 /** @defgroup KeyScan_FIFO_LimitLevel_Control 152 * @{ 153 */ 154 #define IS_KS_FIFO_LIMIT_LEVEL(DATA_NUM) ((DATA_NUM) <= 6) 155 /** 156 * @} 157 */ 158 159 /** @defgroup KeyScan_FIFO_ThreholdLevel_Control 160 * @{ 161 */ 162 #define IS_KS_FIFO_TH_LEVEL(DATA_NUM) (((DATA_NUM) > 0) && ((DATA_NUM) < 16)) 163 /** 164 * @} 165 */ 166 167 /** 168 * @} 169 */ 170 171 /* Exported functions --------------------------------------------------------*/ 172 /** @defgroup KeyScan_Exported_Functions KeyScan Exported Functions 173 * @{ 174 */ 175 176 /** @defgroup KeyScan_Exported_Normal_Functions KeyScan Exported Normal Functions 177 * @{ 178 */ 179 _LONG_CALL_ void KeyScan_StructInit(KeyScan_InitTypeDef* KeyScan_InitStruct); 180 _LONG_CALL_ void KeyScan_Init(KEYSCAN_TypeDef *KeyScan, KeyScan_InitTypeDef* KeyScan_InitStruct); 181 _LONG_CALL_ void KeyScan_INTConfig(KEYSCAN_TypeDef *KeyScan, uint32_t KeyScan_IT, u8 newState); 182 _LONG_CALL_ void KeyScan_ClearINT(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_IT); 183 _LONG_CALL_ u32 KeyScan_GetRawINT(KEYSCAN_TypeDef *KeyScan); 184 _LONG_CALL_ u32 KeyScan_GetINT(KEYSCAN_TypeDef *KeyScan); 185 _LONG_CALL_ u8 KeyScan_GetDataNum(KEYSCAN_TypeDef *KeyScan); 186 _LONG_CALL_ void KeyScan_ClearFIFOData(KEYSCAN_TypeDef *KeyScan); 187 _LONG_CALL_ BOOL KeyScan_GetFIFOState(KEYSCAN_TypeDef *KeyScan, u32 KeyScan_Flag); 188 _LONG_CALL_ void KeyScan_Read(KEYSCAN_TypeDef *KeyScan, u32 *outBuf, u8 count); 189 _LONG_CALL_ void KeyScan_Cmd(KEYSCAN_TypeDef *KeyScan, u8 NewState); 190 /** 191 * @} 192 */ 193 194 /** 195 * @} 196 */ 197 198 199 /* Registers Definitions --------------------------------------------------------*/ 200 /**************************************************************************//** 201 * @defgroup KeyScan_Register_Definitions KeyScan Register Definitions 202 * @{ 203 *****************************************************************************/ 204 205 /**************************************************************************//** 206 * @defgroup KS_CLK_DIV 207 * @{ 208 *****************************************************************************/ 209 #define BIT_KS_CLK_DIV ((u32)0x00000fff) /*Bit[11:0], bits for clock division*/ 210 /** @} */ 211 212 /**************************************************************************//** 213 * @defgroup KS_TIM_CFG0 214 * @{ 215 *****************************************************************************/ 216 #define BIT_KS_POST_GUARD_TIMER ((u32)0x0000000f << 24) /*Bit[27:24], bits for post guard timer set*/ 217 #define BIT_KS_PRE_GUARD_TIMER ((u32)0x0000000f << 16) /*Bit[19:16], bits for pre guard timer set*/ 218 #define BIT_KS_DEB_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for debounce timer set*/ 219 /** @} */ 220 221 /**************************************************************************//** 222 * @defgroup KS_TIM_CFG1 223 * @{ 224 *****************************************************************************/ 225 #define BIT_KS_INTERVAL_TIMER ((u32)0x00000fff << 16) /*Bit[27:16], bits for interval timer set*/ 226 #define BIT_KS_RELEASE_TIMER ((u32)0x00000fff) /*Bit[11:0], bits for all release timer set*/ 227 /** @} */ 228 229 /**************************************************************************//** 230 * @defgroup KS_CTRL 231 * @{ 232 *****************************************************************************/ 233 #define BIT_KS_WORK_MODE ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan work mode select*/ 234 #define BIT_KS_BUSY_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for FSM busy status*/ 235 #define BIT_KS_RUN_ENABLE ((u32)0x00000001) /*Bit[0], bit for enable internal key scan scan clock*/ 236 /** @} */ 237 238 /**************************************************************************//** 239 * @defgroup KS_FIFO_CFG 240 * @{ 241 *****************************************************************************/ 242 #define BIT_KS_FIFO_LIMIT_LEVEL ((u32)0x0000000f << 24) /*Bit[27:24], bits for fifo limit level set*/ 243 #define BIT_KS_FIFO_THREHOLD_LEVEL ((u32)0x0000000f << 16) /*Bit[19:16], bits for fifo threshold set*/ 244 #define BIT_KS_FIFO_OV_CTRL ((u32)0x00000001 << 1) /*Bit[1], bit for fifo overflow control*/ 245 #define BIT_KS_FIFO_CLR ((u32)0x00000001) /*Bit[0], bit for fifo data clear*/ 246 /** @} */ 247 248 /**************************************************************************//** 249 * @defgroup KS_COL_CFG 250 * @{ 251 *****************************************************************************/ 252 #define BIT_KS_COLUMN_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key column select*/ 253 /** @} */ 254 255 /**************************************************************************//** 256 * @defgroup KS_ROW_CFG 257 * @{ 258 *****************************************************************************/ 259 #define BIT_KS_ROW_SEL ((u32)0x000000ff) /*Bit[7:0], bits for key row select*/ 260 /** @} */ 261 262 /**************************************************************************//** 263 * @defgroup KS_DATA_NUM 264 * @{ 265 *****************************************************************************/ 266 #define BIT_KS_FIFO_FULL ((u32)0x00000001 << 17) /*Bit[17], bit for fifo full flag*/ 267 #define BIT_KS_FIFO_EMPTY ((u32)0x00000001 << 16) /*Bit[16], bit for fifo empty flag*/ 268 #define BIT_KS_FIFO_DATA_LEVEL ((u32)0x0000001f) /*Bit[4:0], bits for fifo data level*/ 269 /** @} */ 270 271 /**************************************************************************//** 272 * @defgroup KS_DATA 273 * @{ 274 *****************************************************************************/ 275 #define BIT_KS_PRESS_EVENT ((u32)0x00000001 << 8) /*Bit[8], bit for key press event*/ 276 #define BIT_KS_RELEASE_EVENT ((u32)0x00000000 << 8) /*Bit[8], bit for key release event*/ 277 #define BIT_KS_EVENT_FLAG ((u32)0x0000000f << 8) /*Bit[11:8], bits for keyscan event*/ 278 #define BIT_KS_ROW_INDEX ((u32)0x0000000f << 4) /*Bit[7:4], bits for key row index*/ 279 #define BIT_KS_COL_INDEX ((u32)0x0000000f) /*Bit[3:0], bits for key column index*/ 280 #define BIT_KS_DATA ((u32)0x00000fff) /*Bit[11:8], bits for keyscan data*/ 281 /** @} */ 282 283 /**************************************************************************//** 284 * @defgroup KS_IMR 285 * @{ 286 *****************************************************************************/ 287 #define BIT_KS_SCAN_EVENT_INT_MSK ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt mask*/ 288 #define BIT_KS_FIFO_LIMIT_INT_MSK ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt mask*/ 289 #define BIT_KS_FIFO_OVERFLOW_INT_MSK ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt mask*/ 290 #define BIT_KS_FIFO_FULL_INT_MSK ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt mask*/ 291 #define BIT_KS_SCAN_FINISH_INT_MSK ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt mask*/ 292 #define BIT_KS_FIFO_NOTEMPTY_INT_MSK ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt mask*/ 293 #define BIT_KS_ALL_RELEASE_INT_MSK ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt mask*/ 294 #define BIT_KS_ALL_INT_MSK ((u32)0x0000007f) 295 /** @} */ 296 297 /**************************************************************************//** 298 * @defgroup KS_ICR 299 * @{ 300 *****************************************************************************/ 301 #define BIT_KS_FIFO_LIMIT_INT_CLR ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt clear*/ 302 #define BIT_KS_FIFO_OVERFLOW_INT_CLR ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt clear*/ 303 #define BIT_KS_SCAN_FINISH_INT_CLR ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt clear*/ 304 #define BIT_KS_ALL_RELEASE_INT_CLR ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt clear*/ 305 #define BIT_KS_ALL_INT_CLR ((u32)0x0000007f) 306 /** @} */ 307 308 /**************************************************************************//** 309 * @defgroup KS_ISR 310 * @{ 311 *****************************************************************************/ 312 #define BIT_KS_SCAN_EVENT_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event interrupt status*/ 313 #define BIT_KS_FIFO_LIMIT_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit interrupt status*/ 314 #define BIT_KS_FIFO_OVERFLOW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow interrupt status*/ 315 #define BIT_KS_FIFO_FULL_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full interrupt status*/ 316 #define BIT_KS_SCAN_FINISH_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish interrupt status*/ 317 #define BIT_KS_FIFO_NOTEMPTY_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty interrupt status*/ 318 #define BIT_KS_ALL_RELEASE_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release interrupt status*/ 319 /** @} */ 320 321 /**************************************************************************//** 322 * @defgroup KS_ISR_RAW 323 * @{ 324 *****************************************************************************/ 325 #define BIT_KS_SCAN_EVENT_RAW_INT_STATUS ((u32)0x00000001 << 6) /*Bit[6], bit for key event raw interrupt status*/ 326 #define BIT_KS_FIFO_LIMIT_RAW_INT_STATUS ((u32)0x00000001 << 5) /*Bit[5], bit for keyscan fifo limit raw interrupt status*/ 327 #define BIT_KS_FIFO_OVERFLOW_RAW_INT_STATUS ((u32)0x00000001 << 4) /*Bit[4], bit for keyscan fifo overflow raw interrupt status*/ 328 #define BIT_KS_FIFO_FULL_RAW_INT_STATUS ((u32)0x00000001 << 3) /*Bit[3], bit for keyscan fifo full raw interrupt status*/ 329 #define BIT_KS_SCAN_FINISH_RAW_INT_STATUS ((u32)0x00000001 << 2) /*Bit[2], bit for keyscan finish raw interrupt status*/ 330 #define BIT_KS_FIFO_NOTEMPTY_RAW_INT_STATUS ((u32)0x00000001 << 1) /*Bit[1], bit for keyscan fifo not empty raw interrupt status*/ 331 #define BIT_KS_ALL_RELEASE_RAW_INT_STATUS ((u32)0x00000001) /*Bit[0], bit for keyscan all release raw interrupt status*/ 332 /** @} */ 333 334 /**************************************************************************//** 335 * @defgroup KS_DUMMY 336 * @{ 337 *****************************************************************************/ 338 #define BIT_DUMMY_H ((u32)0x00000001 << 8) /*Bit[15:8], bit for Dummy_h*/ 339 #define BIT_DUMMY_L ((u32)0x00000001 << 2) /*Bit[7:2], bit for Dummy_l*/ 340 #define BIT_KS_DISCHARGE ((u32)0x00000001 << 1) /*Bit[1], bit for discharge the column spurious capacitance,1 for enable discharge*/ 341 #define BIT_KS_INTERVAL_POLARITY ((u32)0x00000001) /*Bit[0], bit for configure the column polarity in debounce and interval phase,1 for drive low*/ 342 /** @} */ 343 /** @} */ 344 345 /** 346 * @} 347 */ 348 349 /** 350 * @} 351 */ 352 353 /* Other Definitions --------------------------------------------------------*/ 354 355 356 #endif 357 358 /******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/ 359