1 /**
2   ******************************************************************************
3   * @file    rtl8721d_sdio.h
4   * @author
5   * @version V1.0.0
6   * @date    2016-05-17
7   * @brief   This file contains all the functions prototypes for the SDIO firmware
8   *          library.
9   ******************************************************************************
10   * @attention
11   *
12   * This module is a confidential and proprietary property of RealTek and
13   * possession or use of this module requires written permission of RealTek.
14   *
15   * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved.
16   ******************************************************************************
17   */
18 
19 #ifndef _RTL8710B_SDIO_H_
20 #define _RTL8710B_SDIO_H_
21 
22 /** @addtogroup AmebaD_Periph_Driver
23   * @{
24   */
25 
26 /** @defgroup SDIO
27   * @brief SDIO driver modules
28   * @{
29   */
30 
31 /* Exported Types --------------------------------------------------------*/
32 /** @defgroup SDIO_Exported_Types SDIO Exported Types
33   * @{
34   */
35 /**
36   * @brief	 SDIO Init structure definition
37   */
38 typedef struct {
39 	/* TXBD */
40 	u32 TXBD_BAR;			/*!< Specifies TXBD base address */
41 	u32 TXBD_RING_SIZE; 	/*!< Specifies TXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
42 	u32 TX_BUFFER_SIZE; 	/*!< Specifies TX buffer size, This parameter must be set to a value in the 0-0xFF range. */
43 
44 	/* RXBD */
45 	u32 RXBD_BAR;			/*!< Specifies RXBD base address */
46 	u32 RXBD_RING_SIZE; 	/*!< Specifies RXBD ring size, This parameter must be set to a value in the 0-0xFFFF range. */
47 	u32 RXBD_FREE_TH;		/*!< the threshold of free RX BD count to trigger interrupt */
48 } SDIO_InitTypeDef;
49 /**
50   * @}
51   */
52 
53 /* Exported constants --------------------------------------------------------*/
54 
55 /** @defgroup SDIO_Exported_Constants SDIO Exported Constants
56   * @{
57   */
58 
59 /** @defgroup SDIO_MP_CMD_definitions The SDIO MP CMD definations
60   * @{
61   */
62 #define SDIO_MP_START			1
63 #define SDIO_MP_STOP			2
64 #define SDIO_MP_LOOPBACK		3
65 #define SDIO_MP_STATUS			4
66 #define SDIO_MP_READ_REG8		5
67 #define SDIO_MP_READ_REG16	6
68 #define SDIO_MP_READ_REG32	7
69 #define SDIO_MP_WRITE_REG8	8
70 #define SDIO_MP_WRITE_REG16	9
71 #define SDIO_MP_WRITE_REG32	10
72 #define SDIO_MP_WAKEUP		11	// wakeup the SDIO task manually, for debugging
73 #define SDIO_MP_DUMP			12    // start/stop to dump the SDIO status periodically
74 #define SDIO_MP_CTX				13     // setup continue TX test
75 #define SDIO_MP_CRX				14     // setup continue RX test
76 #define SDIO_MP_CRX_DA			15    // setup continue RX with dynamic allocate RX Buf test
77 #define SDIO_MP_CRX_STOP		16    // setup continue RX test
78 #define SDIO_MP_DBG_MSG		17    // Debug message On/Off
79 /**
80   * @}
81   */
82 
83 
84 /** @defgroup SDIO_RPWM_definitions The SDIO RPWM definations
85   * @{
86   */
87 #define RPWM2_ACT_BIT			(0x00000001 << 0)     // Active
88 #define RPWM2_SLEEP_BIT		0        // Sleep
89 #define RPWM2_DSTANDBY_BIT	(0x00000001 << 1)     // Deep Standby
90 #define RPWM2_PG_BIT			0        // Power Gated
91 #define RPWM2_FBOOT_BIT		(0x00000001 << 2)     // fast reboot
92 #define RPWM2_NBOOT_BIT		0        // normal reboot
93 #define RPWM2_WKPIN_0_BIT		(0x00000001 << 3)     // enable GPIO wakeup pin 0
94 #define RPWM2_WKPIN_1_BIT		(0x00000001 << 4)     // enable GPIO wakeup pin 1
95 #define RPWM2_WKPIN_2_BIT		(0x00000001 << 5)     // enable GPIO wakeup pin 2
96 #define RPWM2_WKPIN_3_BIT		(0x00000001 << 6)     // enable GPIO wakeup pin 3
97 #define RPWM2_WKPIN_0_LV_BIT	(0x00000001 << 7)     // GPIO wakeup pin 0 wakeup level
98 #define RPWM2_WKPIN_1_LV_BIT	(0x00000001 << 8)     // GPIO wakeup pin 1 wakeup level
99 #define RPWM2_WKPIN_2_LV_BIT	(0x00000001 << 9)     // GPIO wakeup pin 2 wakeup level
100 #define RPWM2_WKPIN_3_LV_BIT	(0x00000001 << 10)    // GPIO wakeup pin 3 wakeup level
101 #define RPWM2_CG_BIT			(0x00000001 << 11)    // Clock Gated
102 #define RPWM2_ACK_BIT			(0x00000001 << 14)    // Acknowledge
103 #define RPWM2_TOGGLE_BIT		(0x00000001 << 15)    // Toggle bit
104 /**
105   * @}
106   */
107 
108 /** @defgroup SDIO_CPWM2_definitions The SDIO CPWM2 definations
109   * @{
110   */
111 #define CPWM2_ACT_BIT			(0x00000001 << 0)     // Active
112 #define CPWM2_DSTANDBY_BIT	(0x00000001 << 1)     // Deep Standby
113 #define CPWM2_FBOOT_BIT		(0x00000001 << 2)     // fast reboot
114 #define CPWM2_INIC_FW_RDY_BIT	(0x00000001 << 3)     // is the iNIC FW(1) or Boot FW(0)
115 #define CPWM2_TOGGLE_BIT		(0x00000001 << 15)    // Toggle bit
116 /**
117   * @}
118   */
119 
120 /** @defgroup SDIO_CPWM1_definitions The SDIO CPWM1 definations
121   * @{
122   */
123 #define CPWM1_TOGGLE_BIT		(0x00000001 << 7)    // Toggle bit
124 /**
125   * @}
126   */
127 
128 /** @defgroup SDIO_EVENT_definitions The SDIO EVENT definations
129   * @{
130   */
131 #define SDIO_EVENT_RX_PKT_RDY			(0x00000001 << 1)		// A new SDIO packet ready
132 #define SDIO_EVENT_DUMP                           (0x00000001 << 3)      // SDIO status dump periodically Enable
133 #define SDIO_EVENT_EXIT					(0x00000001 << 27)		// Request to exit the SDIO task
134 #define SDIO_EVENT_MP_STOPPED			(0x00000001 << 28)		// The SDIO task is stopped
135 #define SDIO_EVENT_IRQ_STOPPED		(0x00000001 << 29)		// The SDIO task is stopped
136 #define SDIO_EVENT_TX_STOPPED			(0x00000001 << 30)		// The SDIO task is stopped
137 #define SDIO_EVENT_RX_STOPPED			(0x00000001 << 31)		// The SDIO task is stopped
138 /**
139   * @}
140   */
141 
142 /**
143   * @}
144   */
145 
146 /** @defgroup SDIO_Exported_Functions SDIO Exported Functions
147   * @{
148   */
149 _LONG_CALL_ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
150 _LONG_CALL_ void SDIO_Init(SDIO_InitTypeDef* SDIOInit_Struct);
151 _LONG_CALL_ void SDIO_INTClear(void);
152 _LONG_CALL_ VOID SDIO_INTConfig(u16 IntMask, u32 NewState);
153 _LONG_CALL_ u8 SDIO_RPWM1_Get(void);
154 _LONG_CALL_ u16 SDIO_RPWM2_Get(void);
155 _LONG_CALL_ void SDIO_CPWM1_Set(u8 Val);
156 _LONG_CALL_ void SDIO_CPWM2_Set(u16 Val, u32 Newstate);
157 _LONG_CALL_ u16 SDIO_RXBD_RPTR_Get(void);
158 _LONG_CALL_ void SDIO_RXBD_WPTR_Set(u16 Val);
159 _LONG_CALL_ u16 SDIO_TXBD_WPTR_Get(void);
160 _LONG_CALL_ void SDIO_TXBD_RPTR_Set(u16 Val);
161 _LONG_CALL_ void SDIO_DMA_Reset(void);
162 /**
163   * @}
164   */
165 
166 /**
167   * @}
168   */
169 /**
170   * @}
171   */
172 
173 #define HAL_SDIO_READ32(addr)            			HAL_READ32(SDIO_DEVICE_REG_BASE, addr)
174 #define HAL_SDIO_WRITE32(addr, value)    			HAL_WRITE32(SDIO_DEVICE_REG_BASE, addr, value)
175 #define HAL_SDIO_READ16(addr)					HAL_READ16(SDIO_DEVICE_REG_BASE, addr)
176 #define HAL_SDIO_WRITE16(addr, value)    			HAL_WRITE16(SDIO_DEVICE_REG_BASE, addr, value)
177 #define HAL_SDIO_READ8(addr)					HAL_READ8(SDIO_DEVICE_REG_BASE, addr)
178 #define HAL_SDIO_WRITE8(addr, value)    			HAL_WRITE8(SDIO_DEVICE_REG_BASE, addr, value)
179 
180 /* Registers Definitions --------------------------------------------------------*/
181 #define REG_SPDIO_TXBD_ADDR 						0xA0       // 4 Bytes
182 #define REG_SPDIO_TXBD_SIZE						0xA4       // 4 Bytes
183 #define REG_SPDIO_TXBD_WPTR						0xA8       // 2 Bytes
184 #define REG_SPDIO_TXBD_RPTR						0xAC       // 2 Bytes
185 #define REG_SPDIO_RXBD_ADDR						0xB0	// 4 Bytes
186 #define REG_SPDIO_RXBD_SIZE						0xB4	// 2 Bytes
187 #define REG_SPDIO_RXBD_C2H_WPTR					0xB6	// 2 Bytes
188 #define REG_SPDIO_RXBD_C2H_RPTR					0xB8	// 2 Bytes
189 #define REG_SPDIO_HCI_RX_REQ						0xBA	// 1 Byte
190 #define REG_SPDIO_CPU_RST_DMA						0xBB	// 1 Byte
191 #define REG_SPDIO_RX_REQ_ADDR						0xBC	// 2 Bytes
192 #define REG_SPDIO_CPU_INT_MASK					0xC0	// 2 Bytes
193 #define REG_SPDIO_CPU_INT_STAS					0xC2	// 2 Bytes
194 #define REG_SPDIO_CCPWM							0xC4	// 1 Byts
195 #define REG_SPDIO_CPU_IND							0xC5	// 1 Byte
196 #define REG_SPDIO_CCPWM2							0xC6	// 2 Bytes
197 #define REG_SPDIO_CPU_H2C_MSG						0xC8	// 4 Bytes
198 #define REG_SPDIO_CPU_C2H_MSG						0xCC	// 4 Bytes
199 #define REG_SPDIO_CRPWM							0xD0	// 1 Bytes
200 #define REG_SPDIO_CRPWM2							0xD2	// 2 Bytes
201 #define REG_SPDIO_AHB_DMA_CTRL					0xD4	// 4 Bytes
202 #define REG_SPDIO_RXBD_CNT					        	0xD8	// 4 Bytes
203 #define REG_SPDIO_TX_BUF_UNIT_SZ			        	0xD9	// 1 Bytes
204 #define REG_SPDIO_RX_BD_FREE_CNT			        	0xDA	// 2 Bytes
205 #define REG_SPDIO_CPU_H2C_MSG_EXT				0xDC	// 4 Bytes
206 #define REG_SPDIO_CPU_C2H_MSG_EXT				0xE0	// 4 Bytes
207 
208 /********************  Bits definition for REG_SPDIO_CPU_RST_DMA register  *******************/
209 #define BIT_CPU_RST_SDIO_DMA						BIT(7)
210 
211 /********************  Bits definition for REG_SPDIO_CPU_INT_MASK/REG_SPDIO_CPU_INT_STAS register  *******************/
212 #define BIT_TXFIFO_H2C_OVF							BIT(0)
213 #define BIT_H2C_BUS_RES_FAIL						BIT(1)
214 #define BIT_H2C_DMA_OK								BIT(2)
215 #define BIT_C2H_DMA_OK								BIT(3)
216 #define BIT_H2C_MSG_INT								BIT(4)
217 #define BIT_RPWM1_INT								BIT(5)
218 #define BIT_RPWM2_INT								BIT(6)
219 #define BIT_SDIO_RST_CMD_INT						BIT(7)
220 #define BIT_RXBD_FLAG_ERR_INT						BIT(8)
221 #define BIT_RX_BD_AVAI_INT							BIT(9)
222 #define BIT_HOST_WAKE_CPU_INT						BIT(10)
223 
224 #define SDIO_INIT_INT_MASK							(BIT_H2C_DMA_OK | BIT_C2H_DMA_OK | \
225 													BIT_H2C_MSG_INT | BIT_RPWM1_INT | \
226 													BIT_RPWM2_INT |BIT_H2C_BUS_RES_FAIL | \
227 													BIT_RXBD_FLAG_ERR_INT)
228 /********************  Bits definition for REG_SPDIO_CPU_IND register  *******************/
229 #define BIT_SYSTEM_TRX_RDY_IND						BIT(0)
230 
231 /********************  Bits definition for REG_SPDIO_HCI_RX_REQ register  *******************/
232 #define BIT_HCI_RX_REQ								BIT(0)
233 
234 #endif	/* #ifndef _RTL8710B_SDIO_H_ */
235