1 #ifndef __INC_RTL8711B_WL_ON_H 2 #define __INC_RTL8711B_WL_ON_H 3 4 /* this is a subset of hal_com_reg.h */ 5 6 /* BIT_WL_PMC_OFFMAC 0x0020 */ 7 #define BIT_WL_PMC_OFFMAC (0x00000001 << 1) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only 8 (auto set by ICFG, and clear when Power Ready) */ 9 #define BIT_WL_APMC_ONMAC (0x00000001 << 0) /*!< Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 10 11 /* REG_WL_RF_PSS 0x005c */ 12 #define BIT_AFE_POWER_MODE_SEL (0x00000001 << 8) /*!< AFE power mode selection:1: LDO mode 0: Power-cut mode */ 13 #define BIT_SEL_LDO_RF (0x00000001 << 2) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33PAD); 0: Power Cut mode (Power source is 1.2V,VDTR). */ 14 #define BIT_SEL_LDO_SYN (0x00000001 << 1) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */ 15 #define BIT_SEL_LDO_BUF (0x00000001 << 0) /*!< Power source selection1: LDO mode (power source is 3.3V,VD33SYN); 0: Power Cut mode (Power source is 1.2V,VDSYN). */ 16 17 /* REG_USB_INDIRECT_CTRL 0x006c */ 18 #define BIT_USB_HOST_INT_REQ (0x00000001 << 31) /*!< For USB doggle mode, USB Host write this bit to 1 will trigger interrupt to CM4. After CM4 finishes handling this interrupt , CM4 will clear this bit to 0 */ 19 //#define BIT_USB_HOST_INT_TYPE (0x00000001 << 30) /*!< 0: read efuse, 1: write efuse, 2: host cmd */ 20 #define BIT_USB_HOST_CMD (0x0000001F << 24) /*!< host cmd val */ 21 22 /* REG_USB_SIE_IMR 0x0078 */ 23 #define BIT_EFUSE_RD_MSK_CM4 (0x00000001 << 23) /*!< USB host indirect read efuse interrupt mask for cm4 */ 24 #define BIT_USB_SUS_MSK_CM4 (0x00000001 << 22) /*!< USB suspend interrupt mask for cm4 */ 25 #define BIT_USB_RES_MSK_CM4 (0x00000001 << 21) /*!< USB resume interrupt mask for cm4 */ 26 #define BIT_SE0_RST_MSK_CM4 (0x00000001 << 20) /*!< SE0 reset interrupt mask for cm4 */ 27 #define BIT_SIE_ACK_DONE_MSK_CM4 (0x00000001 << 19) /*!< SIE ACK done interrupt mask for cm4 */ 28 #define BIT_SIE_NAK_DONE_MSK_CM4 (0x00000001 << 18) /*!< SIE NAK done interrupt mask for cm4 */ 29 #define BIT_LPM_RSM_MSK_CM4 (0x00000001 << 17) /*!< SIE resume from LPM interrupt mask for cm4 */ 30 #define BIT_LPM_ACT_MSK_CM4 (0x00000001 << 16) /*!< SIE enter LPM interrupt mask for cm4 */ 31 #define BIT_EFUSE_RD_MSK_DW8051 (0x00000001 << 7) /*!< USB host indirect read efuse interrupt mask for dw8051 */ 32 #define BIT_USB_SUS_MSK_DW8051 (0x00000001 << 6) /*!< USB suspend interrupt mask for dw8051 */ 33 #define BIT_USB_RES_MSK_DW8051 (0x00000001 << 5) /*!< USB resume interrupt mask for dw8051 */ 34 #define BIT_SE0_RST_MSK_DW8051 (0x00000001 << 4) /*!< SE0 reset interrupt mask for dw8051 */ 35 #define BIT_SIE_ACK_DONE_MSK_DW8051 (0x00000001 << 3) /*!< SIE ACK done interrupt mask for dw8051 */ 36 #define BIT_SIE_NAK_DONE_MSK_DW8051 (0x00000001 << 2) /*!< SIE NAK done interrupt mask for dw8051 */ 37 #define BIT_LPM_RSM_MSK_DW8051 (0x00000001 << 1) /*!< SIE resume from LPM interrupt mask for dw8051 */ 38 #define BIT_LPM_ACT_MSK_DW8051 (0x00000001 << 0) /*!< SIE enter LPM interrupt mask for dw8051 */ 39 40 /* REG_USB_SIE_INT 0x007c */ 41 #define BIT_USB_CMD_INT ((u32)(0x00000001 << 7)) /*!< USB host indirect read/write efuse or host cmd interrupt */ 42 #define BIT_USB_SUS_INT ((u32)(0x00000001 << 6)) /*!< USB suspend interrupt */ 43 #define BIT_USB_RES_INT ((u32)(0x00000001 << 5)) /*!< USB resume interrupt */ 44 #define BIT_SE0_RST_INT ((u32)(0x00000001 << 4)) /*!< SE0 reset interrupt */ 45 #define BIT_SIE_ACK_DONE_INT ((u32)(0x00000001 << 3)) /*!< SIE ACK done interrupt */ 46 #define BIT_SIE_NAK_DONE_INT ((u32)(0x00000001 << 2)) /*!< SIE NAK done interrupt */ 47 #define BIT_LPM_RSM_INT ((u32)(0x00000001 << 1)) /*!< SIE resume from LPM interrupt */ 48 #define BIT_LPM_ACT_INT ((u32)(0x00000001 << 0)) /*!< IE enter LPM interrupt */ 49 50 /* REG_USB_PWR_OPT 0x0088 */ 51 #define BIT_CM4_WAKE_USB ((u32)(0x00000001 << 6)) /*!< R/W 0 cm4 wakeup usb device, 1: wakeup 0: not wakeup */ 52 #define BIT_HOST_WAKE_DEV_EN ((u32)(0x00000001 << 5)) /*!< R/W 0 usb host wake device function enable, 1: Enable, 0:Disable */ 53 #define BIT_HOST_WAKE_DEV ((u32)(0x00000001 << 4)) /*!< R/W 0 usb host wake device, 1: wake */ 54 #define BIT_USB_LPS_BLOCK ((u32)(0x00000001 << 3)) /*!< R/W 0 Block USB RX for wlan is in LPS, 1: Block RX ; 0: Not block */ 55 #define BIT_USB_LPM_NY ((u32)(0x00000001 << 2)) /*!< R/W 0 USB LPM Not Yet */ 56 #define BIT_USB_SUS_DIS ((u32)(0x00000001 << 1)) /*!< R/W 0 Disable USB enter suspend, 1: Disable, 0: enable */ 57 #define BIT_USB_LPMACT_EN ((u32)(0x00000001 << 0)) /*!< R/W 0 Enable USB enter LPM , 1: Enable, 0: Disable */ 58 59 /* REG_SYS_CFG_8710B 0xF0 */ 60 #define BIT_USB_DOGGLE_MODE ((u32)(0x00000001 << 1)) /*!< 1: enable usb host access wifi mac, this bit should set by host driver */ 61 #define BIT_MCLK_VLD ((u32)(0x00000001 << 0)) /*!< 1: MAC clock ready flag */ 62 63 64 #define REG_WL_PMC_CTRL 0x0020 65 66 #define REG_WL_RF_PSS 0x005C /*!< select RF power source: LDO:3.3V, PC: 1.2V*/ 67 68 #define REG_SYS_CFG_8710B 0x00F0 69 70 #define REG_USB_INDIRECT_CTRL 0x006C 71 #define REG_USB_SIE_IMR 0x0078 72 #define REG_USB_SIE_INT 0x007c 73 #define REG_WL_PMC_ISR_8711B 0x0084 74 #define REG_USB_PWR_OPT 0x0088 75 76 #define REG_USB_HOST_RW_DATA 0x009C 77 #define REG_USB_HOST_RW_ADDR 0x00F8 78 #endif //__INC_RTL8711B_WL_ON_H