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Searched refs:CACHE_LINE_SIZE (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/crypto/
A Drtl8721dhp_crypto_ram.c704 u8 cache_buf[CACHE_LINE_SIZE] = {0}; in CRYPTO_Cache_Sync()
718 memcpy(cache_buf, (u8 *)(start_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
720 DCache_Invalidate((start_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
728 memcpy((cache_buf + header_offset), (u8 *)(start_addr), (CACHE_LINE_SIZE - header_offset)); in CRYPTO_Cache_Sync()
731 memcpy((u8 *)(start_addr & CACHE_LINE_ADDR_MSK), cache_buf, CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
733 DCache_Clean((start_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
739 memcpy(cache_buf, (u8 *)(end_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
741 DCache_Invalidate((end_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
745 memcpy((u8 *)(end_addr & CACHE_LINE_ADDR_MSK), cache_buf, CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
747 DCache_Clean((end_addr & CACHE_LINE_ADDR_MSK), CACHE_LINE_SIZE); in CRYPTO_Cache_Sync()
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721d_cache.h61 #define CACHE_LINE_SIZE 32 macro

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