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Searched refs:CKGEN_CTL (Results 1 – 2 of 2) sorted by relevance

/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/ram_hp/
A Drtl8721dhp_sdio_host.c421 value32 = psdioh->CKGEN_CTL; in SDIOH_SwitchSpeed()
424 psdioh->CKGEN_CTL = value32; in SDIOH_SwitchSpeed()
450 psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \ in SDIOH_InitialModeCmd()
460 psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \ in SDIOH_InitialModeCmd()
467 psdioh->CKGEN_CTL = SDIOH_SD30_SAMP_CLK_VP1 | SDIOH_SD30_PUSH_CLK_VP0 | \ in SDIOH_InitialModeCmd()
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Dhal_platform.h1385 __IO uint32_t CKGEN_CTL; /*!< Clock Generation Control Register, Address offset: 0x00000478*/ member

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