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Searched refs:DATA_CACHE (Results 1 – 11 of 11) sorted by relevance

/AliOS-Things-master/components/csi/csi1/include/core/
A Dcore_ck807.h441 #define DATA_CACHE (1 << 1) macro
551 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
562 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
572 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
609 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
621 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
633 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_810.h467 #define DATA_CACHE (1 << 1) macro
577 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
588 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
598 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
635 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
647 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
659 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck810.h448 #define DATA_CACHE (1 << 1) macro
558 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
569 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
579 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
616 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
628 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
640 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck610.h467 #define DATA_CACHE (1 << 1) macro
571 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
582 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
593 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
630 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
642 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
654 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_807.h995 #define DATA_CACHE (1 << 1) macro
1233 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
1244 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
1254 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
1291 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
1303 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
1315 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
/AliOS-Things-master/components/csi/csi2/include/core/
A Dcore_ck807.h441 #define DATA_CACHE (1 << 1) macro
551 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
562 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
572 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
609 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
621 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
633 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_810.h467 #define DATA_CACHE (1 << 1) macro
577 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
588 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
598 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
635 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
647 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
659 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck810.h448 #define DATA_CACHE (1 << 1) macro
558 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
569 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
579 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
616 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
628 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
640 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck610.h467 #define DATA_CACHE (1 << 1) macro
571 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
582 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
593 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
630 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
642 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
654 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_807.h995 #define DATA_CACHE (1 << 1) macro
1233 __set_CFR(DATA_CACHE | CACHE_INV); in csi_dcache_invalid()
1244 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
1254 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
1291 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_INV)); in csi_dcache_invalid_range()
1303 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
1315 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
/AliOS-Things-master/hardware/chip/rtl872xd/sdk/component/soc/realtek/amebad/fwlib/include/
A Drtl8721d_cache.h52 #define DATA_CACHE ((u32)0x00000000) macro

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