1 /**
2 ******************************************************************************
3 * @file rtl8721d_cache.h
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file contains all the functions prototypes for the flash cache firmware
8 * library.
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #ifndef _RTL8710B_CACHE_H_
20 #define _RTL8710B_CACHE_H_
21
22 /** @addtogroup AmebaD_Platform
23 * @{
24 */
25
26 /** @defgroup CACHE
27 * @brief CACHE modules
28 * @{
29 */
30
31 /** @addtogroup CACHE
32 * @verbatim
33 *****************************************************************************************
34 * Introduction
35 *****************************************************************************************
36 * -just support read cache.
37 * -32K bytes.
38 * -used for flash read and XIP.
39 *
40 *****************************************************************************************
41 * how to use
42 *****************************************************************************************
43 * Cache_Enable: enable/disable cache
44 * Cache_Flush: flush cache, you should Cache_Flush after flash write or flash erase
45 *****************************************************************************************
46 * @endverbatim
47 */
48
49 /** @defgroup CACHE_Type_define
50 * @{
51 */
52 #define DATA_CACHE ((u32)0x00000000)
53 #define CODE_CACHE ((u32)0x00000001)
54 /**
55 * @}
56 */
57
58 /** @defgroup CACHE_Line_Aligned_define
59 * @{
60 */
61 #define CACHE_LINE_SIZE 32
62 #define CACHE_LINE_ADDR_MSK 0xFFFFFFE0
63
64 #define IS_CACHE_LINE_ALIGNED_SIZE(BYTES) ((BYTES & 0x1F) == 0)
65 #define IS_CACHE_LINE_ALIGNED_ADDR(ADDR) ((ADDR & 0x1F) == 0)
66 /**
67 * @}
68 */
69
70 /* Exported functions --------------------------------------------------------*/
71 /** @defgroup CACHE_Exported_Functions FLash Cache Exported Functions
72 * @{
73 */
74 /**
75 * @brief Disable/Enable I/D cache.
76 * @param Enable
77 * This parameter can be any combination of the following values:
78 * @arg ENABLE cache enable & SPIC read 16bytes every read command
79 * @arg DISABLE cache disable & SPIC read 4bytes every read command
80 */
81 __STATIC_INLINE
Cache_Enable(u32 Enable)82 void Cache_Enable(u32 Enable)
83 {
84 if (Enable) {
85 SCB_EnableICache();
86 SCB_EnableDCache();
87 } else {
88 SCB_DisableICache();
89 SCB_DisableDCache();
90 }
91 }
92
93 /**
94 * @brief flush I/D cache.
95 */
96 __STATIC_INLINE
Cache_Flush(void)97 void Cache_Flush(void)
98 {
99 SCB_InvalidateICache();
100 SCB_InvalidateDCache();
101 }
102
103 /**
104 * @brief Enable Icache.
105 */
106 __STATIC_INLINE
ICache_Enable(void)107 void ICache_Enable(void)
108 {
109 SCB_EnableICache();
110 }
111
112 /**
113 * @brief Disable Icache.
114 */
115 __STATIC_INLINE
ICache_Disable(void)116 void ICache_Disable(void)
117 {
118 SCB_DisableICache();
119 }
120
121 /**
122 * @brief Invalidate Icache.
123 */
124 __STATIC_INLINE
ICache_Invalidate(void)125 void ICache_Invalidate(void)
126 {
127 SCB_InvalidateICache ();
128 }
129
130 /**
131 * @brief Check DCache Enabled or not.
132 */
133 __STATIC_INLINE
DCache_IsEnabled(void)134 u32 DCache_IsEnabled(void)
135 {
136 return ((SCB->CCR & (u32)SCB_CCR_DC_Msk)?1:0);
137 }
138
139 /**
140 * @brief Enable Dcache.
141 */
142 __STATIC_INLINE
DCache_Enable(void)143 void DCache_Enable(void)
144 {
145 SCB_EnableDCache();
146 }
147
148 /**
149 * @brief Disable Dcache.
150 */
151 __STATIC_INLINE
DCache_Disable(void)152 void DCache_Disable(void)
153 {
154 SCB_DisableDCache();
155 }
156
157 /**
158 * @brief D-Cache Invalidate by address.
159 * @details Invalidates D-Cache for the given address
160 * @param Address address (aligned to 32-byte boundary)
161 * @param Bytes size of memory block (in number of bytes)
162 *
163 * @note Dcache will be restored from memory.
164 * @note This can be used after DMA Rx, and CPU read DMA data from DMA buffer.
165 * @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be Invalidated.
166 */
167 __STATIC_INLINE
DCache_Invalidate(u32 Address,u32 Bytes)168 void DCache_Invalidate(u32 Address, u32 Bytes)
169 {
170 u32 addr = Address, len = Bytes;
171
172 if (DCache_IsEnabled() == 0)
173 return;
174
175 if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
176 SCB_InvalidateDCache();
177 } else {
178 if ((addr & 0x1F) != 0) {
179 addr = (Address >> 5) << 5; //32-byte aligned
180 len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
181 }
182
183 SCB_InvalidateDCache_by_Addr((u32*)addr, len);
184 }
185 }
186
187 /**
188 * @brief D-Cache Clean by address
189 * @details Cleans D-Cache for the given address
190 * @param Address address (aligned to 32-byte boundary)
191 * @param Bytes size of memory block (in number of bytes)
192 *
193 * @note Dcache will be write back to memory.
194 * @note This can be used before DMA Tx, after CPU write data to DMA buffer.
195 * @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be cleaned.
196 * @note AmebaD cache is default read allocation and write through, so clean is not needed.
197 */
198 __STATIC_INLINE
DCache_Clean(u32 Address,u32 Bytes)199 void DCache_Clean(u32 Address, u32 Bytes)
200 {
201 u32 addr = Address, len = Bytes;
202
203 if (DCache_IsEnabled() == 0)
204 return;
205
206 if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
207 SCB_CleanDCache();
208 } else {
209 if ((addr & 0x1F) != 0) {
210 addr = (Address >> 5) << 5; //32-byte aligned
211 len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
212 }
213
214 SCB_CleanDCache_by_Addr((u32*)addr, len);
215 }
216 }
217
218
219 /**
220 * @brief D-Cache Clean and Invalidate by address
221 * @details Cleans and invalidates D_Cache for the given address
222 * @param Address address (aligned to 32-byte boundary)
223 * @param Bytes size of memory block (in number of bytes)
224 *
225 * @note This can be used when you want to write back cache data and then Invalidate cache.
226 * @note if Address is 0xFFFFFFFF, it means dont care, it was used when all Dcache be cleaned.
227 */
228 __STATIC_INLINE
DCache_CleanInvalidate(u32 Address,u32 Bytes)229 void DCache_CleanInvalidate(u32 Address, u32 Bytes)
230 {
231 u32 addr = Address, len = Bytes;
232
233 if (DCache_IsEnabled() == 0)
234 return;
235
236 if ((Address == 0xFFFFFFFF) && (Bytes == 0xFFFFFFFF)) {
237 SCB_CleanInvalidateDCache();
238 } else {
239 if ((addr & 0x1F) != 0) {
240 addr = (Address >> 5) << 5; //32-byte aligned
241 len = ((((Address + Bytes -1) >> 5) + 1) << 5) - addr; //next 32-byte aligned
242 }
243
244 SCB_CleanInvalidateDCache_by_Addr((u32*)addr, len);
245 }
246 }
247 /**
248 * @}
249 */
250
251 /**
252 * @}
253 */
254
255 /**
256 * @}
257 */
258 #endif //_RTL8710B_CACHE_H_
259 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
260