1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __REG_DMA_H__ 5 #define __REG_DMA_H__ 6 7 #include "plat_types.h" 8 #include "stdint.h" 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 // Number of channels on GPDMA and AUDMA 15 #define DMA_NUMBER_CHANNELS 8 16 17 // DMA Channel register block structure 18 struct DMA_CH_T { 19 __IO uint32_t SRCADDR; // 0x100+N*0x20 DMA Channel Source Address Register 20 __IO uint32_t DSTADDR; // 0x104+N*0x20 DMA Channel Destination Address Register 21 __IO uint32_t LLI; // 0x108+N*0x20 DMA Channel Linked List Item Register 22 __IO uint32_t CONTROL; // 0x10C+N*0x20 DMA Channel Control Register 23 __IO uint32_t CONFIG; // 0x110+N*0x20 DMA Channel Configuration Register 24 uint32_t RESERVED1[3]; // 0x114+N*0x20 25 }; 26 27 struct DMA_2D_CFG_T { 28 __IO uint32_t SRCX; // 0x200+N*0x20 DMA 2D Source X Axis Register 29 __IO uint32_t SRCY; // 0x204+N*0x20 DMA 2D Source Y Axis Register 30 __IO uint32_t DSTX; // 0x208+N*0x20 DMA 2D Destination X Axis Register 31 __IO uint32_t DSTY; // 0x20C+N*0x20 DMA 2D Destination Y Axis Register 32 __IO uint32_t CTRL; // 0x210+N*0x20 DMA 2D Control Register 33 uint32_t RESERVED2[3]; // 0x214+N*0x20 34 }; 35 36 // DMA register block 37 struct DMA_T { 38 __I uint32_t INTSTAT; // 0x000 DMA Interrupt Status Register 39 __I uint32_t INTTCSTAT; // 0x004 DMA Interrupt Terminal Count Request Status Register 40 __O uint32_t INTTCCLR; // 0x008 DMA Interrupt Terminal Count Request Clear Register 41 __I uint32_t INTERRSTAT; // 0x00C DMA Interrupt Error Status Register 42 __O uint32_t INTERRCLR; // 0x010 DMA Interrupt Error Clear Register 43 __I uint32_t RAWINTTCSTAT; // 0x014 DMA Raw Interrupt Terminal Count Status Register 44 __I uint32_t RAWINTERRSTAT; // 0x018 DMA Raw Error Interrupt Status Register 45 __I uint32_t ENBLDCHNS; // 0x01C DMA Enabled Channel Register 46 __IO uint32_t SOFTBREQ; // 0x020 DMA Software Burst Request Register 47 __IO uint32_t SOFTSREQ; // 0x024 DMA Software Single Request Register 48 __IO uint32_t SOFTLBREQ; // 0x028 DMA Software Last Burst Request Register 49 __IO uint32_t SOFTLSREQ; // 0x02C DMA Software Last Single Request Register 50 __IO uint32_t DMACONFIG; // 0x030 DMA Configuration Register 51 __IO uint32_t SYNC; // 0x034 DMA Synchronization Register 52 uint32_t RESERVED0[50]; // 0x038 53 struct DMA_CH_T CH[DMA_NUMBER_CHANNELS]; // 0x100 54 struct DMA_2D_CFG_T _2D[DMA_NUMBER_CHANNELS]; // 0x200 55 }; 56 57 // Macro defines for DMA channel control registers 58 59 #define DMA_CONTROL_TRANSFERSIZE(n) ((((n) & 0xFFF) << 0)) // Transfer size 60 #define DMA_CONTROL_TRANSFERSIZE_MASK (0xFFF << 0) 61 #define DMA_CONTROL_TRANSFERSIZE_SHIFT (0) 62 #define DMA_CONTROL_SBSIZE(n) ((((n) & 0x07) << 12)) // Source burst size 63 #define DMA_CONTROL_DBSIZE(n) ((((n) & 0x07) << 15)) // Destination burst size 64 #define DMA_CONTROL_SWIDTH(n) ((((n) & 0x07) << 18)) // Source transfer width 65 #define DMA_CONTROL_SWIDTH_MASK (0x07 << 18) 66 #define DMA_CONTROL_SWIDTH_SHIFT (18) 67 #define DMA_CONTROL_DWIDTH(n) ((((n) & 0x07) << 21)) // Destination transfer width 68 #define DMA_CONTROL_SI ((1UL << 26)) // Source increment 69 #define DMA_CONTROL_DI ((1UL << 27)) // Destination increment 70 #define DMA_CONTROL_SRCAHB1 0 71 #define DMA_CONTROL_DSTAHB1 0 72 #define DMA_CONTROL_PROT1 ((1UL << 28)) // Indicates that the access is in user mode or privileged mode 73 #define DMA_CONTROL_PROT2 ((1UL << 29)) // Indicates that the access is bufferable or not bufferable 74 #define DMA_CONTROL_PROT3 ((1UL << 30)) // Indicates that the access is cacheable or not cacheable 75 #define DMA_CONTROL_TC_IRQ ((1UL << 31)) // Terminal count interrupt enable bit 76 77 // Macro defines for DMA Channel Configuration registers 78 79 #define DMA_CONFIG_EN ((1UL << 0)) // DMA control enable 80 #define DMA_CONFIG_SRCPERIPH(n) ((((n) & 0x1F) << 1)) // Source peripheral 81 #define DMA_CONFIG_DSTPERIPH(n) ((((n) & 0x1F) << 6)) // Destination peripheral 82 #define DMA_CONFIG_TRANSFERTYPE(n) ((((n) & 0x7) << 11)) // This value indicates the type of transfer 83 #define DMA_CONFIG_ERR_IRQMASK ((1UL << 14)) // Interrupt error mask 84 #define DMA_CONFIG_TC_IRQMASK ((1UL << 15)) // Terminal count interrupt mask 85 #define DMA_CONFIG_LOCK ((1UL << 16)) // Lock 86 #define DMA_CONFIG_ACTIVE ((1UL << 17)) // Active 87 #define DMA_CONFIG_HALT ((1UL << 18)) // Halt 88 #define DMA_CONFIG_TRY_BURST ((1UL << 19)) // Try burst 89 90 #define DMA_STAT_CHAN(n) ((1 << (n)) & 0xFF) 91 #define DMA_STAT_CHAN_ALL (0xFF) 92 93 // Macro defines for DMA Configuration register 94 95 #define DMA_DMACONFIG_EN (1 << 0) // DMA Controller enable 96 #define DMA_DMACONFIG_AHB1_BIGENDIAN (1 << 1) // AHB Master endianness configuration 97 #define DMA_DMACONFIG_AHB2_BIGENDIAN (1 << 2) // AHB Master endianness configuration 98 99 #define DMA_DMACONFIG_TC_IRQ_EN(n) (((n) & 0xFF) << 4) 100 #define DMA_DMACONFIG_TC_IRQ_EN_MASK (0xFF << 4) 101 #define DMA_DMACONFIG_TC_IRQ_EN_SHIFT (4) 102 103 // Macro defines for DMA 2D Configuration registers 104 105 #define DMA_2D_MODIFY_SHIFT 11 106 #define DMA_2D_MODIFY_MASK (0x1FFFFF << DMA_2D_MODIFY_SHIFT) 107 #define DMA_2D_MODIFY(n) BITFIELD_VAL(DMA_2D_MODIFY, n) 108 #define DMA_2D_COUNT_SHIFT 0 109 #define DMA_2D_COUNT_MASK (0x7FF << DMA_2D_COUNT_SHIFT) 110 #define DMA_2D_COUNT(n) BITFIELD_VAL(DMA_2D_COUNT, n) 111 112 #define DMA_2D_CTRL_DST_EN (1 << 1) 113 #define DMA_2D_CTRL_SRC_EN (1 << 0) 114 115 #ifdef __cplusplus 116 } 117 #endif 118 119 #endif 120 121