1 /*
2  * Copyright (C) 2015-2020 Alibaba Group Holding Limited
3  */
4 #ifndef __REG_TIMER_H_
5 #define __REG_TIMER_H_
6 
7 #include "plat_types.h"
8 
9 /* ================================================================================ */
10 /* ================                   Timer (TIM)                  ================ */
11 /* ================================================================================ */
12 struct DUAL_TIMER_T {
13     struct TIMER_T {
14         __IO uint32_t Load;       /* Offset: 0x000 (R/W)  Timer X Load */
15         __I  uint32_t Value;      /* Offset: 0x004 (R/ )  Timer X Counter Current Value */
16         __IO uint32_t Control;    /* Offset: 0x008 (R/W)  Timer X Control */
17         __O  uint32_t IntClr;     /* Offset: 0x00C ( /W)  Timer X Interrupt Clear */
18         __I  uint32_t RIS;        /* Offset: 0x010 (R/ )  Timer X Raw Interrupt Status */
19         __I  uint32_t MIS;        /* Offset: 0x014 (R/ )  Timer X Masked Interrupt Status */
20         __IO uint32_t BGLoad;     /* Offset: 0x018 (R/W)  Background Load Register */
21              uint32_t RESERVED0[1];
22     } timer[2];
23     struct ELAPSED_TIMER_T {
24         __IO uint32_t ElapsedCtrl;
25         __I  uint32_t ElapsedVal;
26              uint32_t RESERVED1[6];
27     } elapsed_timer[2];
28 };
29 
30 #define TIMER_CTRL_EN                   (1 << 7)
31 #define TIMER_CTRL_MODE_PERIODIC        (1 << 6)
32 #define TIMER_CTRL_INTEN                (1 << 5)
33 #define TIMER_CTRL_PRESCALE_DIV_1       (0 << 2)
34 #define TIMER_CTRL_PRESCALE_DIV_16      (1 << 2)
35 #define TIMER_CTRL_PRESCALE_DIV_256     (2 << 2)
36 #define TIMER_CTRL_PRESCALE_MASK        (3 << 2)
37 #define TIMER_CTRL_SIZE_32_BIT          (1 << 1)
38 #define TIMER_CTRL_ONESHOT              (1 << 0)
39 
40 #define TIMER_RIS_RIS                   (1 << 0)
41 
42 #define TIMER_MIS_MIS                   (1 << 0)
43 
44 #define TIMER_ELAPSED_CTRL_EN           (1 << 0)
45 #define TIMER_ELAPSED_CTRL_CLR          (1 << 1)
46 
47 #endif
48 
49