1 /** 2 ****************************************************************************** 3 * @file rtl8721d_flash.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the Flash firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8710B_SPI_FLASH_H 20 #define _RTL8710B_SPI_FLASH_H 21 22 #include "rtl8721d_flashclk.h" 23 24 /** @addtogroup AmebaD_Periph_Driver 25 * @{ 26 */ 27 28 /** @defgroup FLASH 29 * @brief SPI Flash driver modules 30 * @{ 31 */ 32 33 /** @addtogroup FLASH 34 * @verbatim 35 ***************************************************************************************** 36 * Introduction 37 ***************************************************************************************** 38 * SPI_Flash_Controller is used to communicate with SPI_Flash. 39 * Support auto mode and user mode to access Flash. 40 * Support multi-channel(1/2/4)data bit to transmit/receive. 41 * Programmable feature: 42 * SPI channel number - Control channel bits of serial transfer. 43 * SPI Clock rate - Control the bit rate of serial transfer. 44 * Flash command registers - Flexible to set the different command codes for 45 * different flash vendors in automatic mode. 46 * Dummy cycles- Allow users to add dummy cycles in receiving data path for 47 * timing tuning or extra pipelining registers. 48 * Flash address size- Define the size of Flash to enable the slave select output 49 * in automatic mode. 50 * 51 ***************************************************************************************** 52 * How to use SPI_Flash_Controller to Read/Program/Erase flash 53 ***************************************************************************************** 54 * To use the SPI_Flash_Controller to Read/Program/Erase flash, you can follow the steps 55 * below: 56 * 57 * 1. Enable SPIC clock by using RCC_PeriphClockCmd(APBPeriph_FLASH, APBPeriph_FLASH_CLOCK_XTAL, ENABLE) function. 58 * 59 * 2. Call Pinmux_SpicCtrl(PinLocation, ON) to configure SPIC pinmux. 60 * 61 * 3. Fill the variable flash_init_para of type FLASH_InitTypeDef with default parameters 62 * using one of the following functions according to flash vendor: 63 * flash vendor Struct Init Function 64 * Winbond FLASH_StructInit(&flash_init_para) 65 * Gigadevice FLASH_StructInit_GD(&flash_init_para) 66 * Micron FLASH_StructInit_Micron(&flash_init_para) 67 * MXIC FLASH_StructInit_MXIC(&flash_init_para) 68 * 69 * Note: (1)We support 4 flash chip vendors above in SDK. 70 * (2)If the flash chip type is Gigadevic and flash size is more than 2MB, 71 * you must set the FLASH_cmd_wr_status2 parameter in flash_init_para 72 * according to spec, because the Write Status Register1 command is 73 * different from write Status Register2 command. 74 * (3)If it is Micron flash chip, it is mandatory to set dummy cycles to 75 * Nonvolatile Configuration Register of flash. The number of dummy cycles is 76 * determined by Clock Frequency and Bit Mode according to spec. 77 * (4)If the flash chip type is Micron N25q00aa, you must set FLASH_cmd_chip_e 78 * parameter according to spec because it is different from default setting. 79 * 80 * 4. Initialize SPIC to designated BitMode using FLASH_Init(). 81 * 82 * 5. Enable Quad I/O by setting QuadEnable bit in FLASH status register. 83 * 84 * 6. Switch SPIC to higher clock rate using RCC_PeriphClockCmd(APBPeriph_FLASH, APBPeriph_FLASH_CLOCK_PLL, ENABLE) function. 85 * 86 * 7. Calibrate by calling FLASH_CalibrationNew() function. 87 * 88 * 8. Then you can Read/Program/Erase flash by calling corresponding functions. 89 * Remember to add flash_write_lock() function before those operations and 90 * flash_write_unlock() after them to protect them when FLASH XIP. 91 * 92 * Note: (1)If flash code has some updates when XIP, you need to flush cache by calling 93 * Cache_Flush() function. 94 * (2)When XIP, the flash initialization and calibration have already finished, 95 * you can Read/Program/Erase flash directly without excuting 1~6 steps described 96 * above. 97 * @endverbatim 98 */ 99 100 /* Exported types ------------------------------------------------------------*/ 101 102 /** @defgroup FLASH_Exported_Types FLASH Exported Types 103 * @{ 104 */ 105 106 /** 107 * @brief FLASH Init structure definition 108 */ 109 typedef struct { 110 u32 FLASH_Id; /*!< Specifies the flash vendor ID. 111 This parameter can be a value of @ref FLASH_VENDOR_ID_definitions */ 112 u8 FLASH_cur_bitmode; /*!< Specifies the current bitmode of SPIC. 113 This parameter can be a value of @ref FLASH_BIT_Mode_definitions */ 114 u8 FLASH_baud_rate; /*!< Specifies the spi_sclk divider value. The frequency of spi_sclk is derived from: 115 Frequency of spi_sclk = Frequency of oc_clk / (2 * FLASH_baud_rate) */ 116 u8 FLASH_baud_boot; /*!< Specifies the spi_sclk divider value for rom boot. The frequency of spi_sclk is derived from: 117 Frequency of spi_sclk = Frequency of oc_clk / (2 * FLASH_baud_rate) */ 118 u32 FLASH_cur_cmd; /*!< Specifies the current read cmd which is used to read data from flash 119 in current bitmode. */ 120 121 /* status bits define */ 122 u32 FLASH_QuadEn_bit; /*!< Specifies the QE bit in status register which is used to enable Quad I/O mode . */ 123 u32 FLASH_Busy_bit; /*!< Specifies the WIP(Write in Progress) bit in status register which indicates whether 124 the device is busy in program/erase/write status register progress. */ 125 u32 FLASH_WLE_bit; /*!< Specifies the WEL(Write Enable Latch) bit in status register which indicates whether 126 the device will accepts program/erase/write status register instructions*/ 127 u32 FLASH_Status2_exist; /*!< Specifies whether this flash chip has Status Register2 or not. 128 This parameter can be 0/1. 0 means it doesn't have Status Register2, 1 means 129 it has Status Register2.*/ 130 131 /* calibration data */ 132 u8 FLASH_rd_sample_phase_cal; /*!< Specifies the read sample phase obtained from calibration. this is cal sample phase get from high speed cal */ 133 u8 FLASH_rd_sample_phase; /*!< Specifies the read sample phase obtained from calibration. this is current sample phase */ 134 u8 FLASH_rd_dummy_cyle[3]; /*!< Specifies the read dummy cycle of different bitmode according to 135 flash datasheet*/ 136 137 /* valid R/W command set */ 138 u32 FLASH_rd_dual_o; /*!< Specifies dual data read cmd */ 139 u32 FLASH_rd_dual_io; /*!< Specifies dual data/addr read cmd */ 140 u32 FLASH_rd_quad_o; /*!< Specifies quad data read cmd */ 141 u32 FLASH_rd_quad_io; /*!< Specifies quad data/addr read cmd */ 142 u32 FLASH_wr_dual_i; /*!< Specifies dual data write cmd */ 143 u32 FLASH_wr_dual_ii; /*!< Specifies dual data/addr write cmd */ 144 u32 FLASH_wr_quad_i; /*!< Specifies quad data write cmd */ 145 u32 FLASH_wr_quad_ii; /*!< Specifies quad data/addr write cmd */ 146 u32 FALSH_dual_valid_cmd; /*!< Specifies valid cmd of dual bitmode to program/read flash in auto mode */ 147 u32 FALSH_quad_valid_cmd; /*!< Specifies valid cmd of quad bitmode to program/read flash in auto mode */ 148 149 /* other command set */ 150 u8 FLASH_cmd_wr_en; /*!< Specifies the Write Enable(WREN) instruction which is for setting WEL bit*/ 151 u8 FLASH_cmd_rd_id; /*!< Specifies the Read ID instruction which is for getting the identity of the flash divice.*/ 152 u8 FLASH_cmd_rd_status; /*!< Specifies the Read Status Register instruction which is for getting the status of flash */ 153 u8 FLASH_cmd_rd_status2; /*!< Specifies the Read Status Register2 instruction which is for getting the status2 of flash */ 154 u8 FLASH_cmd_wr_status; /*!< Specifies the Write Status Register instruction which is for setting the status register of flash */ 155 u8 FLASH_cmd_wr_status2; /*!< Specifies the Write Status Register2 instruction which is for setting the status register2 of flash. 156 In some flash chips, status2 write cmd != status1 write cmd, 157 like: GD25Q32C, GD25Q64C,GD25Q128C etc.*/ 158 u8 FLASH_cmd_chip_e; /*!< Specifies the Erase Chip instruction which is for erasing the whole chip*/ 159 u8 FLASH_cmd_block_e; /*!< Specifies the Erase Block instruction which is for erasing 64kB*/ 160 u8 FLASH_cmd_sector_e; /*!< Specifies the Erase Sector instruction which is for erasing 4kB*/ 161 u8 FLASH_cmd_pwdn_release; /*!< Specifies the Release from Deep Power Down instruction which is for exiting power down mode.*/ 162 u8 FLASH_cmd_pwdn; /*!< Specifies the Deep Power Down instruction which is for entering power down mode.*/ 163 164 /* debug log */ 165 u8 debug; /*!< Specifies whether or not to print debug log.*/ 166 167 /* new calibration */ 168 u8 phase_shift_idx; /*!< Specifies the phase shift idx in new calibration.*/ 169 170 u8 FLASH_addr_phase_len; /*!< Specifies the number of bytes in address phase (between command phase and write/read phase). 171 This parameter can be 0/1/2/3. 0 means 4-byte address mode in SPI Flash.*/ 172 u8 FLASH_pseudo_prm_en; /*!< Specifies whether SPIC enables SPIC performance read mode or not.*/ 173 u8 FLASH_pinmux; /*!< Specifies which pinmux is used. PINMUX_S0 or PINMUX_S1*/ 174 175 u32 FLASH_rd_fast_single; /*!< Specifies fast read cmd in auto mode.*/ 176 } FLASH_InitTypeDef; 177 /** 178 * @} 179 */ 180 181 182 /* Exported constants --------------------------------------------------------*/ 183 184 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 185 * @{ 186 */ 187 188 /** @defgroup FLASH_CLK_Div_definitions 189 * @{ 190 */ 191 #define FLASH_CLK_DIV2P0 0 192 #define FLASH_CLK_DIV2P5 1 193 #define FLASH_CLK_DIV3P0 2 194 #define FLASH_CLK_DIV3P5 3 195 #define FLASH_CLK_DIV4P0 4 196 /** 197 * @} 198 */ 199 200 /** @defgroup FLASH_BIT_Mode_definitions 201 * @{ 202 */ 203 #define SpicOneBitMode 0 204 #define SpicDualBitMode 1 205 #define SpicQuadBitMode 2 206 /** 207 * @} 208 */ 209 210 /** @defgroup FLASH_ERASE_Type_definitions 211 * @{ 212 */ 213 #define EraseChip 0 214 #define EraseBlock 1 215 #define EraseSector 2 216 /** 217 * @} 218 */ 219 220 /** @defgroup FLASH_WAIT_Type_definitions 221 * @{ 222 */ 223 #define WAIT_SPIC_BUSY 0 224 #define WAIT_FLASH_BUSY 1 225 #define WAIT_WRITE_DONE 2 226 #define WAIT_WRITE_EN 3 227 /** 228 * @} 229 */ 230 231 /** @defgroup SPIC_ADDR_PHASE_LEN_definitions 232 * @{ 233 */ 234 #define ADDR_3_BYTE 0x3 235 #define ADDR_4_BYTE 0x0 236 #define ADDR_3_BYTE_USER_PRM 0x0 237 #define ADDR_4_BYTE_USER_PRM 0x4 238 /** 239 * @} 240 */ 241 242 /** @defgroup WINBOND_W25Q16DV_Spec 243 * @{ 244 */ 245 #define FLASH_CMD_WREN 0x06 //write enable 246 #define FLASH_CMD_WRDI 0x04 //write disable 247 #define FLASH_CMD_WRSR 0x01 //write status register 248 #define FLASH_CMD_RDID 0x9F //read idenfication 249 #define FLASH_CMD_RDSR 0x05 //read status register 250 #define FLASH_CMD_RDSR2 0x35 //read status register-2 251 #define FLASH_CMD_READ 0x03 //read data 252 #define FLASH_CMD_FREAD 0x0B //fast read data 253 #define FLASH_CMD_RDSFDP 0x5A //Read SFDP 254 #define FLASH_CMD_RES 0xAB //Read Electronic ID 255 #define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID 256 #define FLASH_CMD_DREAD 0x3B //Double Output Mode command 257 #define FLASH_CMD_SE 0x20 //Sector Erase 258 #define FLASH_CMD_BE 0xD8 //0x52 //64K Block Erase 259 #define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7) 260 #define FLASH_CMD_PP 0x02 //Page Program 261 #define FLASH_CMD_DP 0xB9 //Deep Power Down 262 #define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down 263 #define FLASH_CMD_2READ 0xBB // 2 x I/O read command 264 #define FLASH_CMD_4READ 0xEB // 4 x I/O read command 265 #define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 266 #define FLASH_CMD_4PP 0x32 //quad page program //this is diff with MXIC 267 #define FLASH_CMD_FF 0xFF //Release Read Enhanced 268 #define FLASH_CMD_REMS2 0x92 // read ID for 2x I/O mode //this is diff with MXIC 269 #define FLASH_CMD_REMS4 0x94 // read ID for 4x I/O mode //this is diff with MXIC 270 #define FLASH_CMD_RDSCUR 0x48 // read security register //this is diff with MXIC 271 #define FLASH_CMD_WRSCUR 0x42 // write security register //this is diff with MXIC 272 273 #define FLASH_DM_CYCLE_2O 0x08 274 #define FLASH_DM_CYCLE_2IO 0x04 275 #define FLASH_DM_CYCLE_4O 0x08 276 #define FLASH_DM_CYCLE_4IO 0x06 277 278 #define FLASH_STATUS_BUSY ((u32)0x00000001) 279 #define FLASH_STATUS_WLE ((u32)0x00000002) 280 /** 281 * @} 282 */ 283 284 /** @defgroup WINBOND_W25Q256FV_Spec 285 * @{ 286 */ 287 288 #define FLASH_CMD_ENT_ADDR4B 0xB7 289 #define FLASH_CMD_EXT_ADDR4B 0xE9 290 291 /** 292 * @} 293 */ 294 295 /** @defgroup FLASH_VENDOR_ID_definitions 296 * @{ 297 */ 298 #define FLASH_ID_OTHERS 0 299 #define FLASH_ID_MXIC 1 300 #define FLASH_ID_WINBOND 2 301 #define FLASH_ID_MICRON 3 302 #define FLASH_ID_EON 4 303 #define FLASH_ID_GD 5 304 #define FLASH_ID_BOHONG 6 305 306 /** 307 * @} 308 */ 309 310 /** @defgroup FLASH_MANUFACTURER_ID_definitions 311 * @{ 312 */ 313 #define MANUFACTURER_ID_MXIC 0xC2 314 #define MANUFACTURER_ID_WINBOND 0xEF 315 #define MANUFACTURER_ID_MICRON 0x20 316 #define MANUFACTURER_ID_BOHONG 0x68 317 #define MANUFACTURER_ID_GD 0xC8 318 #define MANUFACTURER_ID_EON 0x1C 319 #define MANUFACTURER_ID_FM 0xA1 320 321 /** 322 * @} 323 */ 324 325 /** 326 * @} 327 */ 328 329 /* Exported functions --------------------------------------------------------*/ 330 /** @defgroup FLASH_Exported_Functions FLASH Exported Functions 331 * @{ 332 */ 333 _LONG_CALL_ void FLASH_Erase(u32 EraseType, u32 Address); 334 _LONG_CALL_ void FLASH_SetStatus(u8 Cmd, u32 Len, u8* Status); 335 _LONG_CALL_ void FLASH_SetStatusBits(u32 SetBits, u32 NewState); 336 _LONG_CALL_ void FLASH_WaitBusy(u32 WaitType); 337 _LONG_CALL_ void FLASH_WriteEn(void); 338 _LONG_CALL_ void FLASH_TxCmd(u8 cmd, u8 DataPhaseLen, u8* pData); 339 _LONG_CALL_ void FLASH_RxCmd(u8 cmd, u32 read_len, u8* read_data); 340 _LONG_CALL_ void FLASH_StructInit(FLASH_InitTypeDef* FLASH_InitStruct); 341 _LONG_CALL_ void FLASH_StructInit_Micron(FLASH_InitTypeDef* FLASH_InitStruct); 342 _LONG_CALL_ void FLASH_StructInit_MXIC(FLASH_InitTypeDef* FLASH_InitStruct); 343 _LONG_CALL_ void FLASH_StructInit_GD(FLASH_InitTypeDef* FLASH_InitStruct); 344 _LONG_CALL_ u8 FLASH_Init(u8 SpicBitMode); 345 _LONG_CALL_ void FLASH_SetSpiMode(FLASH_InitTypeDef *FLASH_InitStruct, u8 SpicBitMode); 346 _LONG_CALL_ void FLASH_DeepPowerDown(u32 NewState); 347 _LONG_CALL_ void FLASH_TxData256B(u32 StartAddr, u32 DataPhaseLen, u8* pData); 348 _LONG_CALL_ void FLASH_TxData12B(u32 StartAddr, u8 DataPhaseLen, u8* pData); 349 _LONG_CALL_ void FLASH_RxData(u8 cmd, u32 StartAddr, u32 read_len, u8* read_data); 350 _LONG_CALL_ u32 FLASH_Calibration(FLASH_InitTypeDef* FLASH_InitStruct, u8 SpicBitMode, u8 LineDelay); 351 352 _LONG_CALL_ u32 FLASH_ClockDiv(u8 Div); 353 _LONG_CALL_ u32 FLASH_CalibrationNew(FLASH_InitTypeDef* FLASH_InitStruct, u8 SpicBitMode, u8 Div, u8 CalStep, u8 LineDelay, u8 StartIdx); 354 _LONG_CALL_ u32 FLASH_CalibrationNewCmd(u32 NewStatus); 355 _LONG_CALL_ u32 FLASH_CalibrationPhaseIdx(u8 phase_idx); 356 _LONG_CALL_ u32 FLASH_CalibrationPhase(u8 phase_int, u8 phase_sel); 357 _LONG_CALL_ u32 FLASH_Calibration500MPSCmd(u32 NewStatus); 358 _LONG_CALL_ u32 FLASH_CalibrationInit(u8 CalibrationEnd); 359 _LONG_CALL_ void FLASH_ClockSwitch(u32 Source, u32 Protection); 360 _LONG_CALL_ int FLASH_WriteStream(u32 address, u32 len, u8 * data); 361 362 /** 363 * @} 364 */ 365 366 /** @defgroup FLASH_Exported_XIP_Functions FLASH Exported XIP Functions 367 * @note these functions will lock cpu when exec to forbit XIP, and flush cache after exec 368 * @{ 369 */ 370 void FLASH_Write_Lock(void); 371 void FLASH_Write_Unlock(void); 372 void FLASH_RxCmdXIP(u8 cmd, u32 read_len, u8* read_data); 373 void FLASH_SetStatusXIP(u8 Cmd, u32 Len, u8* Status); 374 void FLASH_SetStatusBitsXIP(u32 SetBits, u32 NewState); 375 void FLASH_TxData12BXIP(u32 StartAddr, u8 DataPhaseLen, u8* pData); 376 void FLASH_TxData256BXIP(u32 StartAddr, u32 DataPhaseLen, u8* pData); 377 void FLASH_EraseXIP(u32 EraseType, u32 Address); 378 void FLASH_EreaseDwordsXIP(u32 address, u32 dword_num); 379 void FLASH_Write_IPC_Int(VOID *Data, u32 IrqStatus, u32 ChanNum); 380 /** 381 * @} 382 */ 383 384 /* Registers Definitions --------------------------------------------------------*/ 385 /**************************************************************************//** 386 * @defgroup FLASH_Register_Definitions FLASH Register Definitions 387 * @{ 388 *****************************************************************************/ 389 390 /**************************************************************************//** 391 * @defgroup SPIC_CTRLR0 392 * @{ 393 *****************************************************************************/ 394 /******************** Bits definition for SPIC_CTRLR0 register *******************/ 395 #define BIT_CMD_CH(x) (((x) & 0x00000003) << 20) 396 #define BIT_DATA_CH(x) (((x) & 0x00000003) << 18) 397 #define BIT_ADDR_CH(x) (((x) & 0x00000003) << 16) 398 #define BIT_TMOD(x) (((x) & 0x00000003) << 8) 399 #define BIT_SCPOL (0x00000001 << 7) 400 #define BIT_SCPH (0x00000001 << 6) 401 /** @} */ 402 403 /**************************************************************************//** 404 * @defgroup SPIC_CTRLR1 405 * @{ 406 *****************************************************************************/ 407 /******************** Bits definition for SPIC_CTRLR1 register *******************/ 408 #define BIT_NDF(x) ((x) & 0xffff) 409 /** @} */ 410 411 /**************************************************************************//** 412 * @defgroup SPIC_SSIENR 413 * @{ 414 *****************************************************************************/ 415 /******************** Bits definition for SPIC_SSIENR register *******************/ 416 #define BIT_ATCK_CMD (0x00000001 << 1) 417 #define BIT_SPIC_EN (0x00000001) 418 /** @} */ 419 420 /**************************************************************************//** 421 * @defgroup SPIC_SER 422 * @{ 423 *****************************************************************************/ 424 /******************** Bits definition for SPIC_SER register *******************/ 425 #define BIT_SER (0x00000001) 426 /** @} */ 427 428 /**************************************************************************//** 429 * @defgroup SPIC_BAUDR 430 * @{ 431 *****************************************************************************/ 432 /******************** Bits definition for SPIC_BAUDR register *******************/ 433 #define BIT_SCKDV(x) ((x) & 0x0fff) 434 /** @} */ 435 436 /**************************************************************************//** 437 * @defgroup SPIC_SR 438 * @{ 439 *****************************************************************************/ 440 /******************** Bits definition for SPIC_SR register *******************/ 441 #define BIT_TXE (0x00000001 << 5) 442 #define BIT_RFF (0x00000001 << 4) 443 #define BIT_RFNE (0x00000001 << 3) 444 #define BIT_TFE (0x00000001 << 2) 445 #define BIT_TFNF (0x00000001 << 1) 446 #define BIT_BUSY (0x00000001) 447 /** @} */ 448 449 /**************************************************************************//** 450 * @defgroup SPIC_IMR 451 * @{ 452 *****************************************************************************/ 453 /******************** Bits definition for SPIC_IMR register *******************/ 454 #define BIT_TXSIM (0x00000001 << 9) 455 #define BIT_ACEIM (0x00000001 << 8) 456 #define BIT_BYEIM (0x00000001 << 7) 457 #define BIT_WBEIM (0x00000001 << 6) 458 #define BIT_FSEIM (0x00000001 << 5) 459 #define BIT_RXFIM (0x00000001 << 4) 460 #define BIT_RXOIM (0x00000001 << 3) 461 #define BIT_RXUIM (0x00000001 << 2) 462 #define BIT_TXOIM (0x00000001 << 1) 463 #define BIT_TXEIM (0x00000001) 464 /** @} */ 465 466 /**************************************************************************//** 467 * @defgroup SPIC_ISR 468 * @{ 469 *****************************************************************************/ 470 /******************** Bits definition for SPIC_ISR register *******************/ 471 #define BIT_TXSIS (0x00000001 << 9) 472 #define BIT_ACEIS (0x00000001 << 8) 473 #define BIT_BYEIS (0x00000001 << 7) 474 #define BIT_WBEIS (0x00000001 << 6) 475 #define BIT_FSEIS (0x00000001 << 5) 476 #define BIT_RXFIS (0x00000001 << 4) 477 #define BIT_RXOIS (0x00000001 << 3) 478 #define BIT_RXUIS (0x00000001 << 2) 479 #define BIT_TXOIS (0x00000001 << 1) 480 #define BIT_TXEIS (0x00000001) 481 /** @} */ 482 483 /**************************************************************************//** 484 * @defgroup SPIC_RISR 485 * @{ 486 *****************************************************************************/ 487 /******************** Bits definition for SPIC_RISR register *******************/ 488 #define BIT_ACEIR (0x00000001 << 8) 489 #define BIT_BYEIR (0x00000001 << 7) 490 #define BIT_WBEIR (0x00000001 << 6) 491 #define BIT_FSEIR (0x00000001 << 5) 492 #define BIT_RXFIR (0x00000001 << 4) 493 #define BIT_RXOIR (0x00000001 << 3) 494 #define BIT_RXUIR (0x00000001 << 2) 495 #define BIT_TXOIR (0x00000001 << 1) 496 #define BIT_TXEIR (0x00000001) 497 /** @} */ 498 499 /**************************************************************************//** 500 * @defgroup SPIC_CTRLR2 501 * @{ 502 *****************************************************************************/ 503 /******************** Bits definition for SPIC_CTRLR2 register *******************/ 504 #define BIT_FIFO_ENTRY(x) (((x) & 0x0000000f) << 4) 505 #define BIT_WR_SEQ (0x00000001 << 3) 506 #define BIT_WPN_DNUM (0x00000001 << 2) /* Indicate the WPn input pin of SPI Flash is connected to, 0(default): WP=spi_sout[2], 1:WP=spi_sout[3]. */ 507 #define BIT_WPN_SET (0x00000001 << 1) /* To implement write protect function. spi_wen_out and the bit of spi_sout which connects to WPN would be initial to 0. */ 508 #define BIT_SO_DUM (0x00000001) /* SO input pin of SPI Flash, 0: SO connects to spi_sout[0]. 1(default): SO connects to spi_sout[1].*/ 509 /** @} */ 510 511 /**************************************************************************//** 512 * @defgroup SPIC_ADDR_LENGTH 513 * @{ 514 *****************************************************************************/ 515 /******************** Bits definition for SPIC_ADDR_LENGTH register *******************/ 516 #define BIT_ADDR_PHASE_LENGTH(x) ((x) & 0x00000007) 517 /** @} */ 518 519 /**************************************************************************//** 520 * @defgroup SPIC_AUTO_LENGTH 521 * @{ 522 *****************************************************************************/ 523 /******************** Bits definition for SPIC_AUTO_LENGTH register *******************/ 524 #define BIT_CS_H_WR_DUM_LEN(x) (((x) & 0x0000000f) << 28) 525 #define BIT_CS_H_RD_DUM_LEN(x) (((x) & 0x00000003) << 26) 526 #define BIT_AUTO_DUM_LEN(x) (((x) & 0x000000ff) << 18) 527 #define BIT_AUTO_ADDR_LENGTH(x) (((x) & 0x00000003) << 16) 528 #define BIT_RD_DUMMY_LENGTH(x) (((x) & 0x00000fff)) 529 /** @} */ 530 531 /**************************************************************************//** 532 * @defgroup SPIC_VALID_CMD 533 * @{ 534 *****************************************************************************/ 535 /******************** Bits definition for SPIC_VALID_CMD register *******************/ 536 #define BIT_CTRLR0_CH (0x00000001 << 12) 537 #define BIT_PRM_EN (0x00000001 << 11) 538 #define BIT_WR_BLOCKING (0x00000001 << 9) 539 #define BIT_WR_QUAD_II (0x00000001 << 8) 540 #define BIT_WR_QUAD_I (0x00000001 << 7) 541 #define BIT_WR_DUAL_II (0x00000001 << 6) 542 #define BIT_WR_DUAL_I (0x00000001 << 5) 543 #define BIT_RD_QUAD_IO (0x00000001 << 4) 544 #define BIT_RD_QUAD_O (0x00000001 << 3) 545 #define BIT_RD_DUAL_IO (0x00000001 << 2) 546 #define BIT_RD_DUAL_I (0x00000001 << 1) 547 #define BIT_FRD_SINGEL (0x00000001) 548 #define SPIC_VALID_CMD_MASK (0x7fff) 549 550 #define DUAL_PRM_CYCLE_NUM 4 551 #define QUAD_PRM_CYCLE_NUM 2 552 /** @} */ 553 554 /** 555 * @} 556 */ 557 558 /** 559 * @} 560 */ 561 /** 562 * @} 563 */ 564 565 /* Other definations --------------------------------------------------------*/ 566 extern FLASH_InitTypeDef flash_init_para; 567 extern u32 SPIC_CALIB_PATTERN[2]; 568 569 typedef void (*FLASH_STRUCT_INIT_FUNC)(FLASH_InitTypeDef* FLASH_InitStruct); 570 571 #define SPIC_LOWSPEED_SAMPLE_PHASE 1 572 #endif //_RTL8710B_SPI_FLASH_H 573 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 574