1 /** 2 ****************************************************************************** 3 * @file rtl8721d_ssi.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the SPI firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8710B_SPI_H_ 20 #define _RTL8710B_SPI_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup SPI 27 * @brief SPI driver modules 28 * @{ 29 */ 30 31 /** @addtogroup SPI 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * SPI0: 37 * - Support Motorola SPI interface 38 * - Role: Master or Slave 39 * - Base Address: SPI0_DEV 40 * - Bus Clk: 100MHz 41 * - BaudRate: less than or equal to 50M 42 * - Transfer mode:Tx,Rx,TRx,EEPROM Read when configured as Master; TRx when configured as Slave 43 * - Data Frame Size: 4-16 bits supported 44 * - IRQ Number: SPI0_IRQ 45 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_TX 46 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI0_RX 47 * 48 * SPI1: 49 * - Support Motorola SPI interface 50 * - Role: Master 51 * - Base Address: SPI1_DEV 52 * - Bus Clk: 50MHz 53 * - BaudRate: less than or equal to 25M 54 * - Transfer mode:Tx,Rx,TRx,EEPROM Read 55 * - Data Frame Size: 4-16 bits supported 56 * - IRQ Number: SPI1_IRQ 57 * - GDMA TX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_TX 58 * - GDMA RX handshake interface: GDMA_HANDSHAKE_INTERFACE_SPI1_RX 59 * 60 ***************************************************************************************** 61 * How to use Normal SPI 62 ***************************************************************************************** 63 * To use the SPI in DMA mode, the following steps are mandatory: 64 * 65 * 1. Enable peripheral clock using the following functions: 66 * -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0; 67 * -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1; 68 * 69 * 2. Configure the SPIx pinmux: 70 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master; 71 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave; 72 * 73 * 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize, 74 * Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using 75 * SSI_StructInit() and change some parameters if needed 76 * 77 * 4. Init Hardware use step3 parameters: 78 * SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct) 79 * 80 * 5. Enable the SPI: 81 * SSI_Cmd() 82 * 83 * 6. When using poll: 84 * -Using SSI_Writeable() function to make sure that the transmit FIFO is not full, 85 * then using SSI_WriteData() function to send data 86 * 87 * -Using SSI_Readable() function to make sure that the receive FIFO is not empty, 88 * then using SSI_ReadData() function to receive data 89 * 90 * 7. Enable the NVIC and the corresponding interrupt using following function if you need 91 * to use interrupt mode. 92 * -SSI_INTConfig(): SPI IRQ Mask set 93 * -InterruptRegister(): register the SPI irq handler 94 * -InterruptEn(): Enable the NVIC interrupt and set irq priority 95 * 96 * 97 * @note in SPI_Exported_Functions group, these functions below are about Interrupts 98 * and flags management: 99 * -SSI_GetIsr() 100 * -SSI_GetRawIsr() 101 * -SSI_INTConfig() 102 * -SSI_SetRxFifoLevel() 103 * -SSI_SetTxFifoLevel() 104 * -SSI_SetIsrClean() 105 * 106 * 107 ***************************************************************************************** 108 * How to use SPI in DMA mode 109 ***************************************************************************************** 110 * To use the SPI in DMA mode, the following steps are mandatory: 111 * 112 * 1. Enable peripheral clock using the following functions: 113 * -RCC_PeriphClockCmd(APBPeriph_SPI0, APBPeriph_SPI0_CLOCK, ENABLE) for SPI0; 114 * -RCC_PeriphClockCmd(APBPeriph_SPI1, APBPeriph_SPI1_CLOCK, ENABLE) for SPI1; 115 * 116 * 2. Configure the SPIx pinmux: 117 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIM) when configured as Master; 118 * -Pinmux_Config(Pin_Num, PINMUX_FUNCTION_SPIS) when configured as Slave; 119 * 120 * 3. Program the Polarity,Phase,Transfer Mode,Baud Rate Prescaler,DataFrameSize, 121 * Interrupt TRx Threshold level,DMA TRx Threshold level and other parameters using 122 * SSI_StructInit() and change some parameters if needed 123 * 124 * 4. Init Hardware use step3 parameters: 125 * SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct) 126 * 127 * 5. Enable the SPI: 128 * SSI_Cmd() 129 * 130 * 6. GDMA related configurations(DMA burst size/source address/destination address/block size etc). 131 * 132 * 7. Active the SPI DMA TX/RX using SSI_SetDmaEnable() function. 133 * 134 * @note in SPI_Exported_Functions group, these functions below are about DMA: 135 * -SSI_SetDmaEnable() 136 * -SSI_SetDmaLevel() 137 * 138 ***************************************************************************************** 139 * @endverbatim 140 */ 141 142 /* Exported Types --------------------------------------------------------*/ 143 /** @defgroup SPI_Exported_Types SPI Exported Types 144 * @{ 145 */ 146 147 /** 148 * @brief SPI Init structure definition 149 */ 150 typedef struct 151 { 152 u32 SPI_DmaRxDataLevel; /*!< Specifies the DMA receive data level. 153 The dma_rx_req is generated when the number of valid data entries in the 154 receive FIFO is equal to or above this field value+1,and RDMAE=1. 155 @note For Amebaz, the value range of this parameter should be 0 to 63,because 156 the depth of Rx FIFO is 64. */ 157 158 u32 SPI_DmaTxDataLevel; /*!< Specifies the DMA transmit data level. 159 The dma_tx_req is generated when the number of valid data entries in the 160 transmit FIFO is equal to or below this field value,and TDMAE=1. 161 @note For Amebaz, the value range of this parameter should be 0 to 63,because 162 the depth of Rx FIFO is 64. */ 163 164 u32 SPI_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level. 165 This Parameter controls the level of entries(or above) at which the receive FIFO controller 166 triggers an interrupt.When the number of receive FIFO entries is greater than or equal to this 167 value +1,the receive FIFO full interrupt is triggered. 168 @note For Amebaz, the value range of this parameter should be 0 to 63,because the depth 169 of Rx FIFO is 64. */ 170 171 u32 SPI_TxThresholdLevel; /*!< Specifies the transmit FIFO threshold level. 172 This Parameter controls the level of entries (or below) at which the transmit FIFO controller 173 triggers an interrupt.When the number of transmit FIFO entries is less than or equal to this 174 value,the transmit FIFO empty interrupt is triggered. 175 @note For Amebaz, the value range of this parameter should be 0 to 63,because of the depth 176 of Rx FIFO is 64. */ 177 178 u32 SPI_SlaveSelectEnable; /*!< Set the slave select enable flag. 179 This Parameter controls which slave to be selected by master,each bit in SER register 180 corresponds to a slave select line(ss_x_n) from spi master. 181 @note The default vlaue of this parameter is 0,and one slave is selected.if more slaves to be selected, 182 you may use SW way to do this.And this parameter is used only when the device is master. */ 183 184 u32 SPI_ClockDivider; /*!< Specifies the SPI Baud Rate. 185 The value of sclk_out equals to ssi_clk devides the value of this parameter 186 @note The LSB for this field is always set to 0 and is unaffected by a write operation,which ensures 187 an even value is held. */ 188 189 u32 SPI_DataFrameNumber; /*!< Specifies the number of data frames master wants to receive . 190 When TMOD=10 or TMOD=11,Ctrl1 register uses this value to set the number of data frames to 191 be continuous received. 192 @note The value of this parameter should be set to the number of data frames that to be received 193 minus one.And this parameter is used only when the device is master. */ 194 195 u32 SPI_DataFrameFormat; /*!< Selects which serial protocol transfers the data . 196 This parameter can be a value of @ref SPI_Frame_Format_definitions. */ 197 198 u32 SPI_DataFrameSize; /*!< Selects the data frame length . 199 This parameter can be a value of @ref SPI_Data_Frame_Size_definitions. 200 @note Need to right-justify transmit data before writting into the transmit FIFO 201 The transmit logic ignores the upper unused bits when transmitting the data. */ 202 203 u32 SPI_InterruptMask; /*!< Specifies which interrupt to be enable. 204 Each bit in this parameter corresponds to a specific interrupt.*/ 205 206 u32 SPI_Role; /*!< Specifies the role of SPI device. 207 This parameter can be a value of @ref SPI_ROLE_definitions. . */ 208 209 u32 SPI_SclkPhase; /*!< Specifies the serial clock phase. 210 When SPI_SclkPhase = 0, data are captured on the first edge of the serial clock. When SPI_SclkPhase = 1, 211 the serial clock starts toggling one cycle after the slave select line is activated, and data 212 are captured on the second edge of the serial clock. 213 This parameter can be a value of @ref SPI_SCPH_definitions. 214 @note Valid when the frame format(FRF) is set to Motorola SPI. */ 215 216 u32 SPI_SclkPolarity; /*!< Specifies the serial clock polarity. 217 When SPI_SclkPolarity = 0, the serial clock remains low when idle. When SPI_SclkPolarity = 1, 218 the serial clock remains high when idle. 219 This parameter can be a value of @ref SPI_SCPOL_definitions. 220 @note Valid when the frame format(FRF) is set to Motorola SPI.*/ 221 222 u32 SPI_TransferMode; /*!< Selects the mode of transfer for serial communication. 223 This parameter can be a value of @ref SPI_TMOD_definitions. 224 @note This transfer mode is only valid when the DW_apb_ssi is configured as a master device.*/ 225 226 u32 SPI_MicrowireControlFrameSize; /*!< Selects the length of the control word for the Microwire frame format. 227 This parameter can be a value of @ref SPI_MW_Control_Frame_Size_definitions. */ 228 229 u32 SPI_MicrowireDirection; /*!< Specifies of the data word when the Microwire serial protocol is used. 230 This parameter can be a value of @ref SPI_MW_Direction_definitions. */ 231 232 u32 SPI_MicrowireHandshaking; /*!< Specifies Microwire Handshaking. 233 This parameter can be a value of @ref SPI_MW_Handshake_Enable_definitions. */ 234 235 u32 SPI_MicrowireTransferMode; /*!< Specifies Microwire Transfer Mode. 236 This parameter can be a value of @ref SPI_MW_TMOD_definitions. */ 237 }SSI_InitTypeDef; 238 239 /** 240 * @} 241 */ 242 243 /* Exported constants --------------------------------------------------------*/ 244 245 /** @defgroup SPI_Exported_Constants SPI Exported Constants 246 * @{ 247 */ 248 249 /** @defgroup SPI_TMOD_definitions 250 * @{ 251 */ 252 #define TMOD_TR (0) 253 #define TMOD_TO (1) 254 #define TMOD_RO (2) 255 #define TMOD_EEPROM_R (3) 256 /** 257 * @} 258 */ 259 260 /** @defgroup SPI_SCPOL_definitions 261 * @{ 262 */ 263 #define SCPOL_INACTIVE_IS_LOW (0) 264 #define SCPOL_INACTIVE_IS_HIGH (1) 265 /** 266 * @} 267 */ 268 269 /** @defgroup SPI_SCPH_definitions 270 * @{ 271 */ 272 #define SCPH_TOGGLES_IN_MIDDLE (0) 273 #define SCPH_TOGGLES_AT_START (1) 274 /** 275 * @} 276 */ 277 278 /** @defgroup SPI_Data_Frame_Size_definitions 279 * @{ 280 */ 281 #define DFS_4_BITS (3) 282 #define DFS_5_BITS (4) 283 #define DFS_6_BITS (5) 284 #define DFS_7_BITS (6) 285 #define DFS_8_BITS (7) 286 #define DFS_9_BITS (8) 287 #define DFS_10_BITS (9) 288 #define DFS_11_BITS (10) 289 #define DFS_12_BITS (11) 290 #define DFS_13_BITS (12) 291 #define DFS_14_BITS (13) 292 #define DFS_15_BITS (14) 293 #define DFS_16_BITS (15) 294 /** 295 * @} 296 */ 297 298 /** @defgroup SPI_SS_TOGGLE_PHASE_definitions 299 * @{ 300 */ 301 #define SPI_SS_NOT_TOGGLE (0) 302 #define SPI_SS_TOGGLE (1) 303 /** 304 * @} 305 */ 306 307 /** @defgroup SPI_MW_Control_Frame_Size_definitions 308 * @{ 309 */ 310 #define CFS_1_BIT (0) 311 #define CFS_2_BITS (1) 312 #define CFS_3_BITS (2) 313 #define CFS_4_BITS (3) 314 #define CFS_5_BITS (4) 315 #define CFS_6_BITS (5) 316 #define CFS_7_BITS (6) 317 #define CFS_8_BITS (7) 318 #define CFS_9_BITS (8) 319 #define CFS_10_BITS (9) 320 #define CFS_11_BITS (10) 321 #define CFS_12_BITS (11) 322 #define CFS_13_BITS (12) 323 #define CFS_14_BITS (13) 324 #define CFS_15_BITS (14) 325 #define CFS_16_BITS (15) 326 /** 327 * @} 328 */ 329 330 /** @defgroup SPI_ROLE_definitions 331 * @{ 332 */ 333 #define SSI_SLAVE (0) 334 #define SSI_MASTER (1) 335 /** 336 * @} 337 */ 338 339 /** @defgroup SPI_Frame_Format_definitions 340 * @{ 341 */ 342 #define FRF_MOTOROLA_SPI (0) 343 #define FRF_TI_SSP (1) 344 #define FRF_NS_MICROWIRE (2) 345 #define FRF_RSVD (3) 346 /** 347 * @} 348 */ 349 350 /** @defgroup SPI_DMA_Control_definitions 351 * @{ 352 */ 353 #define SSI_NODMA (0) 354 #define SSI_RXDMA_ENABLE (1) 355 #define SSI_TXDMA_ENABLE (2) 356 #define SSI_TRDMA_ENABLE (3) 357 /** 358 * @} 359 */ 360 361 /** @defgroup SPI_MW_Handshake_Enable_definitions 362 * @{ 363 */ 364 #define MW_HANDSHAKE_DISABLE (0) 365 #define MW_HANDSHAKE_ENABLE (1) 366 /** 367 * @} 368 */ 369 370 /** @defgroup SPI_MW_Direction_definitions 371 * @{ 372 */ 373 #define MW_DIRECTION_SLAVE_TO_MASTER (0) 374 #define MW_DIRECTION_MASTER_TO_SLAVE (1) 375 /** 376 * @} 377 */ 378 379 /** @defgroup SPI_MW_TMOD_definitions 380 * @{ 381 */ 382 #define MW_TMOD_NONSEQUENTIAL (0) 383 #define MW_TMOD_SEQUENTIAL (1) 384 /** 385 * @} 386 */ 387 388 /** @defgroup SPI_FIFO_depth_definitions 389 * @{ 390 */ 391 #define SSI_TX_FIFO_DEPTH (64) 392 #define SSI_RX_FIFO_DEPTH (64) 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 401 /* Exported functions --------------------------------------------------------*/ 402 /** @defgroup SPI_Exported_Functions SPI Exported Functions 403 * @{ 404 */ 405 /** @defgroup SPI_Exported_Normal_Functions SPI Exported Normal Functions 406 * @{ 407 */ 408 _LONG_CALL_ void SSI_Cmd(SPI_TypeDef *spi_dev, u32 NewStaus); 409 _LONG_CALL_ void SSI_SetSclkPolarity(SPI_TypeDef *spi_dev, u32 SclkPolarity); 410 _LONG_CALL_ void SSI_SetSclkPhase(SPI_TypeDef *spi_dev, u32 SclkPhase); 411 _LONG_CALL_ void SSI_WriteData(SPI_TypeDef *spi_dev, u32 value); 412 _LONG_CALL_ VOID SSI_INTConfig(SPI_TypeDef* spi_dev, u32 SSI_IT, u32 newState); 413 _LONG_CALL_ void SSI_SetRxFifoLevel(SPI_TypeDef *spi_dev, u32 RxThresholdLevel); 414 _LONG_CALL_ void SSI_SetTxFifoLevel(SPI_TypeDef *spi_dev, u32 TxThresholdLevel); 415 _LONG_CALL_ void SSI_SetSlaveEnable(SPI_TypeDef *spi_dev, u32 SlaveIndex); 416 _LONG_CALL_ u32 SSI_Busy(SPI_TypeDef *spi_dev); 417 _LONG_CALL_ u32 SSI_Writeable(SPI_TypeDef *spi_dev); 418 _LONG_CALL_ u32 SSI_Readable(SPI_TypeDef *spi_dev); 419 _LONG_CALL_ u32 SSI_GetRxCount(SPI_TypeDef *spi_dev); 420 _LONG_CALL_ u32 SSI_GetTxCount(SPI_TypeDef *spi_dev); 421 _LONG_CALL_ u32 SSI_GetStatus(SPI_TypeDef *spi_dev); 422 _LONG_CALL_ u32 SSI_GetIsr(SPI_TypeDef *spi_dev); 423 _LONG_CALL_ u32 SSI_ReadData(SPI_TypeDef *spi_dev); 424 _LONG_CALL_ u32 SSI_ReceiveData(SPI_TypeDef *spi_dev, void* RxData, u32 Length); 425 _LONG_CALL_ u32 SSI_SendData(SPI_TypeDef *spi_dev, void* TxData, u32 Length, u32 Role); 426 _LONG_CALL_ u32 SSI_GetRawIsr(SPI_TypeDef *spi_dev); 427 _LONG_CALL_ u32 SSI_GetSlaveEnable(SPI_TypeDef *spi_dev); 428 _LONG_CALL_ u32 SSI_GetDataFrameSize(SPI_TypeDef *spi_dev); 429 _LONG_CALL_ void SSI_SetSampleDelay(SPI_TypeDef *spi_dev, u32 SampleDelay); 430 _LONG_CALL_ void SSI_Init(SPI_TypeDef *spi_dev, SSI_InitTypeDef *SSI_InitStruct); 431 _LONG_CALL_ void SSI_StructInit(SSI_InitTypeDef* SSI_InitStruct); 432 _LONG_CALL_ void SSI_SetDataFrameSize(SPI_TypeDef *spi_dev, u32 DataFrameSize); 433 _LONG_CALL_ void SSI_SetBaud(SPI_TypeDef *SPIx, u32 BaudRate, u32 IpClk); 434 _LONG_CALL_ void SSI_SetIsrClean(SPI_TypeDef *spi_dev, u32 InterruptStatus); 435 _LONG_CALL_ void SSI_SetReadLen(SPI_TypeDef *spi_dev, u32 DataFrameNumber); 436 /** 437 * @} 438 */ 439 440 /** @defgroup SPI_Exported_DMA_Functions SPI Exported DMA Functions 441 * @{ 442 */ 443 _LONG_CALL_ BOOL SSI_TXGDMA_Init(u32 Index, PGDMA_InitTypeDef GDMA_InitStruct, void *CallbackData, 444 IRQ_FUN CallbackFunc, u8 *pTxData, u32 Length); 445 _LONG_CALL_ BOOL SSI_RXGDMA_Init(u8 Index, GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, 446 IRQ_FUN CallbackFunc, u8 *pRxData, u32 Length); 447 _LONG_CALL_ void SSI_SetDmaEnable(SPI_TypeDef *spi_dev, u32 newState, u32 Mask); 448 _LONG_CALL_ void SSI_SetDmaLevel(SPI_TypeDef *spi_dev, u32 TxLeve, u32 RxLevel); 449 _LONG_CALL_ void SSI_SetBaudDiv(SPI_TypeDef *spi_dev, u32 ClockDivider); 450 _LONG_CALL_ void SSI_SetRole(SPI_TypeDef *spi_dev, u32 role); 451 452 /** 453 * @} 454 */ 455 456 /** 457 * @} 458 */ 459 460 461 462 /* Registers Definitions --------------------------------------------------------*/ 463 /**************************************************************************//** 464 * @defgroup SPI_Register_Definitions SPI Register Definitions 465 * @{ 466 *****************************************************************************/ 467 468 /**************************************************************************//** 469 * @defgroup SPI_CTRLR0 470 * @{ 471 *****************************************************************************/ 472 #define BIT_CTRLR0_DFS ((u32)0x0000000F) 473 #define BIT_CTRLR0_FRF ((u32)0x00000003 << 4) 474 #define BIT_CTRLR0_SCPH ((u32)0x00000001 << 6) 475 #define BIT_CTRLR0_SCPOL ((u32)0x00000001 << 7) 476 #define BIT_CTRLR0_TMOD ((u32)0x00000003 << 8) 477 #define BIT_CTRLR0_SLV_OE ((u32)0x00000001 << 10) 478 #define BIT_CTRLR0_SRL ((u32)0x00000001 << 11) 479 #define BIT_CTRLR0_CFS ((u32)0x0000000F << 12) 480 #define BIT_CTRLR0_TXBYTESWP ((u32)0x00000001 << 21) 481 #define BIT_CTRLR0_TXBITSWP ((u32)0x00000001 << 22) 482 #define BIT_CTRLR0_RXBYTESWP ((u32)0x00000001 << 23) 483 #define BIT_CTRLR0_RXBITSWP ((u32)0x00000001 << 24) 484 #define BIT_CTRLR0_SSTOGGLE ((u32)0x00000001 << 31) 485 /** @} */ 486 487 /**************************************************************************//** 488 * @defgroup SPI_CTRLR1 489 * @{ 490 *****************************************************************************/ 491 #define BIT_CTRLR1_NDF ((u32)0x0000FFFF) 492 /** @} */ 493 494 /**************************************************************************//** 495 * @defgroup SPI_SSIENR 496 * @{ 497 *****************************************************************************/ 498 #define BIT_SSIENR_SSI_EN ((u32)0x00000001) 499 /** @} */ 500 501 /**************************************************************************//** 502 * @defgroup SPI_MWCR 503 * @{ 504 *****************************************************************************/ 505 #define BIT_MWCR_MWMOD ((u32)0x00000001) 506 #define BIT_MWCR_MDD ((u32)0x00000001 << 1) 507 #define BIT_MWCR_MHS ((u32)0x00000001 << 2) 508 /** @} */ 509 510 /**************************************************************************//** 511 * @defgroup SPI_SER 512 * @{ 513 *****************************************************************************/ 514 #define BIT_SER_SER ((u32)0x0000FFFF) 515 /** @} */ 516 517 /**************************************************************************//** 518 * @defgroup SPI_BAUDR 519 * @{ 520 *****************************************************************************/ 521 #define BIT_BAUDR_SCKDV ((u32)0x0000FFFF) 522 /** @} */ 523 524 /**************************************************************************//** 525 * @defgroup SPI_TXFLTR 526 * @{ 527 *****************************************************************************/ 528 #define BIT_TXFTLR_TFT ((u32)0x0000003F)//(TX_ABW-1):0 529 /** @} */ 530 531 /**************************************************************************//** 532 * @defgroup SPI_RXFLTR 533 * @{ 534 *****************************************************************************/ 535 #define BIT_RXFTLR_RFT ((u32)0x0000003F) // (RX_ABW-1):0 536 /** @} */ 537 538 /**************************************************************************//** 539 * @defgroup SPI_TXFLR 540 * @{ 541 *****************************************************************************/ 542 #define BIT_MASK_TXFLR_TXTFL ((u32)0x0000007F) // (TX_ABW):0 543 /** @} */ 544 545 /**************************************************************************//** 546 * @defgroup SPI_RXFLR 547 * @{ 548 *****************************************************************************/ 549 #define BIT_MASK_RXFLR_RXTFL ((u32)0x0000007F) // (RX_ABW):0 550 /** @} */ 551 552 /**************************************************************************//** 553 * @defgroup SPI_SR 554 * @{ 555 *****************************************************************************/ 556 #define BIT_SR_BUSY ((u32)0x00000001) 557 #define BIT_SR_TFNF ((u32)0x00000001 << 1) 558 #define BIT_SR_TFE ((u32)0x00000001 << 2) 559 #define BIT_SR_RFNE ((u32)0x00000001 << 3) 560 #define BIT_SR_RFF ((u32)0x00000001 << 4) 561 #define BIT_SR_TXE ((u32)0x00000001 << 5) 562 #define BIT_SR_DCOL ((u32)0x00000001 << 6) 563 /** @} */ 564 565 /**************************************************************************//** 566 * @defgroup SPI_IMR 567 * @{ 568 *****************************************************************************/ 569 #define BIT_IMR_TXEIM ((u32)0x00000001) 570 #define BIT_IMR_TXOIM ((u32)0x00000001 << 1) 571 #define BIT_IMR_RXUIM ((u32)0x00000001 << 2) 572 #define BIT_IMR_RXOIM ((u32)0x00000001 << 3) 573 #define BIT_IMR_RXFIM ((u32)0x00000001 << 4) 574 #define BIT_IMR_MSTIM ((u32)0x00000001 << 5) /*Master only*/ 575 #define BIT_IMR_FAEIM ((u32)0x00000001 << 5) /*Slave only*/ 576 #define BIT_IMR_TXUIM ((u32)0x00000001 << 6) /*Slave only*/ 577 #define BIT_IMR_SSRIM ((u32)0x00000001 << 7) /*Slave only*/ 578 /** @} */ 579 580 /**************************************************************************//** 581 * @defgroup SPI_ISR 582 * @{ 583 *****************************************************************************/ 584 #define BIT_ISR_TXEIS ((u32)0x00000001) 585 #define BIT_ISR_TXOIS ((u32)0x00000001 << 1) 586 #define BIT_ISR_RXUIS ((u32)0x00000001 << 2) 587 #define BIT_ISR_RXOIS ((u32)0x00000001 << 3) 588 #define BIT_ISR_RXFIS ((u32)0x00000001 << 4) 589 #define BIT_ISR_MSTIS ((u32)0x00000001 << 5) /*Master only*/ 590 #define BIT_ISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/ 591 #define BIT_ISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/ 592 #define BIT_ISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/ 593 /** @} */ 594 595 /**************************************************************************//** 596 * @defgroup SPI_RISR 597 * @{ 598 *****************************************************************************/ 599 #define BIT_RISR_TXEIR ((u32)0x00000001) 600 #define BIT_RISR_TXOIR ((u32)0x00000001 << 1) 601 #define BIT_RISR_RXUIR ((u32)0x00000001 << 2) 602 #define BIT_RISR_RXOIR ((u32)0x00000001 << 3) 603 #define BIT_RISR_RXFIR ((u32)0x00000001 << 4) 604 #define BIT_RISR_MSTIR ((u32)0x00000001 << 5) /*Master only*/ 605 #define BIT_RISR_FAEIS ((u32)0x00000001 << 5) /*Slave only*/ 606 #define BIT_RISR_TXUIS ((u32)0x00000001 << 6) /*Slave only*/ 607 #define BIT_RISR_SSRIS ((u32)0x00000001 << 7) /*Slave only*/ 608 /** @} */ 609 610 /**************************************************************************//** 611 * @defgroup SPI_DMACR 612 * @{ 613 *****************************************************************************/ 614 #define BIT_SHIFT_DMACR_RDMAE ((u32)0x00000001) 615 #define BIT_SHIFT_DMACR_TDMAE ((u32)0x00000001 << 1) 616 /** @} */ 617 618 /**************************************************************************//** 619 * @defgroup SPI_DMATDLR 620 * @{ 621 *****************************************************************************/ 622 #define BIT_DMATDLR_DMATDL ((u32)0x0000003F) // (TX_ABW-1):0 623 /** @} */ 624 625 /**************************************************************************//** 626 * @defgroup SPI_DMARDLR 627 * @{ 628 *****************************************************************************/ 629 #define BIT_DMARDLR_DMARDL ((u32)0x0000003F )// (RX_ABW-1):0 630 /** @} */ 631 632 /**************************************************************************//** 633 * @defgroup SPI_DR 634 * @{ 635 *****************************************************************************/ 636 #define BIT_DR_DR ((u32)0x0000FFFF) 637 /** @} */ 638 639 /**************************************************************************//** 640 * @defgroup SPI_RX_SAMPLE_DELAY 641 * @{ 642 *****************************************************************************/ 643 #define BIT_RX_SAMPLE_DELAY ((u32)0x000000FF) 644 /** @} */ 645 /** @} */ 646 647 /** 648 * @} 649 */ 650 651 /** 652 * @} 653 */ 654 655 /* Other Definitions --------------------------------------------------------*/ 656 typedef struct 657 { 658 SPI_TypeDef* SPIx; 659 u32 Tx_HandshakeInterface; 660 u32 Rx_HandshakeInterface; 661 IRQn_Type IrqNum; 662 } SPI_DevTable; 663 664 extern const SPI_DevTable SPI_DEV_TABLE[2]; 665 666 #define SPI_SLAVE_TXERR_WORK_AROUND 1 667 668 #endif //_RTL8710B_SPI_H_ 669 670 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 671